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* [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds
@ 2021-04-18 22:50 Philippe Mathieu-Daudé
  2021-04-18 22:50 ` [PATCH v2 01/29] target/mips: Simplify meson TCG rules Philippe Mathieu-Daudé
                   ` (29 more replies)
  0 siblings, 30 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-18 22:50 UTC (permalink / raw)
  To: qemu-devel
  Cc: Aleksandar Rikalo, Huacai Chen, Richard Henderson,
	Philippe Mathieu-Daudé,
	Aurelien Jarno

TL;DR:\r
\r
This series restrict TCG-specific objects by moving them to\r
the tcg/ subdir. Code is moved around to satisfy 3 cases:\r
{ generic sysemu / tcg sysemu / tcg user}.\r
\r
Since v1:\r
- Addressed Richard review comments\r
- Added Richard R-b tag\r
\r
Missing review: 5, 7, 8, 17, 18, 23\r
\r
Hi,\r
\r
This series move the MIPS TCG files under target/mips/tcg/.\r
tcg/ is split into {sysemu and user}, and code common to\r
both user/sysemu is left under tcg/ root.\r
\r
Non-user code is moved to sysemu/ (common to TCG and KVM).\r
\r
- Patches 1 & 10 are Meson generic\r
- Patches 2 to 9 move generic symbols around to satisfly KVM linking\r
- Patch 11 introduces tcg-internal.h where we'll move TCG specific\r
  prototypes from the current big internal.h\r
- Patches 12-27 move code by topic (first user, then sysemu, then tcg)\r
- Patch 28 restrict TCG specific machines to TCG (to actually\r
  only build malta/loongson3-virt machines when restricted to KVM)\r
- Patch 29 finally add a CI job with "KVM-only" config:\r
  https://gitlab.com/philmd/qemu/-/jobs/1189874868 (12min 5sec)\r
\r
Diffstat is not that bad, and many #ifdef'ry removed.\r
\r
Please review,\r
\r
Phil.\r
\r
Based-on: <20210413081008.3409459-1-f4bug@amsat.org>\r
          "exec: Remove accel/tcg/ from include paths"\r
\r
Philippe Mathieu-Daudé (29):\r
  target/mips: Simplify meson TCG rules\r
  target/mips: Move IEEE rounding mode array to new source file\r
  target/mips: Move msa_reset() to new source file\r
  target/mips: Make CPU/FPU regnames[] arrays global\r
  target/mips: Optimize CPU/FPU regnames[] arrays\r
  target/mips: Restrict mips_cpu_dump_state() to cpu.c\r
  target/mips: Turn printfpr() macro into a proper function\r
  target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h"\r
  target/mips: Extract load/store helpers to ldst_helper.c\r
  meson: Introduce meson_user_arch source set for arch-specific\r
    user-mode\r
  target/mips: Introduce tcg-internal.h for TCG specific declarations\r
  target/mips: Add simple user-mode mips_cpu_do_interrupt()\r
  target/mips: Add simple user-mode mips_cpu_tlb_fill()\r
  target/mips: Move cpu_signal_handler definition around\r
  target/mips: Move sysemu specific files under sysemu/ subfolder\r
  target/mips: Move physical addressing code to sysemu/physaddr.c\r
  target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG\r
  target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder\r
  target/mips: Restrict mmu_init() to TCG\r
  target/mips: Move tlb_helper.c to tcg/sysemu/\r
  target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope\r
  target/mips: Move Special opcodes to tcg/sysemu/special_helper.c\r
  target/mips: Move helper_cache() to tcg/sysemu/special_helper.c\r
  target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c\r
  target/mips: Move exception management code to exception.c\r
  target/mips: Move CP0 helpers to sysemu/cp0.c\r
  target/mips: Move TCG source files under tcg/ sub directory\r
  hw/mips: Restrict non-virtualized machines to TCG\r
  gitlab-ci: Add KVM mips64el cross-build jobs\r
\r
 meson.build                                  |    6 +\r
 target/mips/helper.h                         |  183 +--\r
 target/mips/internal.h                       |  106 +-\r
 target/mips/tcg/tcg-internal.h               |   64 +\r
 target/mips/{ => tcg}/msa_helper.h.inc       |    0\r
 target/mips/tcg/sysemu_helper.h.inc          |  185 +++\r
 target/mips/{ => tcg}/mips32r6.decode        |    0\r
 target/mips/{ => tcg}/mips64r6.decode        |    0\r
 target/mips/{ => tcg}/msa32.decode           |    0\r
 target/mips/{ => tcg}/msa64.decode           |    0\r
 target/mips/{ => tcg}/tx79.decode            |    0\r
 target/mips/cpu.c                            |  311 ++---\r
 target/mips/fpu.c                            |   25 +\r
 target/mips/msa.c                            |   60 +\r
 target/mips/op_helper.c                      | 1210 ------------------\r
 target/mips/{ => sysemu}/addr.c              |    0\r
 target/mips/sysemu/cp0.c                     |  123 ++\r
 target/mips/{ => sysemu}/cp0_timer.c         |    0\r
 target/mips/{ => sysemu}/machine.c           |    0\r
 target/mips/sysemu/physaddr.c                |  257 ++++\r
 target/mips/{ => tcg}/dsp_helper.c           |    0\r
 target/mips/tcg/exception.c                  |  169 +++\r
 target/mips/{ => tcg}/fpu_helper.c           |    8 -\r
 target/mips/tcg/ldst_helper.c                |  304 +++++\r
 target/mips/{ => tcg}/lmmi_helper.c          |    0\r
 target/mips/{ => tcg}/msa_helper.c           |   36 -\r
 target/mips/{ => tcg}/msa_translate.c        |    0\r
 target/mips/{ => tcg}/mxu_translate.c        |    0\r
 target/mips/tcg/op_helper.c                  |  421 ++++++\r
 target/mips/{ => tcg}/rel6_translate.c       |    0\r
 target/mips/{ => tcg/sysemu}/cp0_helper.c    |    0\r
 target/mips/{ => tcg/sysemu}/mips-semi.c     |    0\r
 target/mips/tcg/sysemu/special_helper.c      |  173 +++\r
 target/mips/{ => tcg/sysemu}/tlb_helper.c    |  612 +++++----\r
 target/mips/{ => tcg}/translate.c            |  104 +-\r
 target/mips/{ => tcg}/translate_addr_const.c |    0\r
 target/mips/{ => tcg}/tx79_translate.c       |    0\r
 target/mips/{ => tcg}/txx9_translate.c       |    0\r
 target/mips/tcg/user/tlb_helper.c            |   64 +\r
 .gitlab-ci.d/crossbuilds.yml                 |    8 +\r
 MAINTAINERS                                  |    3 +-\r
 hw/mips/meson.build                          |   11 +-\r
 target/mips/meson.build                      |   55 +-\r
 target/mips/sysemu/meson.build               |    7 +\r
 target/mips/tcg/meson.build                  |   35 +\r
 target/mips/tcg/sysemu/meson.build           |    6 +\r
 target/mips/tcg/user/meson.build             |    3 +\r
 47 files changed, 2407 insertions(+), 2142 deletions(-)\r
 create mode 100644 target/mips/tcg/tcg-internal.h\r
 rename target/mips/{ => tcg}/msa_helper.h.inc (100%)\r
 create mode 100644 target/mips/tcg/sysemu_helper.h.inc\r
 rename target/mips/{ => tcg}/mips32r6.decode (100%)\r
 rename target/mips/{ => tcg}/mips64r6.decode (100%)\r
 rename target/mips/{ => tcg}/msa32.decode (100%)\r
 rename target/mips/{ => tcg}/msa64.decode (100%)\r
 rename target/mips/{ => tcg}/tx79.decode (100%)\r
 create mode 100644 target/mips/fpu.c\r
 create mode 100644 target/mips/msa.c\r
 delete mode 100644 target/mips/op_helper.c\r
 rename target/mips/{ => sysemu}/addr.c (100%)\r
 create mode 100644 target/mips/sysemu/cp0.c\r
 rename target/mips/{ => sysemu}/cp0_timer.c (100%)\r
 rename target/mips/{ => sysemu}/machine.c (100%)\r
 create mode 100644 target/mips/sysemu/physaddr.c\r
 rename target/mips/{ => tcg}/dsp_helper.c (100%)\r
 create mode 100644 target/mips/tcg/exception.c\r
 rename target/mips/{ => tcg}/fpu_helper.c (99%)\r
 create mode 100644 target/mips/tcg/ldst_helper.c\r
 rename target/mips/{ => tcg}/lmmi_helper.c (100%)\r
 rename target/mips/{ => tcg}/msa_helper.c (99%)\r
 rename target/mips/{ => tcg}/msa_translate.c (100%)\r
 rename target/mips/{ => tcg}/mxu_translate.c (100%)\r
 create mode 100644 target/mips/tcg/op_helper.c\r
 rename target/mips/{ => tcg}/rel6_translate.c (100%)\r
 rename target/mips/{ => tcg/sysemu}/cp0_helper.c (100%)\r
 rename target/mips/{ => tcg/sysemu}/mips-semi.c (100%)\r
 create mode 100644 target/mips/tcg/sysemu/special_helper.c\r
 rename target/mips/{ => tcg/sysemu}/tlb_helper.c (76%)\r
 rename target/mips/{ => tcg}/translate.c (99%)\r
 rename target/mips/{ => tcg}/translate_addr_const.c (100%)\r
 rename target/mips/{ => tcg}/tx79_translate.c (100%)\r
 rename target/mips/{ => tcg}/txx9_translate.c (100%)\r
 create mode 100644 target/mips/tcg/user/tlb_helper.c\r
 create mode 100644 target/mips/sysemu/meson.build\r
 create mode 100644 target/mips/tcg/meson.build\r
 create mode 100644 target/mips/tcg/sysemu/meson.build\r
 create mode 100644 target/mips/tcg/user/meson.build\r
\r
-- \r
2.26.3\r
\r


^ permalink raw reply	[flat|nested] 32+ messages in thread

end of thread, other threads:[~2021-04-19 10:55 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-18 22:50 [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 01/29] target/mips: Simplify meson TCG rules Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 03/29] target/mips: Move msa_reset() " Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 04/29] target/mips: Make CPU/FPU regnames[] arrays global Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 05/29] target/mips: Optimize CPU/FPU regnames[] arrays Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 07/29] target/mips: Turn printfpr() macro into a proper function Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 08/29] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h" Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 09/29] target/mips: Extract load/store helpers to ldst_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 10/29] meson: Introduce meson_user_arch source set for arch-specific user-mode Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 11/29] target/mips: Introduce tcg-internal.h for TCG specific declarations Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 12/29] target/mips: Add simple user-mode mips_cpu_do_interrupt() Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 13/29] target/mips: Add simple user-mode mips_cpu_tlb_fill() Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 14/29] target/mips: Move cpu_signal_handler definition around Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 15/29] target/mips: Move sysemu specific files under sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 16/29] target/mips: Move physical addressing code to sysemu/physaddr.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 17/29] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 18/29] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 19/29] target/mips: Restrict mmu_init() to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 20/29] target/mips: Move tlb_helper.c to tcg/sysemu/ Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 21/29] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 22/29] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 23/29] target/mips: Move helper_cache() " Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 24/29] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 25/29] target/mips: Move exception management code to exception.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 26/29] target/mips: Move CP0 helpers to sysemu/cp0.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 27/29] target/mips: Move TCG source files under tcg/ sub directory Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 28/29] hw/mips: Restrict non-virtualized machines to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 29/29] gitlab-ci: Add KVM mips64el cross-build jobs Philippe Mathieu-Daudé
2021-04-19 10:25   ` Thomas Huth
2021-04-18 23:03 ` [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds no-reply

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