* [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
@ 2021-04-20 1:31 frank.chang
2021-04-20 14:17 ` Richard Henderson
2021-04-22 1:06 ` Richard Henderson
0 siblings, 2 replies; 5+ messages in thread
From: frank.chang @ 2021-04-20 1:31 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Peter Maydell, Alex Bennée, Aurelien Jarno
From: Frank Chang <frank.chang@sifive.com>
In IEEE 754-2008 spec:
Invalid operation exception is signaled when doing:
fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
unless c is a quiet NaN; if c is a quiet NaN then it is
implementation defined whether the invalid operation exception
is signaled.
In RISC-V Unprivileged ISA spec:
The fused multiply-add instructions must set the invalid
operation exception flag when the multiplicands are Inf and
zero, even when the addend is a quiet NaN.
This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat-specialize.c.inc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index c2f87addb25..12f29fbfc5e 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -624,6 +624,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
} else {
return 1;
}
+#elif defined(TARGET_RISCV)
+ /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 3; /* deafult NaN */
#elif defined(TARGET_XTENSA)
/*
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-20 1:31 [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions frank.chang
@ 2021-04-20 14:17 ` Richard Henderson
2021-04-22 0:05 ` Alistair Francis
2021-04-22 1:06 ` Richard Henderson
1 sibling, 1 reply; 5+ messages in thread
From: Richard Henderson @ 2021-04-20 14:17 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv, Alistair Francis
Cc: Peter Maydell, Alex Bennée, Aurelien Jarno
On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> From: Frank Chang<frank.chang@sifive.com>
>
> In IEEE 754-2008 spec:
> Invalid operation exception is signaled when doing:
> fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
> unless c is a quiet NaN; if c is a quiet NaN then it is
> implementation defined whether the invalid operation exception
> is signaled.
>
> In RISC-V Unprivileged ISA spec:
> The fused multiply-add instructions must set the invalid
> operation exception flag when the multiplicands are Inf and
> zero, even when the addend is a quiet NaN.
>
> This commit set invalid operation execption flag for RISC-V when
> multiplicands of muladd instructions are Inf and zero.
>
> Signed-off-by: Frank Chang<frank.chang@sifive.com>
> ---
> fpu/softfloat-specialize.c.inc | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Alistair, will you take this via your riscv queue?
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-20 14:17 ` Richard Henderson
@ 2021-04-22 0:05 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2021-04-22 0:05 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, open list:RISC-V, Frank Chang,
qemu-devel@nongnu.org Developers, Alistair Francis,
Alex Bennée, Aurelien Jarno
On Wed, Apr 21, 2021 at 12:17 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> > From: Frank Chang<frank.chang@sifive.com>
> >
> > In IEEE 754-2008 spec:
> > Invalid operation exception is signaled when doing:
> > fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
> > unless c is a quiet NaN; if c is a quiet NaN then it is
> > implementation defined whether the invalid operation exception
> > is signaled.
> >
> > In RISC-V Unprivileged ISA spec:
> > The fused multiply-add instructions must set the invalid
> > operation exception flag when the multiplicands are Inf and
> > zero, even when the addend is a quiet NaN.
> >
> > This commit set invalid operation execption flag for RISC-V when
> > multiplicands of muladd instructions are Inf and zero.
> >
> > Signed-off-by: Frank Chang<frank.chang@sifive.com>
> > ---
> > fpu/softfloat-specialize.c.inc | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Alistair, will you take this via your riscv queue?
Yep, getting it now
Alistair
>
>
> r~
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-20 1:31 [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions frank.chang
2021-04-20 14:17 ` Richard Henderson
@ 2021-04-22 1:06 ` Richard Henderson
2021-04-22 1:42 ` Alistair Francis
1 sibling, 1 reply; 5+ messages in thread
From: Richard Henderson @ 2021-04-22 1:06 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv; +Cc: Alistair Francis
On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> + return 3; /* deafult NaN */
Late notice of spelling error: default.
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
2021-04-22 1:06 ` Richard Henderson
@ 2021-04-22 1:42 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2021-04-22 1:42 UTC (permalink / raw)
To: Richard Henderson
Cc: Frank Chang, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Thu, Apr 22, 2021 at 11:06 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/19/21 6:31 PM, frank.chang@sifive.com wrote:
> > + return 3; /* deafult NaN */
>
> Late notice of spelling error: default.
Fixed when I applied it.
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> r~
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-04-20 1:31 [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions frank.chang
2021-04-20 14:17 ` Richard Henderson
2021-04-22 0:05 ` Alistair Francis
2021-04-22 1:06 ` Richard Henderson
2021-04-22 1:42 ` Alistair Francis
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