From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, "Yongbok Kim" <yongbok.kim@mips.com>,
mmorrell@tachyum.com, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 11/11] target/mips: Drop denormal operand to update_msacsr
Date: Wed, 26 May 2021 21:14:05 -0700 [thread overview]
Message-ID: <20210527041405.391567-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210527041405.391567-1-richard.henderson@linaro.org>
The comment about not signaling all underflow cases is
almost certainly incorrect. It has been there since the
initial commit of the file.
There is a bit of code below that sets underflow with
float_flag_oflush_denormal, which is probably the fix
for whatever the original case may have been.
Cc: Yongbok Kim <yongbok.kim@mips.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/msa_helper.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index ffe6e630ed..b752373bce 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -6205,7 +6205,7 @@ static int ieee_to_mips_xcpt_msa(int ieee_xcpt)
return mips_xcpt;
}
-static int update_msacsr(CPUMIPSState *env, int action, int denormal)
+static int update_msacsr(CPUMIPSState *env, int action)
{
int ieee_exception_flags;
int mips_exception_flags = 0;
@@ -6215,10 +6215,6 @@ static int update_msacsr(CPUMIPSState *env, int action, int denormal)
ieee_exception_flags = get_float_exception_flags(
&env->active_tc.msa_fp_status);
- /* QEMU softfloat does not signal all underflow cases */
- if (denormal) {
- ieee_exception_flags |= float_flag_underflow;
- }
if (ieee_exception_flags) {
mips_exception_flags = ieee_to_mips_xcpt_msa(ieee_exception_flags);
}
@@ -6469,7 +6465,7 @@ static int32_t float64_to_q32(float64 a, float_status *status)
cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
} \
DEST = cond ? M_MAX_UINT(BITS) : 0; \
- c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
+ c = update_msacsr(env, CLEAR_IS_INEXACT); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7043,13 +7039,6 @@ void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
}
-#define float16_is_zero(ARG) 0
-#define float16_is_zero_or_denormal(ARG) 0
-
-#define IS_DENORMAL(ARG, BITS) \
- (!float ## BITS ## _is_zero(ARG) \
- && float ## BITS ## _is_zero_or_denormal(ARG))
-
#define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
do { \
float_status *status = &env->active_tc.msa_fp_status; \
@@ -7057,7 +7046,7 @@ void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
\
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
- c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
+ c = update_msacsr(env, 0); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7193,7 +7182,7 @@ void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
\
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
- c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
+ c = update_msacsr(env, 0); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7312,7 +7301,7 @@ void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
\
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _ ## OP(ARG, status); \
- c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
+ c = update_msacsr(env, 0); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7365,7 +7354,7 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
\
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _ ## OP(ARG, status); \
- c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
+ c = update_msacsr(env, CLEAR_FS_UNDERFLOW); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
@@ -7416,7 +7405,7 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
\
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
- c = update_msacsr(env, 0, 0); \
+ c = update_msacsr(env, 0); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7672,7 +7661,7 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
\
set_float_exception_flags(0, status); \
DEST = float ## BITS ## _ ## OP(ARG, status); \
- c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
+ c = update_msacsr(env, CLEAR_FS_UNDERFLOW); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7780,8 +7769,7 @@ void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
float ## BITS ## _is_quiet_nan(DEST, status) ? \
- 0 : RECIPROCAL_INEXACT, \
- IS_DENORMAL(DEST, BITS)); \
+ 0 : RECIPROCAL_INEXACT); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
@@ -7897,7 +7885,7 @@ void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
(~float_flag_inexact), \
status); \
\
- c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
+ c = update_msacsr(env, 0); \
\
if (get_enabled_exceptions(env, c)) { \
DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
--
2.25.1
next prev parent reply other threads:[~2021-05-27 4:22 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-27 4:13 [PATCH 00/11] softfloat: Improve denormal handling Richard Henderson
2021-05-27 4:13 ` [PATCH 01/11] softfloat: Rename float_flag_input_denormal to float_flag_iflush_denormal Richard Henderson
2021-06-07 15:16 ` Alex Bennée
2021-06-19 15:08 ` Philippe Mathieu-Daudé
2021-05-27 4:13 ` [PATCH 02/11] softfloat: Rename float_flag_output_denormal to float_flag_oflush_denormal Richard Henderson
2021-06-07 15:16 ` Alex Bennée
2021-06-19 15:08 ` Philippe Mathieu-Daudé
2021-05-27 4:13 ` [PATCH 03/11] softfloat: Introduce float_flag_inorm_denormal Richard Henderson
2021-05-28 17:41 ` Michael Morrell
2021-05-29 15:21 ` Richard Henderson
2021-07-14 16:44 ` Michael Morrell
2021-07-14 16:57 ` Richard Henderson
2021-07-14 17:50 ` Michael Morrell
2022-01-12 0:02 ` Michael Morrell
2021-06-07 15:35 ` Alex Bennée
2021-06-07 16:28 ` Alex Bennée
2021-06-07 16:41 ` Richard Henderson
2021-06-07 17:19 ` Alex Bennée
2021-06-07 20:52 ` Richard Henderson
2021-05-27 4:13 ` [PATCH 04/11] softfloat: Introduce float_flag_result_denormal Richard Henderson
2021-06-07 16:30 ` Alex Bennée
2021-06-19 15:10 ` Philippe Mathieu-Daudé
2021-05-27 4:13 ` [PATCH 05/11] target/i386: Use float_flag_inorm_denormal Richard Henderson
2021-06-19 18:41 ` Richard Henderson
2021-05-27 4:14 ` [PATCH 06/11] target/rx: Handle the FPSW.DN bit in helper_set_fpsw Richard Henderson
2021-05-28 15:34 ` Yoshinori Sato
2021-05-27 4:14 ` [PATCH 07/11] target/rx: Use FloatRoundMode " Richard Henderson
2021-05-28 15:35 ` Yoshinori Sato
2021-06-01 3:27 ` Philippe Mathieu-Daudé
2021-05-27 4:14 ` [PATCH 08/11] target/rx: Fix setting of FPSW.CE Richard Henderson
2021-05-28 15:35 ` Yoshinori Sato
2021-05-27 4:14 ` [PATCH 09/11] target/mips: Drop inline markers from msa_helper.c Richard Henderson
2021-06-01 3:27 ` Philippe Mathieu-Daudé
2021-05-27 4:14 ` [PATCH 10/11] target/mips: Do not check MSACSR_FS_MASK in update_msacsr Richard Henderson
2021-06-19 15:15 ` Philippe Mathieu-Daudé
2021-05-27 4:14 ` Richard Henderson [this message]
2021-06-01 3:29 ` [PATCH 11/11] target/mips: Drop denormal operand to update_msacsr Philippe Mathieu-Daudé
2021-06-07 16:31 ` [PATCH 00/11] softfloat: Improve denormal handling Alex Bennée
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