From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Warner Losh" <imp@bsdimp.com>
Subject: [PATCH v3 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
Date: Sat, 11 Sep 2021 18:54:26 +0200 [thread overview]
Message-ID: <20210911165434.531552-17-f4bug@amsat.org> (raw)
In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org>
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/openrisc/cpu.h | 5 +++--
target/openrisc/cpu.c | 2 +-
target/openrisc/interrupt.c | 2 --
target/openrisc/meson.build | 6 ++++--
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..be6df81a810 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -312,8 +312,6 @@ struct OpenRISCCPU {
void cpu_openrisc_list(void);
-void openrisc_cpu_do_interrupt(CPUState *cpu);
-bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_openrisc_cpu;
+void openrisc_cpu_do_interrupt(CPUState *cpu);
+bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
/* hw/openrisc_pic.c */
void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index bd34e429ecb..27cb04152f9 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
- .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
.tlb_fill = openrisc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
.do_interrupt = openrisc_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 3eab771dcda..19223e3f25b 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -28,7 +28,6 @@
void openrisc_cpu_do_interrupt(CPUState *cs)
{
-#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
int exception = cs->exception_index;
@@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
} else {
cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
}
-#endif
cs->exception_index = -1;
}
diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build
index 9774a583065..e445dec4a00 100644
--- a/target/openrisc/meson.build
+++ b/target/openrisc/meson.build
@@ -9,7 +9,6 @@
'exception_helper.c',
'fpu_helper.c',
'gdbstub.c',
- 'interrupt.c',
'interrupt_helper.c',
'mmu.c',
'sys_helper.c',
@@ -17,7 +16,10 @@
))
openrisc_softmmu_ss = ss.source_set()
-openrisc_softmmu_ss.add(files('machine.c'))
+openrisc_softmmu_ss.add(files(
+ 'interrupt.c',
+ 'machine.c',
+))
target_arch += {'openrisc': openrisc_ss}
target_softmmu_arch += {'openrisc': openrisc_softmmu_ss}
--
2.31.1
next prev parent reply other threads:[~2021-09-11 17:10 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-11 16:54 [PATCH v3 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 07/24] target/arm: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 08/24] target/cris: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 09/24] target/hppa: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 10/24] target/i386: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 13/24] target/microblaze: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 14/24] target/mips: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 15/24] target/nios2: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` Philippe Mathieu-Daudé [this message]
2021-09-11 16:54 ` [PATCH v3 17/24] target/ppc: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 18/24] target/riscv: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 19/24] target/sh4: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 20/24] target/sparc: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 21/24] target/rx: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 22/24] target/xtensa: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
2021-09-12 19:50 ` [PATCH v3 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Richard Henderson
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