From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Bin Meng" <bmeng.cn@gmail.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Warner Losh" <imp@bsdimp.com>
Subject: [PATCH v3 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
Date: Sat, 11 Sep 2021 18:54:28 +0200 [thread overview]
Message-ID: <20210911165434.531552-19-f4bug@amsat.org> (raw)
In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org>
Restrict cpu_exec_interrupt() and its callees to sysemu.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 5 -----
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf1c899c00b..e735e53e26c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
@@ -362,6 +361,7 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579c..13575c14085 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
static const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.tlb_fill = riscv_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f4..701858d670c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
return RISCV_EXCP_NONE; /* indicates no pending interrupt */
}
}
-#endif
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
-#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_HARD) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
}
-#endif
return false;
}
-#if !defined(CONFIG_USER_ONLY)
-
/* Return true is floating point support is currently enabled */
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
--
2.31.1
next prev parent reply other threads:[~2021-09-11 17:12 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-11 16:54 [PATCH v3 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 07/24] target/arm: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 08/24] target/cris: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 09/24] target/hppa: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 10/24] target/i386: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 13/24] target/microblaze: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 14/24] target/mips: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 15/24] target/nios2: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 16/24] target/openrisc: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 17/24] target/ppc: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` Philippe Mathieu-Daudé [this message]
2021-09-11 16:54 ` [PATCH v3 19/24] target/sh4: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 20/24] target/sparc: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 21/24] target/rx: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 22/24] target/xtensa: " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Philippe Mathieu-Daudé
2021-09-11 16:54 ` [PATCH v3 24/24] user: Remove cpu_get_pic_interrupt() stubs Philippe Mathieu-Daudé
2021-09-12 19:50 ` [PATCH v3 00/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Richard Henderson
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