From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
Anup Patel <anup.patel@wdc.com>,
qemu-devel@nongnu.org, Atish Patra <atish.patra@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs
Date: Tue, 26 Oct 2021 12:12:08 +0530 [thread overview]
Message-ID: <20211026064227.2014502-4-anup.patel@wdc.com> (raw)
In-Reply-To: <20211026064227.2014502-1-anup.patel@wdc.com>
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external
interrupt to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 61 ++++++++++++++++++++++++++++-----------
target/riscv/cpu.h | 5 ++++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 36 +++++++++++++++++++++--
target/riscv/csr.c | 43 ++++++++++++++++++---------
target/riscv/machine.c | 6 ++--
6 files changed, 117 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0460a3972b..8042c4ebcf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -570,23 +570,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
static void riscv_cpu_set_irq(void *opaque, int irq, int level)
{
RISCVCPU *cpu = RISCV_CPU(opaque);
+ CPURISCVState *env = &cpu->env;
- switch (irq) {
- case IRQ_U_SOFT:
- case IRQ_S_SOFT:
- case IRQ_VS_SOFT:
- case IRQ_M_SOFT:
- case IRQ_U_TIMER:
- case IRQ_S_TIMER:
- case IRQ_VS_TIMER:
- case IRQ_M_TIMER:
- case IRQ_U_EXT:
- case IRQ_S_EXT:
- case IRQ_VS_EXT:
- case IRQ_M_EXT:
- riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
- break;
- default:
+ if (irq < IRQ_LOCAL_MAX) {
+ switch (irq) {
+ case IRQ_U_SOFT:
+ case IRQ_S_SOFT:
+ case IRQ_VS_SOFT:
+ case IRQ_M_SOFT:
+ case IRQ_U_TIMER:
+ case IRQ_S_TIMER:
+ case IRQ_VS_TIMER:
+ case IRQ_M_TIMER:
+ case IRQ_U_EXT:
+ case IRQ_S_EXT:
+ case IRQ_VS_EXT:
+ case IRQ_M_EXT:
+ riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
+ /* Require H-extension for handling guest local interrupts */
+ if (!riscv_has_ext(env, RVH)) {
+ g_assert_not_reached();
+ }
+
+ /* Compute bit position in HGEIP CSR */
+ irq = irq - IRQ_LOCAL_MAX + 1;
+ if (env->geilen < irq) {
+ g_assert_not_reached();
+ }
+
+ /* Update HGEIP CSR */
+ env->hgeip &= ~((target_ulong)1 << irq);
+ if (level) {
+ env->hgeip |= (target_ulong)1 << irq;
+ }
+
+ /* Update mip.SGEIP bit */
+ riscv_cpu_update_mip(cpu, MIP_SGEIP,
+ BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+ } else {
g_assert_not_reached();
}
}
@@ -599,7 +625,8 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
- qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
+ qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
+ IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
#endif /* CONFIG_USER_ONLY */
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a33dc30be8..bbf469f079 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -148,6 +148,7 @@ struct CPURISCVState {
target_ulong priv;
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
+ target_ulong geilen;
target_ulong resetvec;
target_ulong mhartid;
@@ -185,6 +186,8 @@ struct CPURISCVState {
target_ulong htval;
target_ulong htinst;
target_ulong hgatp;
+ target_ulong hgeie;
+ target_ulong hgeip;
uint64_t htimedelta;
/* Virtual CSRs */
@@ -337,6 +340,8 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8a5a4cde95..335e0193a9 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -500,6 +500,7 @@ typedef enum RISCVException {
#define IRQ_M_EXT 11
#define IRQ_S_GEXT 12
#define IRQ_LOCAL_MAX 13
+#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1)
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0d1132f39d..bb7ac9890b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -125,7 +125,10 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
target_ulong pending = env->mip & env->mie &
~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
- target_ulong vspending = (env->mip & env->mie &
+ target_ulong vsgemask =
+ (target_ulong)1 << get_field(env->hstatus, HSTATUS_VGEIN);
+ target_ulong vsgein = (env->hgeip & vsgemask) ? MIP_VSEIP : 0;
+ target_ulong vspending = ((env->mip | vsgein) & env->mie &
(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
target_ulong mie = env->priv < PRV_M ||
@@ -241,6 +244,28 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
}
}
+target_ulong riscv_cpu_get_geilen(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return 0;
+ }
+
+ return env->geilen;
+}
+
+void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ if (geilen > (TARGET_LONG_BITS - 1)) {
+ return;
+ }
+
+ env->geilen = geilen;
+}
+
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
@@ -302,9 +327,14 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
CPUState *cs = CPU(cpu);
- uint32_t old = env->mip;
+ uint32_t gein, vsgein = 0, old = env->mip;
bool locked = false;
+ if (riscv_cpu_virt_enabled(env)) {
+ gein = get_field(env->hstatus, HSTATUS_VGEIN);
+ vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+ }
+
if (!qemu_mutex_iothread_locked()) {
locked = true;
qemu_mutex_lock_iothread();
@@ -312,7 +342,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
env->mip = (env->mip & ~mask) | (value & mask);
- if (env->mip) {
+ if (env->mip | vsgein) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a0a0c0679..7ff285282b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -793,7 +793,7 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
RISCVCPU *cpu = env_archcpu(env);
/* Allow software control of delegable interrupts not claimed by hardware */
target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
- uint32_t old_mip;
+ uint32_t gin, old_mip;
if (mask) {
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
@@ -801,6 +801,11 @@ static RISCVException rmw_mip(CPURISCVState *env, int csrno,
old_mip = env->mip;
}
+ if (csrno != CSR_HVIP) {
+ gin = get_field(env->hstatus, HSTATUS_VGEIN);
+ old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
+ }
+
if (ret_value) {
*ret_value = old_mip;
}
@@ -963,7 +968,7 @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
target_ulong new_value, target_ulong write_mask)
{
/* Shift the S bits to their VS bit location in mip */
- int ret = rmw_mip(env, 0, ret_value, new_value << 1,
+ int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
(write_mask << 1) & vsip_writable_mask & env->hideleg);
if (ret_value) {
@@ -983,7 +988,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
if (riscv_cpu_virt_enabled(env)) {
ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
} else {
- ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ ret = rmw_mip(env, csrno, ret_value, new_value,
write_mask & env->mideleg & sip_writable_mask);
}
@@ -1102,7 +1107,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- int ret = rmw_mip(env, 0, ret_value, new_value,
+ int ret = rmw_mip(env, csrno, ret_value, new_value,
write_mask & hvip_writable_mask);
if (ret_value) {
@@ -1115,7 +1120,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- int ret = rmw_mip(env, 0, ret_value, new_value,
+ int ret = rmw_mip(env, csrno, ret_value, new_value,
write_mask & hip_writable_mask);
if (ret_value) {
@@ -1152,15 +1157,27 @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException write_hgeie(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException read_hgeie(CPURISCVState *env, int csrno,
+ target_ulong *val)
{
if (val) {
- qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ *val = env->hgeie;
}
return RISCV_EXCP_NONE;
}
+static RISCVException write_hgeie(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
+ val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
+ env->hgeie = val;
+ /* Update mip.SGEIP bit */
+ riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
+ BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_htval(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1188,11 +1205,11 @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException write_hgeip(CPURISCVState *env, int csrno,
- target_ulong val)
+static RISCVException read_hgeip(CPURISCVState *env, int csrno,
+ target_ulong *val)
{
if (val) {
- qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ *val = env->hgeip;
}
return RISCV_EXCP_NONE;
}
@@ -1619,10 +1636,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { "hie", hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
- [CSR_HGEIE] = { "hgeie", hmode, read_zero, write_hgeie },
+ [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
[CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
- [CSR_HGEIP] = { "hgeip", hmode, read_zero, write_hgeip },
+ [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL },
[CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
[CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index f64b2a96c1..fe99ec7304 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -102,8 +102,8 @@ static const VMStateDescription vmstate_vector = {
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = hyper_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(env.hstatus, RISCVCPU),
@@ -113,6 +113,8 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINTTL(env.htval, RISCVCPU),
VMSTATE_UINTTL(env.htinst, RISCVCPU),
VMSTATE_UINTTL(env.hgatp, RISCVCPU),
+ VMSTATE_UINTTL(env.hgeie, RISCVCPU),
+ VMSTATE_UINTTL(env.hgeip, RISCVCPU),
VMSTATE_UINT64(env.htimedelta, RISCVCPU),
VMSTATE_UINT64(env.vsstatus, RISCVCPU),
--
2.25.1
next prev parent reply other threads:[~2021-10-26 7:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
2021-10-26 6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-11-01 8:59 ` Bin Meng
2021-10-26 6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-11-02 6:52 ` Bin Meng
2021-11-02 10:24 ` Anup Patel
2021-11-02 10:52 ` Bin Meng
2021-11-03 5:30 ` Anup Patel
2021-10-26 6:42 ` Anup Patel [this message]
2021-10-26 6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-10-31 23:35 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 06/22] target/riscv: Add AIA cpu feature Anup Patel
2021-10-26 6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
2021-11-01 6:55 ` Alistair Francis
2021-11-01 7:57 ` Anup Patel
2021-11-03 5:57 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-11-04 4:52 ` Alistair Francis
2021-12-07 10:08 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-10-26 6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-11-04 4:43 ` Alistair Francis
2021-12-09 6:14 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-11-04 4:49 ` Alistair Francis
2021-12-09 6:44 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-11-04 4:51 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-11-04 4:56 ` Alistair Francis
2021-12-09 11:15 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-10-26 6:42 ` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-10-26 6:42 ` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 22/22] docs/system: riscv: Document AIA options for " Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211026064227.2014502-4-anup.patel@wdc.com \
--to=anup.patel@wdc.com \
--cc=Alistair.Francis@wdc.com \
--cc=anup@brainfault.org \
--cc=atish.patra@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=palmer@dabbelt.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).