From: Anup Patel <anup@brainfault.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup.patel@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs
Date: Thu, 9 Dec 2021 12:14:51 +0530 [thread overview]
Message-ID: <CAAhSdy27HKfvnWhaaWLiC3T-ikq==MZdRKHmqkpy4WP3=GMf1g@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKODrqQRD6XUZOjaEjXiY6JNLWd2ZL3rUnb8g0jUEC1_FQ@mail.gmail.com>
On Thu, Nov 4, 2021 at 10:19 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 5:39 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The AIA hvictl and hviprioX CSRs allow hypervisor to control
> > interrupts visible at VS-level. This patch implements AIA hvictl
> > and hviprioX CSRs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > target/riscv/cpu.h | 1 +
> > target/riscv/csr.c | 126 +++++++++++++++++++++++++++++++++++++++++
> > target/riscv/machine.c | 2 +
> > 3 files changed, 129 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 718a95e864..21d9c536ef 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -196,6 +196,7 @@ struct CPURISCVState {
> > uint64_t htimedelta;
> >
> > /* Hypervisor controlled virtual interrupt priorities */
> > + target_ulong hvictl;
> > uint8_t hviprio[64];
> >
> > /* Virtual CSRs */
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 3a7d89ac34..46d0cabbde 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -219,6 +219,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
> >
> > }
> >
> > +static int aia_hmode(CPURISCVState *env, int csrno)
> > +{
> > + if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + return hmode(env, csrno);
> > +}
> > +
> > static int aia_hmode32(CPURISCVState *env, int csrno)
> > {
> > if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > @@ -1031,6 +1040,9 @@ static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
> > uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
> >
> > if (riscv_cpu_virt_enabled(env)) {
> > + if (env->hvictl & HVICTL_VTI) {
> > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > + }
> > ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> > } else {
> > ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
> > @@ -1229,6 +1241,9 @@ static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
> > uint64_t mask = env->mideleg & sip_writable_mask;
> >
> > if (riscv_cpu_virt_enabled(env)) {
> > + if (env->hvictl & HVICTL_VTI) {
> > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> > + }
> > ret = rmw_vsip64(env, CSR_VSIE, ret_val, new_val, wr_mask);
> > } else {
> > ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
> > @@ -1615,6 +1630,110 @@ static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + *val = env->hvictl;
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + env->hvictl = val & HVICTL_VALID_MASK;
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int read_hvipriox(CPURISCVState *env, int first_index,
> > + uint8_t *iprio, target_ulong *val)
> > +{
> > + int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
>
> You should be checking the CPUs xlen instead of using the hardcoded
> TARGET_LONG_BITS here.
Sure, I will update and use CPU xlen.
Regards,
Anup
>
> Alistair
>
> > +
> > + /* First index has to be multiple of numbe of irqs per register */
> > + if (first_index % num_irqs) {
> > + return (riscv_cpu_virt_enabled(env)) ?
> > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + /* Fill-up return value */
> > + *val = 0;
> > + for (i = 0; i < num_irqs; i++) {
> > + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> > + continue;
> > + }
> > + if (rdzero) {
> > + continue;
> > + }
> > + *val |= ((target_ulong)iprio[irq]) << (i * 8);
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int write_hvipriox(CPURISCVState *env, int first_index,
> > + uint8_t *iprio, target_ulong val)
> > +{
> > + int i, irq, rdzero, num_irqs = 4 * (TARGET_LONG_BITS / 32);
> > +
> > + /* First index has to be multiple of numbe of irqs per register */
> > + if (first_index % num_irqs) {
> > + return (riscv_cpu_virt_enabled(env)) ?
> > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + /* Fill-up priority arrary */
> > + for (i = 0; i < num_irqs; i++) {
> > + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
> > + continue;
> > + }
> > + if (rdzero) {
> > + iprio[irq] = 0;
> > + } else {
> > + iprio[irq] = (val >> (i * 8)) & 0xff;
> > + }
> > + }
> > +
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 0, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 0, env->hviprio, val);
> > +}
> > +
> > +static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 4, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 4, env->hviprio, val);
> > +}
> > +
> > +static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 8, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 8, env->hviprio, val);
> > +}
> > +
> > +static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
> > +{
> > + return read_hvipriox(env, 12, env->hviprio, val);
> > +}
> > +
> > +static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
> > +{
> > + return write_hvipriox(env, 12, env->hviprio, val);
> > +}
> > +
> > /* Virtual CSR Registers */
> > static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > @@ -2005,9 +2124,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
> > [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
> >
> > + /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
> > + [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
> > + [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
> > + [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
> > +
> > /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> > [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
> > [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
> > + [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
> > + [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
> > [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh },
> > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
> >
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index 7356d70be6..bc20960260 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -116,6 +116,8 @@ static const VMStateDescription vmstate_hyper = {
> > VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> > VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> > VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> > +
> > + VMSTATE_UINTTL(env.hvictl, RISCVCPU),
> > VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
> >
> > VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> > --
> > 2.25.1
> >
> >
next prev parent reply other threads:[~2021-12-09 6:50 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
2021-10-26 6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-11-01 8:59 ` Bin Meng
2021-10-26 6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-11-02 6:52 ` Bin Meng
2021-11-02 10:24 ` Anup Patel
2021-11-02 10:52 ` Bin Meng
2021-11-03 5:30 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-10-31 23:35 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 06/22] target/riscv: Add AIA cpu feature Anup Patel
2021-10-26 6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
2021-11-01 6:55 ` Alistair Francis
2021-11-01 7:57 ` Anup Patel
2021-11-03 5:57 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-11-04 4:52 ` Alistair Francis
2021-12-07 10:08 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-10-26 6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-11-04 4:43 ` Alistair Francis
2021-12-09 6:14 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-11-04 4:49 ` Alistair Francis
2021-12-09 6:44 ` Anup Patel [this message]
2021-10-26 6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-11-04 4:51 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-11-04 4:56 ` Alistair Francis
2021-12-09 11:15 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-10-26 6:42 ` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-10-26 6:42 ` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 22/22] docs/system: riscv: Document AIA options for " Anup Patel
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