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From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
	Anup Patel <anup.patel@wdc.com>,
	qemu-devel@nongnu.org, Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
Date: Tue, 26 Oct 2021 12:12:10 +0530	[thread overview]
Message-ID: <20211026064227.2014502-6-anup.patel@wdc.com> (raw)
In-Reply-To: <20211026064227.2014502-1-anup.patel@wdc.com>

The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
   but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
   AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 11 +++--------
 target/riscv/cpu.h |  5 +++++
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8042c4ebcf..69d6b5eb36 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -124,11 +124,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
     env->vext_ver = vext_ver;
 }
 
-static void set_feature(CPURISCVState *env, int feature)
-{
-    env->features |= (1ULL << feature);
-}
-
 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 {
 #ifndef CONFIG_USER_ONLY
@@ -425,18 +420,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
 
     if (cpu->cfg.mmu) {
-        set_feature(env, RISCV_FEATURE_MMU);
+        riscv_set_feature(env, RISCV_FEATURE_MMU);
     }
 
     if (cpu->cfg.pmp) {
-        set_feature(env, RISCV_FEATURE_PMP);
+        riscv_set_feature(env, RISCV_FEATURE_PMP);
 
         /*
          * Enhanced PMP should only be available
          * on harts with PMP support
          */
         if (cpu->cfg.epmp) {
-            set_feature(env, RISCV_FEATURE_EPMP);
+            riscv_set_feature(env, RISCV_FEATURE_EPMP);
         }
     }
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bbf469f079..cc035a8897 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -326,6 +326,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
     return env->features & (1ULL << feature);
 }
 
+static inline void riscv_set_feature(CPURISCVState *env, int feature)
+{
+    env->features |= (1ULL << feature);
+}
+
 #include "cpu_user.h"
 
 extern const char * const riscv_int_regnames[];
-- 
2.25.1



  parent reply	other threads:[~2021-10-26  7:26 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-26  6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
2021-10-26  6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-11-01  8:59   ` Bin Meng
2021-10-26  6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-11-02  6:52   ` Bin Meng
2021-11-02 10:24     ` Anup Patel
2021-11-02 10:52       ` Bin Meng
2021-11-03  5:30         ` Anup Patel
2021-10-26  6:42 ` [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-10-26  6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-10-31 23:35   ` Alistair Francis
2021-10-26  6:42 ` Anup Patel [this message]
2021-10-26  6:42 ` [PATCH v4 06/22] target/riscv: Add AIA cpu feature Anup Patel
2021-10-26  6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
2021-11-01  6:55   ` Alistair Francis
2021-11-01  7:57     ` Anup Patel
2021-11-03  5:57       ` Alistair Francis
2021-10-26  6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-11-04  4:52   ` Alistair Francis
2021-12-07 10:08     ` Anup Patel
2021-10-26  6:42 ` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-10-26  6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-11-04  4:43   ` Alistair Francis
2021-12-09  6:14     ` Anup Patel
2021-10-26  6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-11-04  4:49   ` Alistair Francis
2021-12-09  6:44     ` Anup Patel
2021-10-26  6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-11-04  4:51   ` Alistair Francis
2021-10-26  6:42 ` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-10-26  6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-11-04  4:56   ` Alistair Francis
2021-12-09 11:15     ` Anup Patel
2021-10-26  6:42 ` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-10-26  6:42 ` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-10-26  6:42 ` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-10-26  6:42 ` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-10-26  6:42 ` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-10-26  6:42 ` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-10-26  6:42 ` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-10-26  6:42 ` [PATCH v4 22/22] docs/system: riscv: Document AIA options for " Anup Patel

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