From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts
Date: Mon, 1 Nov 2021 09:35:21 +1000 [thread overview]
Message-ID: <CAKmqyKP45N2+FEG5eMqocv7XbO2ZmAWJAiKy3-mf2AnCYdW_UA@mail.gmail.com> (raw)
In-Reply-To: <20211026064227.2014502-5-anup.patel@wdc.com>
On Tue, Oct 26, 2021 at 5:41 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The guest external interrupts from an interrupt controller are
> delivered only when the Guest/VM is running (i.e. V=1). This means
> any guest external interrupt which is triggered while the Guest/VM
> is not running (i.e. V=0) will be missed on QEMU resulting in Guest
> with sluggish response to serial console input and other I/O events.
>
> To solve this, we check and inject interrupt after setting V=1.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index bb7ac9890b..04df3792a8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -287,6 +287,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
> }
>
> env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> +
> + if (enable) {
> + /*
> + * The guest external interrupts from an interrupt controller are
> + * delivered only when the Guest/VM is running (i.e. V=1). This means
> + * any guest external interrupt which is triggered while the Guest/VM
> + * is not running (i.e. V=0) will be missed on QEMU resulting in guest
> + * with sluggish response to serial console input and other I/O events.
> + *
> + * To solve this, we check and inject interrupt after setting V=1.
> + */
> + riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> + }
> }
>
> bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-10-31 23:37 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 6:42 [PATCH v4 00/22] QEMU RISC-V AIA support Anup Patel
2021-10-26 6:42 ` [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-11-01 8:59 ` Bin Meng
2021-10-26 6:42 ` [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-11-02 6:52 ` Bin Meng
2021-11-02 10:24 ` Anup Patel
2021-11-02 10:52 ` Bin Meng
2021-11-03 5:30 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-10-31 23:35 ` Alistair Francis [this message]
2021-10-26 6:42 ` [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 06/22] target/riscv: Add AIA cpu feature Anup Patel
2021-10-26 6:42 ` [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
2021-11-01 6:55 ` Alistair Francis
2021-11-01 7:57 ` Anup Patel
2021-11-03 5:57 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-11-04 4:52 ` Alistair Francis
2021-12-07 10:08 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-10-26 6:42 ` [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-11-04 4:43 ` Alistair Francis
2021-12-09 6:14 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-11-04 4:49 ` Alistair Francis
2021-12-09 6:44 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-11-04 4:51 ` Alistair Francis
2021-10-26 6:42 ` [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-11-04 4:56 ` Alistair Francis
2021-12-09 11:15 ` Anup Patel
2021-10-26 6:42 ` [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-10-26 6:42 ` [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-10-26 6:42 ` [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-10-26 6:42 ` [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-10-26 6:42 ` [PATCH v4 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-10-26 6:42 ` [PATCH v4 22/22] docs/system: riscv: Document AIA options for " Anup Patel
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