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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
	bin.meng@windriver.com, Alistair.Francis@wdc.com,
	LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 13/14] target/riscv: Don't save pc when exception return
Date: Wed, 10 Nov 2021 15:04:51 +0800	[thread overview]
Message-ID: <20211110070452.48539-14-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20211110070452.48539-1-zhiwei_liu@c-sky.com>

As pc will be written by the xepc in exception return, just ignore
pc in translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/helper.h                          | 4 ++--
 target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-----
 target/riscv/op_helper.c                       | 4 ++--
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e198d43981..a67965efe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -67,8 +67,8 @@ DEF_HELPER_2(csrr, tl, env, int)
 DEF_HELPER_3(csrw, void, env, int, tl)
 DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
 #ifndef CONFIG_USER_ONLY
-DEF_HELPER_2(sret, tl, env, tl)
-DEF_HELPER_2(mret, tl, env, tl)
+DEF_HELPER_1(sret, tl, env)
+DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 #endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 75c6ef80a6..6077bbbf11 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -74,10 +74,8 @@ static bool trans_uret(DisasContext *ctx, arg_uret *a)
 static bool trans_sret(DisasContext *ctx, arg_sret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
     if (has_ext(ctx, RVS)) {
-        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+        gen_helper_sret(cpu_pc, cpu_env);
         tcg_gen_exit_tb(NULL, 0); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
     } else {
@@ -92,8 +90,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
 static bool trans_mret(DisasContext *ctx, arg_mret *a)
 {
 #ifndef CONFIG_USER_ONLY
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+    gen_helper_mret(cpu_pc, cpu_env);
     tcg_gen_exit_tb(NULL, 0); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
     return true;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..095d39671b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -71,7 +71,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 
 #ifndef CONFIG_USER_ONLY
 
-target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
     target_ulong prev_priv, prev_virt;
@@ -132,7 +132,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
     return retpc;
 }
 
-target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
+target_ulong helper_mret(CPURISCVState *env)
 {
     if (!(env->priv >= PRV_M)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-- 
2.25.1



  parent reply	other threads:[~2021-11-10  7:15 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-10  7:04 [PATCH v2 00/14] Support UXL filed in xstatus LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10  9:42   ` LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-10 10:52   ` Richard Henderson
2021-11-10 13:44     ` LIU Zhiwei
2021-11-10 14:40       ` Richard Henderson
2021-11-11  5:04         ` LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10  7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11   ` Richard Henderson
2021-11-10 14:08     ` LIU Zhiwei
2021-11-10 14:43       ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29   ` Richard Henderson
2021-11-10  7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23   ` Richard Henderson
2021-11-10 14:26     ` LIU Zhiwei
2021-11-10 15:01       ` Richard Henderson
2021-11-10  7:04 ` LIU Zhiwei [this message]
2021-11-10 11:25   ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return Richard Henderson
2021-11-10  7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27   ` Richard Henderson
2021-11-10 14:38     ` LIU Zhiwei
2021-11-10 15:02       ` Richard Henderson

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