From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Alexey Baturo <baturo.alexey@gmail.com>
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN
Date: Wed, 10 Nov 2021 15:40:52 +0100 [thread overview]
Message-ID: <bbafca7f-1984-f030-cabc-b5f62ef5afd5@linaro.org> (raw)
In-Reply-To: <df0a3a5a-7ca5-b2dc-36c0-d802df99b5b0@c-sky.com>
On 11/10/21 2:44 PM, LIU Zhiwei wrote:
>> I suspect the extend should come before the pointer mask and not after, but this is is a
>> weakness in the current RVJ spec that it does not specify how the extension interacts
>> with UXL. (The reverse ordering would allow a 64-bit os to place a 32-bit application
>> at a base address above 4gb, which could allow address separation without paging enabled.)
>
> Agree. Should we adjust currently, or just add a TODO comment here?
Let's add a todo comment for sure.
>> I do think we should merge gen_pm_adjust_address into this function so that we only
>> create one new temporary.
>
> I think custom instructions will be added in the future. And possibly there will be some
> custom load/store instructions.
> If we merge gen_pm_adjust_address, we may have to split it once again at that time.
I don't think so. We're simply having one function to compute a canonical address from a
register plus offset plus mods.
Also, patch 10 combines pm-mask with zero-extension, so we shouldn't need to do both here.
The checks should be combined like
tcg_gen_addi_tl(addr, src1, imm);
if (ctx->pm_enabled) {
tcg_gen_and_tl(addr, addr, pm_mask);
tcg_gen_or_tl(addr, addr, pm_base);
} else if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
and could possibly be extended to
if (ctx->pm_mask_enabled) {
tcg_gen_and_tl(addr, addr, pm_mask);
} else if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
if (ctx->pm_base_enabled) {
tcg_gen_or_tl(addr, addr, pm_base);
}
with one more bit in TB_FLAGS, e.g.
if (env->cur_pm_mask < (xl == MVL_RV32 ? UINT32_MAX : UINT64_MAX)) {
flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
}
if (env->cur_pm_base != 0) {
flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
}
r~
next prev parent reply other threads:[~2021-11-10 14:41 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 7:04 [PATCH v2 00/14] Support UXL filed in xstatus LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10 9:42 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-10 10:52 ` Richard Henderson
2021-11-10 13:44 ` LIU Zhiwei
2021-11-10 14:40 ` Richard Henderson [this message]
2021-11-11 5:04 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11 ` Richard Henderson
2021-11-10 14:08 ` LIU Zhiwei
2021-11-10 14:43 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23 ` Richard Henderson
2021-11-10 14:26 ` LIU Zhiwei
2021-11-10 15:01 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-10 11:25 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27 ` Richard Henderson
2021-11-10 14:38 ` LIU Zhiwei
2021-11-10 15:02 ` Richard Henderson
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