From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen
Date: Wed, 10 Nov 2021 17:42:43 +0800 [thread overview]
Message-ID: <c4494f62-0063-4ff4-bf2f-c8ff6526924c@c-sky.com> (raw)
In-Reply-To: <20211110070452.48539-5-zhiwei_liu@c-sky.com>
On 2021/11/10 下午3:04, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/gdbstub.c | 73 +++++++++++++++++++++++++++++++-----------
> 1 file changed, 54 insertions(+), 19 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 23429179e2..7563414ef7 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -24,11 +24,25 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> + target_ulong tmp;
>
> if (n < 32) {
> - return gdb_get_regl(mem_buf, env->gpr[n]);
> + tmp = env->gpr[n];
> } else if (n == 32) {
> - return gdb_get_regl(mem_buf, env->pc);
> + tmp = env->pc;
> + } else {
> + return 0;
> + }
> +
> + switch (env->misa_mxl_max) {
> + case MXL_RV32:
> + gdb_get_reg32(mem_buf, tmp);
Oops. This is a typo. It should be
return gdb_get_reg32(mem_buf, tmp)
> + break;
> + case MXL_RV64:
> + gdb_get_reg64(mem_buf, tmp);
and
gdb_get_reg64(mem_buf, tmp);
Will fix it in next patch set.
Thanks,
Zhiwei
> + break;
> + default:
> + g_assert_not_reached();
> }
> return 0;
> }
> @@ -37,18 +51,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> -
> - if (n == 0) {
> - /* discard writes to x0 */
> - return sizeof(target_ulong);
> - } else if (n < 32) {
> - env->gpr[n] = ldtul_p(mem_buf);
> - return sizeof(target_ulong);
> + int length = 0;
> + target_ulong tmp;
> +
> + switch (env->misa_mxl_max) {
> + case MXL_RV32:
> + tmp = (int32_t)ldl_p(mem_buf);
> + length = 4;
> + break;
> + case MXL_RV64:
> + if (cpu_get_xl(env) < MXL_RV64) {
> + tmp = (int32_t)ldq_p(mem_buf);
> + } else {
> + tmp = ldq_p(mem_buf);
> + }
> + length = 8;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + if (n > 0 && n < 32) {
> + env->gpr[n] = tmp;
> } else if (n == 32) {
> - env->pc = ldtul_p(mem_buf);
> - return sizeof(target_ulong);
> + env->pc = tmp;
> }
> - return 0;
> +
> + return length;
> }
>
> static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
> @@ -198,13 +226,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-32bit-fpu.xml", 0);
> }
> -#if defined(TARGET_RISCV32)
> - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
> - 1, "riscv-32bit-virtual.xml", 0);
> -#elif defined(TARGET_RISCV64)
> - gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
> - 1, "riscv-64bit-virtual.xml", 0);
> -#endif
> + switch (env->misa_mxl_max) {
> + case MXL_RV32:
> + gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> + riscv_gdb_set_virtual,
> + 1, "riscv-32bit-virtual.xml", 0);
> + break;
> + case MXL_RV64:
> + gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> + riscv_gdb_set_virtual,
> + 1, "riscv-64bit-virtual.xml", 0);
> + break;
> + default:
> + g_assert_not_reached();
> + }
>
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
next prev parent reply other threads:[~2021-11-10 9:43 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 7:04 [PATCH v2 00/14] Support UXL filed in xstatus LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 01/14] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-10 10:18 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 02/14] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 03/14] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-10 9:42 ` LIU Zhiwei [this message]
2021-11-10 7:04 ` [PATCH v2 05/14] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-10 10:52 ` Richard Henderson
2021-11-10 13:44 ` LIU Zhiwei
2021-11-10 14:40 ` Richard Henderson
2021-11-11 5:04 ` LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 06/14] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-10 10:55 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 08/14] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-10 7:04 ` [PATCH v2 09/14] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-10 11:31 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 10/14] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-10 11:11 ` Richard Henderson
2021-11-10 14:08 ` LIU Zhiwei
2021-11-10 14:43 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-10 11:29 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 12/14] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-10 11:23 ` Richard Henderson
2021-11-10 14:26 ` LIU Zhiwei
2021-11-10 15:01 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 13/14] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-10 11:25 ` Richard Henderson
2021-11-10 7:04 ` [PATCH v2 14/14] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-10 11:27 ` Richard Henderson
2021-11-10 14:38 ` LIU Zhiwei
2021-11-10 15:02 ` Richard Henderson
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