Re: [PATCH v2 14/14] target/riscv: Enable uxl field write

[LIU Zhiwei <zhiwei_liu@c-sky.com>]

On 2021/11/10 下午7:27, Richard Henderson wrote:
> On 11/10/21 8:04 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>>   target/riscv/csr.c                      | 5 ++---
>>   target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
>>   target/riscv/op_helper.c                | 3 ++-
>>   3 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 33e342f529..e07cd522ef 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -555,15 +555,14 @@ static RISCVException 
>> write_mstatus(CPURISCVState *env, int csrno,
>>            * RV32: MPV and GVA are not in mstatus. The current plan 
>> is to
>>            * add them to mstatush. For now, we just don't support it.
>>            */
>> -        mask |= MSTATUS_MPV | MSTATUS_GVA;
>> +        mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
>>       }
>>         mstatus = (mstatus & ~mask) | (val & mask);
>>         if (riscv_cpu_mxl(env) == MXL_RV64) {
>> -        /* SXL and UXL fields are for now read only */
>> +        /* SXL fields are for now read only */
>>           mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
>> -        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
>>       }
>>       env->mstatus = mstatus;
>
> Why do you not allow writes to SXL?

That means we still don't support the change of SXLEN.
I didn't check the S-mode CSRs behavior when XLEN changes in this patch 
set.

For example, the behavior of satp when trap into M-mode from S-mode if 
SXLEN=32 and MXLEN=64.

>
> You're missing a change to write_sstatus to allow S-mode to write to UXL.
Yes.
>
>> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
>> b/target/riscv/insn_trans/trans_rvi.c.inc
>> index 7a0b037594..cb73a2f1ee 100644
>> --- a/target/riscv/insn_trans/trans_rvi.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
>> @@ -472,7 +472,7 @@ static bool trans_csrrw(DisasContext *ctx, 
>> arg_csrrw *a)
>>           return do_csrw(ctx, a->csr, src);
>>       }
>>   -    TCGv mask = tcg_constant_tl(-1);
>> +    TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX 
>> : -1);
>>       return do_csrrw(ctx, a->rd, a->csr, src, mask);
>>   }
>>   @@ -523,7 +523,7 @@ static bool trans_csrrwi(DisasContext *ctx, 
>> arg_csrrwi *a)
>>           return do_csrw(ctx, a->csr, src);
>>       }
>>   -    TCGv mask = tcg_constant_tl(-1);
>> +    TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX 
>> : -1);
>>       return do_csrrw(ctx, a->rd, a->csr, src, mask);
>>   }
>>   diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>> index 095d39671b..561e156bec 100644
>> --- a/target/riscv/op_helper.c
>> +++ b/target/riscv/op_helper.c
>> @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
>>     void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
>>   {
>> -    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
>> +    target_ulong mask = cpu_get_xl(env) == MXL_RV32 ? UINT32_MAX : -1;
>> +    RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
>>         if (ret != RISCV_EXCP_NONE) {
>>           riscv_raise_exception(env, ret, GETPC());
>>
>
> The rest of this should be a separate patch.
>
>
> r~