From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Alexander Graf <agraf@csgraf.de>, Cameron Esfahani <dirty@apple.com>
Cc: kettenis@openbsd.org, qemu-devel@nongnu.org,
AJ Barris <AwlsomeAlex@github.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Paolo Bonzini <pbonzini@redhat.com>,
osy@github.com
Subject: Re: [PATCH] hvf: arm: Ignore cache operations on MMIO
Date: Mon, 25 Oct 2021 22:57:00 +0200 [thread overview]
Message-ID: <21b998e6-f915-a96b-0802-41156b4db76a@amsat.org> (raw)
In-Reply-To: <20211025191349.52992-1-agraf@csgraf.de>
On 10/25/21 21:13, Alexander Graf wrote:
> Apple's Hypervisor.Framework forwards cache operations as MMIO traps
> into user space. For MMIO however, these have no meaning: There is no
> cache attached to them.
>
> So let's filter SYS instructions for DATA exits out and treat them as nops.
>
> This fixes OpenBSD booting as guest.
>
> Signed-off-by: Alexander Graf <agraf@csgraf.de>
> Reported-by: AJ Barris <AwlsomeAlex@github.com>
> ---
> target/arm/hvf/hvf.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index bff3e0cde7..46ff4892a7 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -1098,6 +1098,33 @@ static void hvf_sync_vtimer(CPUState *cpu)
> }
> }
>
> +static bool hvf_emulate_insn(CPUState *cpu)
> +{
> + ARMCPU *arm_cpu = ARM_CPU(cpu);
> + CPUARMState *env = &arm_cpu->env;
> + uint32_t insn;
> +
> + /*
> + * We ran into an instruction that traps for data, but is not
> + * hardware predecoded. This should not ever happen for well
> + * behaved guests. Let's try to see if we can somehow rescue
> + * the situation.
> + */
> +
> + cpu_synchronize_state(cpu);
> + if (cpu_memory_rw_debug(cpu, env->pc, &insn, 4, 0)) {
What about using cpu_ldl_data()?
> + /* Could not read the instruction */
> + return false;
> + }
> +
> + if ((insn & 0xffc00000) == 0xd5000000) {
Could there be an endianess issue here?
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> + /* MSR/MRS/SYS/SYSL - happens for cache ops which are nops on data */
> + return true;
> + }
> +
> + return false;
> +}
> +
> int hvf_vcpu_exec(CPUState *cpu)
> {
> ARMCPU *arm_cpu = ARM_CPU(cpu);
> @@ -1156,6 +1183,11 @@ int hvf_vcpu_exec(CPUState *cpu)
> hvf_exit->exception.physical_address, isv,
> iswrite, s1ptw, len, srt);
>
> + if (!isv) {
> + g_assert(hvf_emulate_insn(cpu));
> + advance_pc = true;
> + break;
> + }
> assert(isv);
>
> if (iswrite) {
>
next prev parent reply other threads:[~2021-10-25 20:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 19:13 [PATCH] hvf: arm: Ignore cache operations on MMIO Alexander Graf
2021-10-25 20:57 ` Philippe Mathieu-Daudé [this message]
2021-10-26 0:14 ` Richard Henderson
2021-10-26 7:09 ` Alexander Graf
2021-10-26 8:56 ` Philippe Mathieu-Daudé
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