From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Alexander Graf <agraf@csgraf.de>,
Richard Henderson <richard.henderson@linaro.org>,
Cameron Esfahani <dirty@apple.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
kettenis@openbsd.org, Roman Bolshakov <r.bolshakov@yadro.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH] hvf: arm: Ignore cache operations on MMIO
Date: Tue, 26 Oct 2021 10:56:47 +0200 [thread overview]
Message-ID: <d70b34c0-c228-c1f0-be52-01dd90d57f54@amsat.org> (raw)
In-Reply-To: <1d84fe5e-1933-8798-ff42-e752ea4e5943@csgraf.de>
On 10/26/21 09:09, Alexander Graf wrote:
> On 26.10.21 02:14, Richard Henderson wrote:
>> On 10/25/21 12:13 PM, Alexander Graf wrote:
>>> @@ -1156,6 +1183,11 @@ int hvf_vcpu_exec(CPUState *cpu)
>>> hvf_exit->exception.physical_address, isv,
>>> iswrite, s1ptw, len, srt);
>>> + if (!isv) {
>>> + g_assert(hvf_emulate_insn(cpu));
>>> + advance_pc = true;
>>> + break;
>>> + }
>>> assert(isv);
>>
>> Ouch. HVF really passes along an invalid syndrome? I was expecting
>> that you'd be able to avoid all of the instruction parsing and check
>> syndrome.cm (bit 8) for a cache management instruction.
>
>
> That's a very subtle way of telling me I'm stupid :). Thanks for the
> catch! Using the CM bit is obviously way better. Let me build v2.
Having given my R-b I take half of the blame.
prev parent reply other threads:[~2021-10-26 8:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 19:13 [PATCH] hvf: arm: Ignore cache operations on MMIO Alexander Graf
2021-10-25 20:57 ` Philippe Mathieu-Daudé
2021-10-26 0:14 ` Richard Henderson
2021-10-26 7:09 ` Alexander Graf
2021-10-26 8:56 ` Philippe Mathieu-Daudé [this message]
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