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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
	alistair23@gmail.com
Subject: [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro
Date: Fri,  2 Apr 2021 16:02:19 -0400	[thread overview]
Message-ID: <4b26392f1626590ee9064d43df4aef590472b72d.1617393702.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1617393702.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 6 ------
 target/riscv/csr.c      | 9 ++++++++-
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index caf4599207..969dd05eae 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -423,12 +423,6 @@
 #define SSTATUS32_SD        0x80000000
 #define SSTATUS64_SD        0x8000000000000000ULL
 
-#if defined(TARGET_RISCV32)
-#define SSTATUS_SD SSTATUS32_SD
-#elif defined(TARGET_RISCV64)
-#define SSTATUS_SD SSTATUS64_SD
-#endif
-
 /* hstatus CSR bits */
 #define HSTATUS_VSBE         0x00000020
 #define HSTATUS_GVA          0x00000040
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..832c3bf7fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -418,7 +418,7 @@ static const target_ulong delegable_excps =
     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
-    SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+    SSTATUS_SUM | SSTATUS_MXR;
 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 static const target_ulong hip_writable_mask = MIP_VSSIP;
 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
@@ -738,6 +738,13 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
 {
     target_ulong mask = (sstatus_v1_10_mask);
+
+    if (riscv_cpu_is_32bit(env)) {
+        mask |= SSTATUS32_SD;
+    } else {
+        mask |= SSTATUS64_SD;
+    }
+
     *val = env->mstatus & mask;
     return 0;
 }
-- 
2.31.0



  parent reply	other threads:[~2021-04-02 20:10 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02 20:02 [PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-02 20:02 ` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-05 14:48   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:02 ` Alistair Francis [this message]
2021-04-05 14:49   ` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-05 14:54   ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-05 15:10   ` Richard Henderson
2021-04-07 17:11     ` Alistair Francis
2021-04-08 15:20     ` Alistair Francis
2021-04-08 18:51       ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-05 15:14   ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-05 15:15   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-05 15:15   ` Richard Henderson
2021-04-12  9:10   ` Bin Meng
2021-04-02 20:03 ` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build Alistair Francis
2021-04-06 14:57   ` Richard Henderson

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