From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro
Date: Fri, 2 Apr 2021 16:02:31 -0400 [thread overview]
Message-ID: <7efb55362999a5b709ea8e7fa0ea188e740d9c67.1617393702.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1617393702.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 10 ----------
target/riscv/csr.c | 12 ++++++++++--
target/riscv/translate.c | 19 +++++++++++++++++--
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8caab23b62..dd643d0f63 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -387,16 +387,6 @@
#define MXL_RV64 2
#define MXL_RV128 3
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 832c3bf7fd..6052b2d6e9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -492,7 +492,11 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
- mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+ if (riscv_cpu_is_32bit(env)) {
+ mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+ } else {
+ mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+ }
env->mstatus = mstatus;
return 0;
@@ -564,7 +568,11 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
}
/* misa.MXL writes are not supported by QEMU */
- val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+ if (riscv_cpu_is_32bit(env)) {
+ val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+ } else {
+ val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+ }
/* flush translation cache */
if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2f9f5ccc62..9c6d998efa 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -369,6 +369,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ CPUState *cpu = ctx->cs;
+ CPURISCVState *env = cpu->env_ptr;
+
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
@@ -377,12 +380,24 @@ static void mark_fs_dirty(DisasContext *ctx)
tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ if (riscv_cpu_is_32bit(env)) {
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS32_SD);
+ } else {
+#if defined(TARGET_RISCV64)
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS64_SD);
+#endif
+ }
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ if (riscv_cpu_is_32bit(env)) {
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS32_SD);
+ } else {
+#if defined(TARGET_RISCV64)
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS64_SD);
+#endif
+ }
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tmp);
--
2.31.0
next prev parent reply other threads:[~2021-04-02 20:13 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-02 20:02 [PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-02 20:02 ` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-05 14:48 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-05 14:49 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-05 14:54 ` Richard Henderson
2021-04-02 20:02 ` Alistair Francis [this message]
2021-04-05 15:10 ` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro Richard Henderson
2021-04-07 17:11 ` Alistair Francis
2021-04-08 15:20 ` Alistair Francis
2021-04-08 18:51 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-05 15:14 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-05 15:15 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-05 15:15 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:03 ` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build Alistair Francis
2021-04-06 14:57 ` Richard Henderson
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