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From: Richard Henderson <richard.henderson@linaro.org>
To: matheus.ferst@eldorado.org.br, qemu-devel@nongnu.org,
	qemu-ppc@nongnu.org
Cc: lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br,
	luis.pires@eldorado.org.br, f4bug@amsat.org,
	david@gibson.dropbear.id.au
Subject: Re: [PATCH v4 30/31] target/ppc: Implement vcfuged instruction
Date: Thu, 13 May 2021 06:36:22 -0500	[thread overview]
Message-ID: <89dbecb1-085a-4d94-9d6d-6e193fde9fd7@linaro.org> (raw)
In-Reply-To: <20210512185441.3619828-31-matheus.ferst@eldorado.org.br>

On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
> 
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/insn32.decode               |  7 ++++
>   target/ppc/translate.c                 |  1 +
>   target/ppc/translate/vector-impl.c.inc | 50 ++++++++++++++++++++++++++
>   3 files changed, 58 insertions(+)
>   create mode 100644 target/ppc/translate/vector-impl.c.inc
> 
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 64788e2a4b..73b5ea0422 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -23,6 +23,9 @@
>   %ds_si          2:s14  !function=times_4
>   @DS             ...... rt:5 ra:5 .............. ..      &D si=%ds_si
>   
> +&VX             vrt vra vrb
> +@VX             ...... vrt:5 vra:5 vrb:5 .......... .   &VX
> +
>   &X              rt ra rb
>   @X              ...... rt:5 ra:5 rb:5 .......... .      &X
>   
> @@ -97,3 +100,7 @@ SETBC           011111 ..... ..... ----- 0110000000 -   @X_bi
>   SETBCR          011111 ..... ..... ----- 0110100000 -   @X_bi
>   SETNBC          011111 ..... ..... ----- 0111000000 -   @X_bi
>   SETNBCR         011111 ..... ..... ----- 0111100000 -   @X_bi
> +
> +## Vector Bit Manipulation Instruction
> +
> +VCFUGED         000100 ..... ..... ..... 10101001101    @VX
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 477e3deede..847de8e012 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7627,6 +7627,7 @@ static int times_4(DisasContext *ctx, int x)
>   #include "translate/vmx-impl.c.inc"
>   
>   #include "translate/vsx-impl.c.inc"
> +#include "translate/vector-impl.c.inc"
>   
>   #include "translate/dfp-impl.c.inc"
>   
> diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
> new file mode 100644
> index 0000000000..4e07de5671
> --- /dev/null
> +++ b/target/ppc/translate/vector-impl.c.inc
> @@ -0,0 +1,50 @@
> +/*
> + * Power ISA decode for Vector Facility instructions
> + *
> + * Copyright (c) 2021 Matheus Ferst <matheus.ferst@eldorado.org.br>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
> +{
> +    TCGv_i64 tgt, src, mask;
> +
> +    if (unlikely(!ctx->altivec_enabled)) {
> +        gen_exception(ctx, POWERPC_EXCP_VPU);
> +        return true;
> +    }

You have to REQUIRE_INSN_FLAGS(something) before checking for altivec_enabled.

You're going to want to create some boilerplate for this, because it's going to 
get repeated a *lot*.

> +    // centrifuge lower double word
> +    get_cpu_vsrl(src, a->vra+32);
> +    get_cpu_vsrl(mask, a->vrb+32);
> +    gen_helper_cfuged(tgt, src, mask);
> +    set_cpu_vsrl(a->vrt+32, tgt);
> +
> +    // centrifuge higher double word
> +    get_cpu_vsrh(src, a->vra+32);
> +    get_cpu_vsrh(mask, a->vrb+32);
> +    gen_helper_cfuged(tgt, src, mask);
> +    set_cpu_vsrh(a->vrt+32, tgt);

This has multiple checkpatch errors.


r~


  reply	other threads:[~2021-05-13 11:41 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
2021-05-13  4:03   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
2021-05-13  4:03   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
2021-05-13  4:06   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
2021-05-13  4:06   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
2021-05-13  4:07   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
2021-05-13  4:08   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
2021-05-13  4:10   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
2021-05-12 19:31   ` Bruno Piazera Larsen
2021-05-13  4:11   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
2021-05-13  4:12   ` David Gibson
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-12 19:21   ` Matheus K. Ferst
2021-05-13  4:14     ` David Gibson
2021-05-12 18:54 ` [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-12 18:54 ` [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-12 18:54 ` [PATCH v4 13/31] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-12 18:54 ` [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-12 18:54 ` [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-12 18:54 ` [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-12 19:45   ` Bruno Piazera Larsen
2021-05-12 18:54 ` [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-12 18:54 ` [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
2021-05-13 10:37   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
2021-05-13 10:42   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-13 10:50   ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-13 11:01   ` Richard Henderson
2021-05-13 11:43     ` Matheus K. Ferst
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-13 11:31   ` Richard Henderson
2021-05-13 12:24     ` Matheus K. Ferst
2021-05-14  0:01       ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-13 11:36   ` Richard Henderson [this message]
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-13 11:40   ` Richard Henderson
2021-05-13  4:22 ` [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions David Gibson

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