[PATCH v2 0/5] target/arm: various changes to cpu.h

[PATCH v2 0/5] target/arm: various changes to cpu.h

[Leif Lindholm]

First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS).

Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined
by the ARM ARM.

Third, add field definitions for CLIDR (excepting the Ttype<n> fields, since
I was unsure of prefererred naming - Ttype7-Ttype1?).

Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c,

Lastly, add all ID_ (aarch32) registers/fields.

Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be
submitting shortly, and some of those features also exist for aarch32.

v1->v2:
- Correct CCSIDR_EL1 field sizes in 3/5.
- Rebase to current master.

Leif Lindholm (5):
  target/arm: fix typo in cpu.h ID_AA64PFR1 field name
  target/arm: make ARMCPU.clidr 64-bit
  target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to
    cpu.h
  target/arm: add aarch64 ID register fields to cpu.h
  target/arm: add aarch32 ID register fields to cpu.h

 target/arm/cpu.h | 71 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 69 insertions(+), 2 deletions(-)

-- 
2.20.1

[PATCH v2 1/5] target/arm: fix typo in cpu.h ID_AA64PFR1 field name

[Leif Lindholm]

SBSS -> SSBS

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7e6c881a7e..5e3cf77ec7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1883,7 +1883,7 @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
-FIELD(ID_AA64PFR1, SBSS, 4, 4)
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
 
-- 
2.20.1

Re: [PATCH v2 1/5] target/arm: fix typo in cpu.h ID_AA64PFR1 field name

[Laurent Desnogues]

On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> SBSS -> SSBS
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target/arm/cpu.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 7e6c881a7e..5e3cf77ec7 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1883,7 +1883,7 @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
>  FIELD(ID_AA64PFR0, SVE, 32, 4)
>
>  FIELD(ID_AA64PFR1, BT, 0, 4)
> -FIELD(ID_AA64PFR1, SBSS, 4, 4)
> +FIELD(ID_AA64PFR1, SSBS, 4, 4)
>  FIELD(ID_AA64PFR1, MTE, 8, 4)
>  FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
>
> --
> 2.20.1
>
>

[PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit

[Leif Lindholm]

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5e3cf77ec7..fadd1a47df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -938,7 +938,7 @@ struct ARMCPU {
     uint32_t id_afr0;
     uint64_t id_aa64afr0;
     uint64_t id_aa64afr1;
-    uint32_t clidr;
+    uint64_t clidr;
     uint64_t mp_affinity; /* MP ID without feature bits */
     /* The elements of this array are the CCSIDR values for each cache,
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
-- 
2.20.1

Re: [PATCH v2 2/5] target/arm: make ARMCPU.clidr 64-bit

[Laurent Desnogues]

On Tue, Dec 15, 2020 at 12:52 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
> 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
> Extend the clidr field to be able to hold this context.
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target/arm/cpu.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 5e3cf77ec7..fadd1a47df 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -938,7 +938,7 @@ struct ARMCPU {
>      uint32_t id_afr0;
>      uint64_t id_aa64afr0;
>      uint64_t id_aa64afr1;
> -    uint32_t clidr;
> +    uint64_t clidr;
>      uint64_t mp_affinity; /* MP ID without feature bits */
>      /* The elements of this array are the CCSIDR values for each cache,
>       * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
> --
> 2.20.1
>
>

[PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Leif Lindholm]

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fadd1a47df..90ba707b64 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-- 
2.20.1

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Laurent Desnogues]

Hello,

On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> ---
>  target/arm/cpu.h | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index fadd1a47df..90ba707b64 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
>  /*
>   * System register ID fields.
>   */
> +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> +FIELD(CLIDR_EL1, LOC, 24, 3)
> +FIELD(CLIDR_EL1, LOUU, 27, 3)
> +FIELD(CLIDR_EL1, ICB, 30, 3)
> +
> +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)

The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
depend on whether the ARMv8.3-CCIDX extension is implemented or not.
If we really want to define the fields this way, we perhaps should
define two sets.  Or at the very least, add a comment stating this
definition is for ARMv8.3-CCIDX.

> +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> +FIELD(CTR_EL0,  L1IP, 14, 2)
> +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> +FIELD(CTR_EL0,  ERG, 20, 4)
> +FIELD(CTR_EL0,  CWG, 24, 4)
> +FIELD(CTR_EL0,  IDC, 28, 1)
> +FIELD(CTR_EL0,  DIC, 29, 1)

There's a missing field:  TminLine which starts at bit 32.  If
implemented, that would require to make ctr a 64-bit integer.

Thanks,

Laurent

> +
>  FIELD(MIDR_EL1, REVISION, 0, 4)
>  FIELD(MIDR_EL1, PARTNUM, 4, 12)
>  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> --
> 2.20.1
>
>

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Leif Lindholm]

On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> Hello,
> 
> On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > ---
> >  target/arm/cpu.h | 24 ++++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >
> > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > index fadd1a47df..90ba707b64 100644
> > --- a/target/arm/cpu.h
> > +++ b/target/arm/cpu.h
> > @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
> >  /*
> >   * System register ID fields.
> >   */
> > +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> > +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> > +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> > +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> > +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> > +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> > +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> > +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> > +FIELD(CLIDR_EL1, LOC, 24, 3)
> > +FIELD(CLIDR_EL1, LOUU, 27, 3)
> > +FIELD(CLIDR_EL1, ICB, 30, 3)
> > +
> > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> 
> The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> If we really want to define the fields this way, we perhaps should
> define two sets.  Or at the very least, add a comment stating this
> definition is for ARMv8.3-CCIDX.

Urgh, sorry for this.
I added the fields only to make the CPU definition more readable, so I
think we don't need to worry about runtime handling of this?
But I don't think it makes sense to add only the one form.
Should I use CCIDX_CCSIDR_EL1 for these ones and add

/* When FEAT_CCIDX is not implemented */
FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
FIELD(CCSIDR_EL1, NUMSETS, 13, 15)

with a comment that
/* When FEAT_CCIDX is implemented */
for the former set
?

> > +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> > +FIELD(CTR_EL0,  L1IP, 14, 2)
> > +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> > +FIELD(CTR_EL0,  ERG, 20, 4)
> > +FIELD(CTR_EL0,  CWG, 24, 4)
> > +FIELD(CTR_EL0,  IDC, 28, 1)
> > +FIELD(CTR_EL0,  DIC, 29, 1)
> 
> There's a missing field:  TminLine which starts at bit 32.

Ack, oops.

> If
> implemented, that would require to make ctr a 64-bit integer.

As far as I can tell, this will be safe with existing code - should I
fold in a patch extending the register?

Regards,

Leif

> Thanks,
> 
> Laurent
> 
> > +
> >  FIELD(MIDR_EL1, REVISION, 0, 4)
> >  FIELD(MIDR_EL1, PARTNUM, 4, 12)
> >  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> > --
> > 2.20.1
> >
> >

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Laurent Desnogues]

Hi Leif,

On Tue, Dec 15, 2020 at 5:49 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> > Hello,
> >
> > On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
> > >
> > > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > > ---
> > >  target/arm/cpu.h | 24 ++++++++++++++++++++++++
> > >  1 file changed, 24 insertions(+)
> > >
> > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > > index fadd1a47df..90ba707b64 100644
> > > --- a/target/arm/cpu.h
> > > +++ b/target/arm/cpu.h
> > > @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
> > >  /*
> > >   * System register ID fields.
> > >   */
> > > +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> > > +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> > > +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> > > +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> > > +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> > > +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> > > +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> > > +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> > > +FIELD(CLIDR_EL1, LOC, 24, 3)
> > > +FIELD(CLIDR_EL1, LOUU, 27, 3)
> > > +FIELD(CLIDR_EL1, ICB, 30, 3)
> > > +
> > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> >
> > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > If we really want to define the fields this way, we perhaps should
> > define two sets.  Or at the very least, add a comment stating this
> > definition is for ARMv8.3-CCIDX.
>
> Urgh, sorry for this.
> I added the fields only to make the CPU definition more readable, so I
> think we don't need to worry about runtime handling of this?
> But I don't think it makes sense to add only the one form.
> Should I use CCIDX_CCSIDR_EL1 for these ones and add
>
> /* When FEAT_CCIDX is not implemented */
> FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
>
> with a comment that
> /* When FEAT_CCIDX is implemented */
> for the former set
> ?

Having both would be handy, but you need to have different names for
the fields.  For setting fields up in cpu{64}.c that'd be acceptable
as you know if the CPU you define has ARMv8.3-CCIDX. In the rest of
the code the use would be more complicated as you'd have to check for
ARMv8.3-CCIDX before accessing fields.  But the use of those fields
outside of cpu{64}.c would likely be extremely limited so I don't
think that's an issue.

> > > +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> > > +FIELD(CTR_EL0,  L1IP, 14, 2)
> > > +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> > > +FIELD(CTR_EL0,  ERG, 20, 4)
> > > +FIELD(CTR_EL0,  CWG, 24, 4)
> > > +FIELD(CTR_EL0,  IDC, 28, 1)
> > > +FIELD(CTR_EL0,  DIC, 29, 1)
> >
> > There's a missing field:  TminLine which starts at bit 32.
>
> Ack, oops.
>
> > If
> > implemented, that would require to make ctr a 64-bit integer.
>
> As far as I can tell, this will be safe with existing code - should I
> fold in a patch extending the register?

IMHO it'd be better to extend ctr to 64-bit.  But I'm not sure of the
implications in the rest of the code.

Thanks,

Laurent

> Regards,
>
> Leif
>
> > Thanks,
> >
> > Laurent
> >
> > > +
> > >  FIELD(MIDR_EL1, REVISION, 0, 4)
> > >  FIELD(MIDR_EL1, PARTNUM, 4, 12)
> > >  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> > > --
> > > 2.20.1
> > >
> > >

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Leif Lindholm]

Hi Laurent,

On Thu, Dec 17, 2020 at 11:02:23 +0100, Laurent Desnogues wrote:
> Hi Leif,
> 
> On Tue, Dec 15, 2020 at 5:49 PM Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> > > Hello,
> > >
> > > On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
> > > >
> > > > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > > > ---
> > > >  target/arm/cpu.h | 24 ++++++++++++++++++++++++
> > > >  1 file changed, 24 insertions(+)
> > > >
> > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > > > index fadd1a47df..90ba707b64 100644
> > > > --- a/target/arm/cpu.h
> > > > +++ b/target/arm/cpu.h
> > > > @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
> > > >  /*
> > > >   * System register ID fields.
> > > >   */
> > > > +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> > > > +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> > > > +FIELD(CLIDR_EL1, LOC, 24, 3)
> > > > +FIELD(CLIDR_EL1, LOUU, 27, 3)
> > > > +FIELD(CLIDR_EL1, ICB, 30, 3)
> > > > +
> > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> > >
> > > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > > If we really want to define the fields this way, we perhaps should
> > > define two sets.  Or at the very least, add a comment stating this
> > > definition is for ARMv8.3-CCIDX.
> >
> > Urgh, sorry for this.
> > I added the fields only to make the CPU definition more readable, so I
> > think we don't need to worry about runtime handling of this?
> > But I don't think it makes sense to add only the one form.
> > Should I use CCIDX_CCSIDR_EL1 for these ones and add
> >
> > /* When FEAT_CCIDX is not implemented */
> > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> > FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
> >
> > with a comment that
> > /* When FEAT_CCIDX is implemented */
> > for the former set
> > ?
> 
> Having both would be handy, but you need to have different names for
> the fields.

Different names for the same field?
I.e.
FIELD(CCIDX_CCSIDR_EL1, LINESIZE, 0, 3)
would need a different name for LINESIZE than
FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
?

> For setting fields up in cpu{64}.c that'd be acceptable
> as you know if the CPU you define has ARMv8.3-CCIDX. In the rest of
> the code the use would be more complicated as you'd have to check for
> ARMv8.3-CCIDX before accessing fields.  But the use of those fields
> outside of cpu{64}.c would likely be extremely limited so I don't
> think that's an issue.

Yeah, QEMU itself currently doesn't look into the fields at all.

> > > > +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> > > > +FIELD(CTR_EL0,  L1IP, 14, 2)
> > > > +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> > > > +FIELD(CTR_EL0,  ERG, 20, 4)
> > > > +FIELD(CTR_EL0,  CWG, 24, 4)
> > > > +FIELD(CTR_EL0,  IDC, 28, 1)
> > > > +FIELD(CTR_EL0,  DIC, 29, 1)
> > >
> > > There's a missing field:  TminLine which starts at bit 32.
> >
> > Ack, oops.
> >
> > > If
> > > implemented, that would require to make ctr a 64-bit integer.
> >
> > As far as I can tell, this will be safe with existing code - should I
> > fold in a patch extending the register?
> 
> IMHO it'd be better to extend ctr to 64-bit.  But I'm not sure of the
> implications in the rest of the code.

Sorry, I was ambivalent in my message: I meant that (at a glance it
looked like) existing code should be fine with extending it to
64-bit. So I'll do that.

Best Regards,

Leif

> 
> Thanks,
> 
> Laurent
> 
> > Regards,
> >
> > Leif
> >
> > > Thanks,
> > >
> > > Laurent
> > >
> > > > +
> > > >  FIELD(MIDR_EL1, REVISION, 0, 4)
> > > >  FIELD(MIDR_EL1, PARTNUM, 4, 12)
> > > >  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> > > > --
> > > > 2.20.1
> > > >
> > > >

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Laurent Desnogues]

On Thu, Dec 17, 2020 at 1:10 PM Leif Lindholm <leif@nuviainc.com> wrote:
[...]
> > > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> > > >
> > > > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > > > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > > > If we really want to define the fields this way, we perhaps should
> > > > define two sets.  Or at the very least, add a comment stating this
> > > > definition is for ARMv8.3-CCIDX.
> > >
> > > Urgh, sorry for this.
> > > I added the fields only to make the CPU definition more readable, so I
> > > think we don't need to worry about runtime handling of this?
> > > But I don't think it makes sense to add only the one form.
> > > Should I use CCIDX_CCSIDR_EL1 for these ones and add
> > >
> > > /* When FEAT_CCIDX is not implemented */
> > > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> > > FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
> > >
> > > with a comment that
> > > /* When FEAT_CCIDX is implemented */
> > > for the former set
> > > ?
> >
> > Having both would be handy, but you need to have different names for
> > the fields.
>
> Different names for the same field?
> I.e.
> FIELD(CCIDX_CCSIDR_EL1, LINESIZE, 0, 3)
> would need a different name for LINESIZE than
> FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> ?

I was thinking about changing the field names, not the register name
because the register is the same, only the layout changes.  So
LINESIZE -> CCIDX_LINESIZE, etc.

That's personal preference, Peter might have a different one.

Thanks,

Laurent

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Leif Lindholm]

On Thu, Dec 17, 2020 at 13:18:03 +0100, Laurent Desnogues wrote:
> On Thu, Dec 17, 2020 at 1:10 PM Leif Lindholm <leif@nuviainc.com> wrote:
> [...]
> > > > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > > > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> > > > >
> > > > > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > > > > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > > > > If we really want to define the fields this way, we perhaps should
> > > > > define two sets.  Or at the very least, add a comment stating this
> > > > > definition is for ARMv8.3-CCIDX.
> > > >
> > > > Urgh, sorry for this.
> > > > I added the fields only to make the CPU definition more readable, so I
> > > > think we don't need to worry about runtime handling of this?
> > > > But I don't think it makes sense to add only the one form.
> > > > Should I use CCIDX_CCSIDR_EL1 for these ones and add
> > > >
> > > > /* When FEAT_CCIDX is not implemented */
> > > > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> > > > FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
> > > >
> > > > with a comment that
> > > > /* When FEAT_CCIDX is implemented */
> > > > for the former set
> > > > ?
> > >
> > > Having both would be handy, but you need to have different names for
> > > the fields.
> >
> > Different names for the same field?
> > I.e.
> > FIELD(CCIDX_CCSIDR_EL1, LINESIZE, 0, 3)
> > would need a different name for LINESIZE than
> > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > ?
> 
> I was thinking about changing the field names, not the register name
> because the register is the same, only the layout changes.  So
> LINESIZE -> CCIDX_LINESIZE, etc.
> 
> That's personal preference, Peter might have a different one.

I see. Sure, that works too, and doesn't pollute the register name.
I'll wait for Peter before sending out v3.

Thanks!

/
    Leif

> 
> Thanks,
> 
> Laurent

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Peter Maydell]

On Thu, 17 Dec 2020 at 12:24, Leif Lindholm <leif@nuviainc.com> wrote:
>
> On Thu, Dec 17, 2020 at 13:18:03 +0100, Laurent Desnogues wrote:
> > I was thinking about changing the field names, not the register name
> > because the register is the same, only the layout changes.  So
> > LINESIZE -> CCIDX_LINESIZE, etc.
> >
> > That's personal preference, Peter might have a different one.
>
> I see. Sure, that works too, and doesn't pollute the register name.
> I'll wait for Peter before sending out v3.

Laurent's suggestion works for me.

thanks
-- PMM

[PATCH v2 4/5] target/arm: add aarch64 ID register fields to cpu.h

[Leif Lindholm]

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 90ba707b64..efa977eaca 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1895,6 +1895,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
 FIELD(ID_AA64ISAR1, SB, 36, 4)
 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -1905,11 +1908,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -1923,6 +1933,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
 FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
 
 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -1932,6 +1944,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
 FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -1958,6 +1972,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
-- 
2.20.1

Re: [PATCH v2 4/5] target/arm: add aarch64 ID register fields to cpu.h

[Laurent Desnogues]

On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Add entries present in ARM DDI 0487F.c (August 2020).
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target/arm/cpu.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 90ba707b64..efa977eaca 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1895,6 +1895,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
>  FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
>  FIELD(ID_AA64ISAR1, SB, 36, 4)
>  FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
> +FIELD(ID_AA64ISAR1, BF16, 44, 4)
> +FIELD(ID_AA64ISAR1, DGH, 48, 4)
> +FIELD(ID_AA64ISAR1, I8MM, 52, 4)
>
>  FIELD(ID_AA64PFR0, EL0, 0, 4)
>  FIELD(ID_AA64PFR0, EL1, 4, 4)
> @@ -1905,11 +1908,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
>  FIELD(ID_AA64PFR0, GIC, 24, 4)
>  FIELD(ID_AA64PFR0, RAS, 28, 4)
>  FIELD(ID_AA64PFR0, SVE, 32, 4)
> +FIELD(ID_AA64PFR0, SEL2, 36, 4)
> +FIELD(ID_AA64PFR0, MPAM, 40, 4)
> +FIELD(ID_AA64PFR0, AMU, 44, 4)
> +FIELD(ID_AA64PFR0, DIT, 48, 4)
> +FIELD(ID_AA64PFR0, CSV2, 56, 4)
> +FIELD(ID_AA64PFR0, CSV3, 60, 4)
>
>  FIELD(ID_AA64PFR1, BT, 0, 4)
>  FIELD(ID_AA64PFR1, SSBS, 4, 4)
>  FIELD(ID_AA64PFR1, MTE, 8, 4)
>  FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
> +FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
>
>  FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
>  FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
> @@ -1923,6 +1933,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
>  FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
>  FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
>  FIELD(ID_AA64MMFR0, EXS, 44, 4)
> +FIELD(ID_AA64MMFR0, FGT, 56, 4)
> +FIELD(ID_AA64MMFR0, ECV, 60, 4)
>
>  FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
>  FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
> @@ -1932,6 +1944,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
>  FIELD(ID_AA64MMFR1, PAN, 20, 4)
>  FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
>  FIELD(ID_AA64MMFR1, XNX, 28, 4)
> +FIELD(ID_AA64MMFR1, TWED, 32, 4)
> +FIELD(ID_AA64MMFR1, ETS, 36, 4)
>
>  FIELD(ID_AA64MMFR2, CNP, 0, 4)
>  FIELD(ID_AA64MMFR2, UAO, 4, 4)
> @@ -1958,6 +1972,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
>  FIELD(ID_AA64DFR0, PMSVER, 32, 4)
>  FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
>  FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
> +FIELD(ID_AA64DFR0, MTPMU, 48, 4)
>
>  FIELD(ID_DFR0, COPDBG, 0, 4)
>  FIELD(ID_DFR0, COPSDBG, 4, 4)
> --
> 2.20.1
>
>

[PATCH v2 5/5] target/arm: add aarch32 ID register fields to cpu.h

[Leif Lindholm]

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa977eaca..fb81eed776 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1823,6 +1823,8 @@ FIELD(ID_ISAR6, DP, 4, 4)
 FIELD(ID_ISAR6, FHM, 8, 4)
 FIELD(ID_ISAR6, SB, 12, 4)
 FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
 
 FIELD(ID_MMFR0, VMSA, 0, 4)
 FIELD(ID_MMFR0, PMSA, 4, 4)
@@ -1833,6 +1835,24 @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
 FIELD(ID_MMFR0, FCSE, 24, 4)
 FIELD(ID_MMFR0, INNERSHR, 28, 4)
 
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
 FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -1851,6 +1871,8 @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_MMFR5, ETS, 0, 4)
+
 FIELD(ID_PFR0, STATE0, 0, 4)
 FIELD(ID_PFR0, STATE1, 4, 4)
 FIELD(ID_PFR0, STATE2, 8, 4)
@@ -1869,6 +1891,10 @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
 FIELD(ID_PFR1, GIC, 28, 4)
 
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
 FIELD(ID_AA64ISAR0, AES, 4, 4)
 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -1983,6 +2009,8 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(ID_DFR1, MTPMU, 0, 4)
+
 FIELD(DBGDIDR, SE_IMP, 12, 1)
 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
 FIELD(DBGDIDR, VERSION, 16, 4)
-- 
2.20.1

Re: [PATCH v2 5/5] target/arm: add aarch32 ID register fields to cpu.h

[Laurent Desnogues]

On Tue, Dec 15, 2020 at 12:52 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Add entries present in ARM DDI 0487F.c (August 2020).
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index efa977eaca..fb81eed776 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1823,6 +1823,8 @@ FIELD(ID_ISAR6, DP, 4, 4)
>  FIELD(ID_ISAR6, FHM, 8, 4)
>  FIELD(ID_ISAR6, SB, 12, 4)
>  FIELD(ID_ISAR6, SPECRES, 16, 4)
> +FIELD(ID_ISAR6, BF16, 20, 4)
> +FIELD(ID_ISAR6, I8MM, 24, 4)
>
>  FIELD(ID_MMFR0, VMSA, 0, 4)
>  FIELD(ID_MMFR0, PMSA, 4, 4)
> @@ -1833,6 +1835,24 @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
>  FIELD(ID_MMFR0, FCSE, 24, 4)
>  FIELD(ID_MMFR0, INNERSHR, 28, 4)
>
> +FIELD(ID_MMFR1, L1HVDVA, 0, 4)
> +FIELD(ID_MMFR1, L1UNIVA, 4, 4)
> +FIELD(ID_MMFR1, L1HVDSW, 8, 4)
> +FIELD(ID_MMFR1, L1UNISW, 12, 4)
> +FIELD(ID_MMFR1, L1HVD, 16, 4)
> +FIELD(ID_MMFR1, L1UNI, 20, 4)
> +FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
> +FIELD(ID_MMFR1, BPRED, 28, 4)
> +
> +FIELD(ID_MMFR2, L1HVDFG, 0, 4)
> +FIELD(ID_MMFR2, L1HVDBG, 4, 4)
> +FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
> +FIELD(ID_MMFR2, HVDTLB, 12, 4)
> +FIELD(ID_MMFR2, UNITLB, 16, 4)
> +FIELD(ID_MMFR2, MEMBARR, 20, 4)
> +FIELD(ID_MMFR2, WFISTALL, 24, 4)
> +FIELD(ID_MMFR2, HWACCFLG, 28, 4)
> +
>  FIELD(ID_MMFR3, CMAINTVA, 0, 4)
>  FIELD(ID_MMFR3, CMAINTSW, 4, 4)
>  FIELD(ID_MMFR3, BPMAINT, 8, 4)
> @@ -1851,6 +1871,8 @@ FIELD(ID_MMFR4, LSM, 20, 4)
>  FIELD(ID_MMFR4, CCIDX, 24, 4)
>  FIELD(ID_MMFR4, EVT, 28, 4)
>
> +FIELD(ID_MMFR5, ETS, 0, 4)
> +
>  FIELD(ID_PFR0, STATE0, 0, 4)
>  FIELD(ID_PFR0, STATE1, 4, 4)
>  FIELD(ID_PFR0, STATE2, 8, 4)
> @@ -1869,6 +1891,10 @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
>  FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
>  FIELD(ID_PFR1, GIC, 28, 4)
>
> +FIELD(ID_PFR2, CSV3, 0, 4)
> +FIELD(ID_PFR2, SSBS, 4, 4)
> +FIELD(ID_PFR2, RAS_FRAC, 8, 4)
> +
>  FIELD(ID_AA64ISAR0, AES, 4, 4)
>  FIELD(ID_AA64ISAR0, SHA1, 8, 4)
>  FIELD(ID_AA64ISAR0, SHA2, 12, 4)
> @@ -1983,6 +2009,8 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
>  FIELD(ID_DFR0, PERFMON, 24, 4)
>  FIELD(ID_DFR0, TRACEFILT, 28, 4)
>
> +FIELD(ID_DFR1, MTPMU, 0, 4)
> +
>  FIELD(DBGDIDR, SE_IMP, 12, 1)
>  FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
>  FIELD(DBGDIDR, VERSION, 16, 4)
> --
> 2.20.1
>
>

Re: [PATCH v2 0/5] target/arm: various changes to cpu.h

[Peter Maydell]

On Tue, 15 Dec 2020 at 11:48, Leif Lindholm <leif@nuviainc.com> wrote:
>
> First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS).
>
> Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined
> by the ARM ARM.
>
> Third, add field definitions for CLIDR (excepting the Ttype<n> fields, since
> I was unsure of prefererred naming - Ttype7-Ttype1?).
>
> Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c,
>
> Lastly, add all ID_ (aarch32) registers/fields.
>
> Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be
> submitting shortly, and some of those features also exist for aarch32.
>
> v1->v2:
> - Correct CCSIDR_EL1 field sizes in 3/5.
> - Rebase to current master.


What happened to the various Reviewed-by:s that people gave you for
patches in the v1 series ?

thanks
-- PMM

Re: [PATCH v2 0/5] target/arm: various changes to cpu.h

[Leif Lindholm]

On Tue, Dec 15, 2020 at 12:11:43 +0000, Peter Maydell wrote:
> On Tue, 15 Dec 2020 at 11:48, Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS).
> >
> > Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined
> > by the ARM ARM.
> >
> > Third, add field definitions for CLIDR (excepting the Ttype<n> fields, since
> > I was unsure of prefererred naming - Ttype7-Ttype1?).
> >
> > Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c,
> >
> > Lastly, add all ID_ (aarch32) registers/fields.
> >
> > Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be
> > submitting shortly, and some of those features also exist for aarch32.
> >
> > v1->v2:
> > - Correct CCSIDR_EL1 field sizes in 3/5.
> > - Rebase to current master.
> 
> What happened to the various Reviewed-by:s that people gave you for
> patches in the v1 series ?

Melted away in excessive multitasking, sigh.
Sorry, v3 coming up.

/
    Leif

[PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Leif Lindholm]

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
v1->v2:
- Correct CCSIDR_EL1 field sizes.

 target/arm/cpu.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fadd1a47df..90ba707b64 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-- 
2.20.1

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Peter Maydell]

On Mon, 14 Dec 2020 at 12:36, Leif Lindholm <leif@nuviainc.com> wrote:
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> ---
> v1->v2:
> - Correct CCSIDR_EL1 field sizes.

Hi -- could you resend the whole series for a v2, please?
The tools (and people) that handle patches get a bit confused
by partial series.

thanks
-- PMM

Re: [PATCH v2 3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

[Leif Lindholm]

On Mon, Dec 14, 2020 at 13:36:51 +0000, Peter Maydell wrote:
> On Mon, 14 Dec 2020 at 12:36, Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > ---
> > v1->v2:
> > - Correct CCSIDR_EL1 field sizes.
> 
> Hi -- could you resend the whole series for a v2, please?
> The tools (and people) that handle patches get a bit confused
> by partial series.

Of course :)
Done, and noted for future.

/
    Leif