* [PULL 0/4] tcg patch queue
@ 2024-01-10 21:52 Richard Henderson
2024-01-10 21:52 ` [PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128 Richard Henderson
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: Richard Henderson @ 2024-01-10 21:52 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:
Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240111
for you to fetch changes up to 1d513e06d96697f44de4a1b85c6ff627c443e306:
util: fix build with musl libc on ppc64le (2024-01-11 08:48:16 +1100)
----------------------------------------------------------------
tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
tcg/ppc: Use new registers for LQ destination
util: fix build with musl libc on ppc64le
----------------------------------------------------------------
Natanael Copa (1):
util: fix build with musl libc on ppc64le
Paolo Bonzini (2):
tcg/i386: convert add/sub of 128 to sub/add of -128
tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
Richard Henderson (1):
tcg/ppc: Use new registers for LQ destination
tcg/ppc/tcg-target-con-set.h | 2 +-
tcg/tcg.c | 21 ++++++++++++----
util/cpuinfo-ppc.c | 6 ++---
tcg/i386/tcg-target.c.inc | 60 +++++++++++++++++++++++++++++++++-----------
tcg/ppc/tcg-target.c.inc | 3 ++-
5 files changed, 67 insertions(+), 25 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128
2024-01-10 21:52 [PULL 0/4] tcg patch queue Richard Henderson
@ 2024-01-10 21:52 ` Richard Henderson
2024-01-10 21:52 ` [PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates Richard Henderson
` (3 subsequent siblings)
4 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-01-10 21:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini
From: Paolo Bonzini <pbonzini@redhat.com>
Extend the existing conditional that generates INC/DEC, to also swap an
ADD for a SUB and vice versa when the immediate is 128. This facilitates
using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231228120514.70205-1-pbonzini@redhat.com>
[rth: Use a switch on C]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++++++------------
1 file changed, 34 insertions(+), 15 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index a83f8aab30..29e80af78b 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1316,23 +1316,41 @@ static void tgen_arithi(TCGContext *s, int c, int r0,
c &= 7;
}
- /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
- partial flags update stalls on Pentium4 and are not recommended
- by current Intel optimization manuals. */
- if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
- int is_inc = (c == ARITH_ADD) ^ (val < 0);
- if (TCG_TARGET_REG_BITS == 64) {
- /* The single-byte increment encodings are re-tasked as the
- REX prefixes. Use the MODRM encoding. */
- tcg_out_modrm(s, OPC_GRP5 + rexw,
- (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
- } else {
- tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
+ switch (c) {
+ case ARITH_ADD:
+ case ARITH_SUB:
+ if (!cf) {
+ /*
+ * ??? While INC is 2 bytes shorter than ADDL $1, they also induce
+ * partial flags update stalls on Pentium4 and are not recommended
+ * by current Intel optimization manuals.
+ */
+ if (val == 1 || val == -1) {
+ int is_inc = (c == ARITH_ADD) ^ (val < 0);
+ if (TCG_TARGET_REG_BITS == 64) {
+ /*
+ * The single-byte increment encodings are re-tasked
+ * as the REX prefixes. Use the MODRM encoding.
+ */
+ tcg_out_modrm(s, OPC_GRP5 + rexw,
+ (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
+ } else {
+ tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
+ }
+ return;
+ }
+ if (val == 128) {
+ /*
+ * Facilitate using an 8-bit immediate. Carry is inverted
+ * by this transformation, so do it only if cf == 0.
+ */
+ c ^= ARITH_ADD ^ ARITH_SUB;
+ val = -128;
+ }
}
- return;
- }
+ break;
- if (c == ARITH_AND) {
+ case ARITH_AND:
if (TCG_TARGET_REG_BITS == 64) {
if (val == 0xffffffffu) {
tcg_out_ext32u(s, r0, r0);
@@ -1351,6 +1369,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0,
tcg_out_ext16u(s, r0, r0);
return;
}
+ break;
}
if (val == (int8_t)val) {
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
2024-01-10 21:52 [PULL 0/4] tcg patch queue Richard Henderson
2024-01-10 21:52 ` [PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128 Richard Henderson
@ 2024-01-10 21:52 ` Richard Henderson
2024-01-10 21:52 ` [PULL 3/4] tcg/ppc: Use new registers for LQ destination Richard Henderson
` (2 subsequent siblings)
4 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-01-10 21:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini
From: Paolo Bonzini <pbonzini@redhat.com>
In the case where OR or XOR has an 8-bit immediate between 128 and 255,
we can operate on a low-byte register and shorten the output by two or
three bytes (two if a prefix byte is needed for REX.B).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231228120524.70239-1-pbonzini@redhat.com>
[rth: Incorporate into switch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 29e80af78b..d268199fc1 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -244,6 +244,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
#define P_VEXL 0x80000 /* Set VEX.L = 1 */
#define P_EVEX 0x100000 /* Requires EVEX encoding */
+#define OPC_ARITH_EbIb (0x80)
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
@@ -1370,6 +1371,16 @@ static void tgen_arithi(TCGContext *s, int c, int r0,
return;
}
break;
+
+ case ARITH_OR:
+ case ARITH_XOR:
+ if (val >= 0x80 && val <= 0xff
+ && (r0 < 4 || TCG_TARGET_REG_BITS == 64)) {
+ tcg_out_modrm(s, OPC_ARITH_EbIb + P_REXB_RM, c, r0);
+ tcg_out8(s, val);
+ return;
+ }
+ break;
}
if (val == (int8_t)val) {
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PULL 3/4] tcg/ppc: Use new registers for LQ destination
2024-01-10 21:52 [PULL 0/4] tcg patch queue Richard Henderson
2024-01-10 21:52 ` [PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128 Richard Henderson
2024-01-10 21:52 ` [PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates Richard Henderson
@ 2024-01-10 21:52 ` Richard Henderson
2024-01-10 21:52 ` [PULL 4/4] util: fix build with musl libc on ppc64le Richard Henderson
2024-01-11 15:16 ` [PULL 0/4] tcg patch queue Peter Maydell
4 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-01-10 21:52 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable, Philippe Mathieu-Daudé
LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.
This requires new support in process_op_defs and tcg_reg_alloc_op.
Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target-con-set.h | 2 +-
tcg/tcg.c | 21 ++++++++++++++++-----
tcg/ppc/tcg-target.c.inc | 3 ++-
3 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
index bbd7b21247..cb47b29452 100644
--- a/tcg/ppc/tcg-target-con-set.h
+++ b/tcg/ppc/tcg-target-con-set.h
@@ -35,7 +35,7 @@ C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, rZ, rZ)
C_O1_I4(r, r, r, ri, ri)
C_O2_I1(r, r, r)
-C_O2_I1(o, m, r)
+C_N1O1_I1(o, m, r)
C_O2_I2(r, r, r, r)
C_O2_I4(r, r, rI, rZM, r, r)
C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 896a36caeb..e2c38f6d11 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -653,6 +653,7 @@ static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1,
#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4),
#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2),
+#define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1),
#define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1),
#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1),
@@ -676,6 +677,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
#undef C_O1_I3
#undef C_O1_I4
#undef C_N1_I2
+#undef C_N1O1_I1
#undef C_N2_I1
#undef C_O2_I1
#undef C_O2_I2
@@ -696,6 +698,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode);
#define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } },
#define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } },
+#define C_N1O1_I1(O1, O2, I1) { .args_ct_str = { "&" #O1, #O2, #I1 } },
#define C_N2_I1(O1, O2, I1) { .args_ct_str = { "&" #O1, "&" #O2, #I1 } },
#define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } },
@@ -718,6 +721,7 @@ static const TCGTargetOpDef constraint_sets[] = {
#undef C_O1_I3
#undef C_O1_I4
#undef C_N1_I2
+#undef C_N1O1_I1
#undef C_N2_I1
#undef C_O2_I1
#undef C_O2_I2
@@ -738,6 +742,7 @@ static const TCGTargetOpDef constraint_sets[] = {
#define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
#define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2)
+#define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1)
#define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1)
#define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1)
@@ -2988,6 +2993,7 @@ static void process_op_defs(TCGContext *s)
.pair = 2,
.pair_index = o,
.regs = def->args_ct[o].regs << 1,
+ .newreg = def->args_ct[o].newreg,
};
def->args_ct[o].pair = 1;
def->args_ct[o].pair_index = i;
@@ -3004,6 +3010,7 @@ static void process_op_defs(TCGContext *s)
.pair = 1,
.pair_index = o,
.regs = def->args_ct[o].regs >> 1,
+ .newreg = def->args_ct[o].newreg,
};
def->args_ct[o].pair = 2;
def->args_ct[o].pair_index = i;
@@ -5036,17 +5043,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
break;
case 1: /* first of pair */
- tcg_debug_assert(!arg_ct->newreg);
if (arg_ct->oalias) {
reg = new_args[arg_ct->alias_index];
- break;
+ } else if (arg_ct->newreg) {
+ reg = tcg_reg_alloc_pair(s, arg_ct->regs,
+ i_allocated_regs | o_allocated_regs,
+ output_pref(op, k),
+ ts->indirect_base);
+ } else {
+ reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
+ output_pref(op, k),
+ ts->indirect_base);
}
- reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs,
- output_pref(op, k), ts->indirect_base);
break;
case 2: /* second of pair */
- tcg_debug_assert(!arg_ct->newreg);
if (arg_ct->oalias) {
reg = new_args[arg_ct->alias_index];
} else {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 856c3b18f5..54816967bc 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2595,6 +2595,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
tcg_debug_assert(!need_bswap);
tcg_debug_assert(datalo & 1);
tcg_debug_assert(datahi == datalo - 1);
+ tcg_debug_assert(!is_ld || datahi != index);
insn = is_ld ? LQ : STQ;
tcg_out32(s, insn | TAI(datahi, index, 0));
} else {
@@ -4071,7 +4072,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_qemu_ld_a32_i128:
case INDEX_op_qemu_ld_a64_i128:
- return C_O2_I1(o, m, r);
+ return C_N1O1_I1(o, m, r);
case INDEX_op_qemu_st_a32_i128:
case INDEX_op_qemu_st_a64_i128:
return C_O0_I3(o, m, r);
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PULL 4/4] util: fix build with musl libc on ppc64le
2024-01-10 21:52 [PULL 0/4] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2024-01-10 21:52 ` [PULL 3/4] tcg/ppc: Use new registers for LQ destination Richard Henderson
@ 2024-01-10 21:52 ` Richard Henderson
2024-01-11 15:16 ` [PULL 0/4] tcg patch queue Peter Maydell
4 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2024-01-10 21:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Natanael Copa, qemu-stable
From: Natanael Copa <ncopa@alpinelinux.org>
Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers
instead of the GNU specific PPC_FEATURE2_HAS_ISEL and
PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861
Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Fixes: 63922f467a ("tcg/ppc: Replace HAVE_ISEL macro with a variable")
Fixes: 68f340d4cd ("tcg/ppc: Enable Altivec detection")
Message-Id: <20231219105236.7059-1-ncopa@alpinelinux.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
util/cpuinfo-ppc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index 1ea3db0ac8..b2d8893a06 100644
--- a/util/cpuinfo-ppc.c
+++ b/util/cpuinfo-ppc.c
@@ -6,10 +6,10 @@
#include "qemu/osdep.h"
#include "host/cpuinfo.h"
+#include <asm/cputable.h>
#ifdef CONFIG_GETAUXVAL
# include <sys/auxv.h>
#else
-# include <asm/cputable.h>
# include "elf.h"
#endif
@@ -40,7 +40,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
info |= CPUINFO_V2_06;
}
- if (hwcap2 & PPC_FEATURE2_HAS_ISEL) {
+ if (hwcap2 & PPC_FEATURE2_ISEL) {
info |= CPUINFO_ISEL;
}
if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
@@ -53,7 +53,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void)
* always have both anyway, since VSX came with Power7
* and crypto came with Power8.
*/
- if (hwcap2 & PPC_FEATURE2_HAS_VEC_CRYPTO) {
+ if (hwcap2 & PPC_FEATURE2_VEC_CRYPTO) {
info |= CPUINFO_CRYPTO;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2024-01-10 21:52 [PULL 0/4] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2024-01-10 21:52 ` [PULL 4/4] util: fix build with musl libc on ppc64le Richard Henderson
@ 2024-01-11 15:16 ` Peter Maydell
4 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2024-01-11 15:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Wed, 10 Jan 2024 at 21:52, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 34eac35f893664eb8545b98142e23d9954722766:
>
> Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240111
>
> for you to fetch changes up to 1d513e06d96697f44de4a1b85c6ff627c443e306:
>
> util: fix build with musl libc on ppc64le (2024-01-11 08:48:16 +1100)
>
> ----------------------------------------------------------------
> tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
> tcg/ppc: Use new registers for LQ destination
> util: fix build with musl libc on ppc64le
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2023-08-29 17:02 Richard Henderson
@ 2023-08-29 18:27 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2023-08-29 18:27 UTC (permalink / raw)
To: qemu-devel
On 8/29/23 10:02, Richard Henderson wrote:
> The following changes since commit 813bac3d8d70d85cb7835f7945eb9eed84c2d8d0:
>
> Merge tag '2023q3-bsd-user-pull-request' of https://gitlab.com/bsdimp/qemu into staging (2023-08-29 08:58:00 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230829
>
> for you to fetch changes up to dad2f2f5afbaf58d6056f31dfd4b9edd0854b8ab:
>
> tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32 (2023-08-29 09:57:39 -0700)
>
> ----------------------------------------------------------------
> softmmu: Use async_run_on_cpu in tcg_commit
> tcg: Remove vecop_list check from tcg_gen_not_vec
> tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32
>
Disregard this PR. I will re-issue with the abi_ptr change reverted.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2023-08-29 17:02 Richard Henderson
2023-08-29 18:27 ` Richard Henderson
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2023-08-29 17:02 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 813bac3d8d70d85cb7835f7945eb9eed84c2d8d0:
Merge tag '2023q3-bsd-user-pull-request' of https://gitlab.com/bsdimp/qemu into staging (2023-08-29 08:58:00 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230829
for you to fetch changes up to dad2f2f5afbaf58d6056f31dfd4b9edd0854b8ab:
tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32 (2023-08-29 09:57:39 -0700)
----------------------------------------------------------------
softmmu: Use async_run_on_cpu in tcg_commit
tcg: Remove vecop_list check from tcg_gen_not_vec
tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32
----------------------------------------------------------------
Richard Henderson (4):
softmmu: Assert data in bounds in iotlb_to_section
softmmu: Use async_run_on_cpu in tcg_commit
tcg: Remove vecop_list check from tcg_gen_not_vec
tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32
include/exec/cpu-common.h | 1 -
tcg/sparc64/tcg-target.h | 2 +-
accel/tcg/cpu-exec-common.c | 30 --------------------------
softmmu/physmem.c | 50 ++++++++++++++++++++++++++++++++------------
tcg/tcg-op-vec.c | 7 +++----
tcg/sparc64/tcg-target.c.inc | 11 ----------
6 files changed, 41 insertions(+), 60 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2022-04-20 19:16 Richard Henderson
@ 2022-04-21 4:56 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2022-04-21 4:56 UTC (permalink / raw)
To: qemu-devel
On 4/20/22 12:16, Richard Henderson wrote:
> The following changes since commit 2d20a57453f6a206938cbbf77bed0b378c806c1f:
>
> Merge tag 'pull-fixes-for-7.1-200422-1' of https://github.com/stsquad/qemu into staging (2022-04-20 11:13:08 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220420
>
> for you to fetch changes up to a61532faa5a4d5e021e35b6a4a1e180c72d4a22f:
>
> tcg: Add tcg_constant_ptr (2022-04-20 12:12:47 -0700)
>
> ----------------------------------------------------------------
> Cleanup sysemu/tcg.h usage.
> Fix indirect lowering vs cond branches
> Remove ATOMIC_MMU_IDX
> Add tcg_constant_ptr
Applied, thanks. Please update the wiki changelog for 7.1 as appropriate.
r~
>
> ----------------------------------------------------------------
> Richard Henderson (3):
> tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH
> accel/tcg: Remove ATOMIC_MMU_IDX
> tcg: Add tcg_constant_ptr
>
> Thomas Huth (1):
> Don't include sysemu/tcg.h if it is not necessary
>
> include/tcg/tcg.h | 4 ++++
> accel/tcg/cputlb.c | 1 -
> accel/tcg/hmp.c | 1 -
> accel/tcg/tcg-accel-ops-icount.c | 1 -
> accel/tcg/user-exec.c | 1 -
> bsd-user/main.c | 1 -
> hw/virtio/vhost.c | 1 -
> linux-user/main.c | 1 -
> monitor/misc.c | 1 -
> target/arm/helper.c | 1 -
> target/s390x/cpu_models_sysemu.c | 1 -
> target/s390x/helper.c | 1 -
> tcg/tcg.c | 34 +++++++++++++++++++++++++++-------
> 13 files changed, 31 insertions(+), 18 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2022-04-20 19:16 Richard Henderson
2022-04-21 4:56 ` Richard Henderson
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2022-04-20 19:16 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 2d20a57453f6a206938cbbf77bed0b378c806c1f:
Merge tag 'pull-fixes-for-7.1-200422-1' of https://github.com/stsquad/qemu into staging (2022-04-20 11:13:08 -0700)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220420
for you to fetch changes up to a61532faa5a4d5e021e35b6a4a1e180c72d4a22f:
tcg: Add tcg_constant_ptr (2022-04-20 12:12:47 -0700)
----------------------------------------------------------------
Cleanup sysemu/tcg.h usage.
Fix indirect lowering vs cond branches
Remove ATOMIC_MMU_IDX
Add tcg_constant_ptr
----------------------------------------------------------------
Richard Henderson (3):
tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH
accel/tcg: Remove ATOMIC_MMU_IDX
tcg: Add tcg_constant_ptr
Thomas Huth (1):
Don't include sysemu/tcg.h if it is not necessary
include/tcg/tcg.h | 4 ++++
accel/tcg/cputlb.c | 1 -
accel/tcg/hmp.c | 1 -
accel/tcg/tcg-accel-ops-icount.c | 1 -
accel/tcg/user-exec.c | 1 -
bsd-user/main.c | 1 -
hw/virtio/vhost.c | 1 -
linux-user/main.c | 1 -
monitor/misc.c | 1 -
target/arm/helper.c | 1 -
target/s390x/cpu_models_sysemu.c | 1 -
target/s390x/helper.c | 1 -
tcg/tcg.c | 34 +++++++++++++++++++++++++++-------
13 files changed, 31 insertions(+), 18 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2022-03-14 17:36 Richard Henderson
@ 2022-03-15 9:53 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2022-03-15 9:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, 14 Mar 2022 at 17:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 15df33ceb73cb6bb3c6736cf4d2cff51129ed4b4:
>
> Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20220312-1' into staging (2022-03-13 17:29:18 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220314
>
> for you to fetch changes up to 76cff100beeae8d3676bb658cccd45ef5ced8aa9:
>
> tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 (2022-03-14 10:31:51 -0700)
>
> ----------------------------------------------------------------
> Fixes for s390x host vectors
> Fix for arm ldrd unpredictable case
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2022-03-14 17:36 Richard Henderson
2022-03-15 9:53 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2022-03-14 17:36 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 15df33ceb73cb6bb3c6736cf4d2cff51129ed4b4:
Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20220312-1' into staging (2022-03-13 17:29:18 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220314
for you to fetch changes up to 76cff100beeae8d3676bb658cccd45ef5ced8aa9:
tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 (2022-03-14 10:31:51 -0700)
----------------------------------------------------------------
Fixes for s390x host vectors
Fix for arm ldrd unpredictable case
----------------------------------------------------------------
Richard Henderson (4):
tcg/s390x: Fix tcg_out_dupi_vec vs VGM
tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
tcg/s390x: Fix tcg_out_dup_vec vs general registers
tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
tcg/arm/tcg-target.c.inc | 17 +++++++++++++++--
tcg/s390x/tcg-target.c.inc | 7 ++++---
2 files changed, 19 insertions(+), 5 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2022-01-05 0:40 Richard Henderson
@ 2022-01-05 2:53 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2022-01-05 2:53 UTC (permalink / raw)
To: qemu-devel
On 1/4/22 4:40 PM, Richard Henderson wrote:
> The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
>
> Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
>
> for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
>
> common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
>
> ----------------------------------------------------------------
> Fix for safe_syscall_base.
> Fix for folding of vector add/sub.
> Fix build on loongarch64 with gcc 8.
> Remove decl for qemu_run_machine_init_done_notifiers.
>
> ----------------------------------------------------------------
> Philippe Mathieu-Daudé (1):
> linux-user: Fix trivial build error on loongarch64 hosts
>
> Richard Henderson (2):
> tcg/optimize: Fix folding of vector ops
> common-user: Fix tail calls to safe_syscall_set_errno_tail
>
> Xiaoyao Li (1):
> sysemu: Cleanup qemu_run_machine_init_done_notifiers()
>
> include/sysemu/sysemu.h | 1 -
> linux-user/host/loongarch64/host-signal.h | 4 +--
> tcg/optimize.c | 49 +++++++++++++++++++++++-------
> common-user/host/i386/safe-syscall.inc.S | 1 +
> common-user/host/mips/safe-syscall.inc.S | 1 +
> common-user/host/x86_64/safe-syscall.inc.S | 1 +
> 6 files changed, 42 insertions(+), 15 deletions(-)
Applied.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2022-01-05 0:40 Richard Henderson
2022-01-05 2:53 ` Richard Henderson
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2022-01-05 0:40 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 67e41fe0cfb62e6cdfa659f0155417d17e5274ea:
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging (2022-01-04 07:23:27 -0800)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220104
for you to fetch changes up to d7478d4229f0a2b2817a55487e6b17081099fae4:
common-user: Fix tail calls to safe_syscall_set_errno_tail (2022-01-04 15:41:03 -0800)
----------------------------------------------------------------
Fix for safe_syscall_base.
Fix for folding of vector add/sub.
Fix build on loongarch64 with gcc 8.
Remove decl for qemu_run_machine_init_done_notifiers.
----------------------------------------------------------------
Philippe Mathieu-Daudé (1):
linux-user: Fix trivial build error on loongarch64 hosts
Richard Henderson (2):
tcg/optimize: Fix folding of vector ops
common-user: Fix tail calls to safe_syscall_set_errno_tail
Xiaoyao Li (1):
sysemu: Cleanup qemu_run_machine_init_done_notifiers()
include/sysemu/sysemu.h | 1 -
linux-user/host/loongarch64/host-signal.h | 4 +--
tcg/optimize.c | 49 +++++++++++++++++++++++-------
common-user/host/i386/safe-syscall.inc.S | 1 +
common-user/host/mips/safe-syscall.inc.S | 1 +
common-user/host/x86_64/safe-syscall.inc.S | 1 +
6 files changed, 42 insertions(+), 15 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2021-11-11 11:06 Richard Henderson
@ 2021-11-11 13:57 ` Richard Henderson
0 siblings, 0 replies; 21+ messages in thread
From: Richard Henderson @ 2021-11-11 13:57 UTC (permalink / raw)
To: qemu-devel
On 11/11/21 12:06 PM, Richard Henderson wrote:
> The following changes since commit 1b9fc6d8ba6667ceb56a3392e84656dcaed0d676:
>
> Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2021-11-11 09:56:22 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211111
>
> for you to fetch changes up to d58f01733b94845b0c2232018a2bedb6a2347ec5:
>
> tcg/s390x: Fix tcg_out_vec_op argument type (2021-11-11 11:47:58 +0100)
>
> ----------------------------------------------------------------
> appease coverity vs extract2
> update docs for ctpop opcodes
> tcg/s390x build fix for gcc11
>
> ----------------------------------------------------------------
> Miroslav Rezanina (1):
> tcg/s390x: Fix tcg_out_vec_op argument type
>
> Philippe Mathieu-Daudé (1):
> tcg: Remove TCI experimental status
>
> Richard Henderson (2):
> tcg/optimize: Add an extra cast to fold_extract2
> tcg: Document ctpop opcodes
>
> docs/about/build-platforms.rst | 10 ++++++----
> meson.build | 4 ++--
> tcg/optimize.c | 2 +-
> tcg/s390x/tcg-target.c.inc | 3 ++-
> meson_options.txt | 2 +-
> scripts/meson-buildoptions.sh | 3 +--
> tcg/README | 6 ++++++
> 7 files changed, 19 insertions(+), 11 deletions(-)
Applied, thanks.
r~
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2021-11-11 11:06 Richard Henderson
2021-11-11 13:57 ` Richard Henderson
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2021-11-11 11:06 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 1b9fc6d8ba6667ceb56a3392e84656dcaed0d676:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2021-11-11 09:56:22 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211111
for you to fetch changes up to d58f01733b94845b0c2232018a2bedb6a2347ec5:
tcg/s390x: Fix tcg_out_vec_op argument type (2021-11-11 11:47:58 +0100)
----------------------------------------------------------------
appease coverity vs extract2
update docs for ctpop opcodes
tcg/s390x build fix for gcc11
----------------------------------------------------------------
Miroslav Rezanina (1):
tcg/s390x: Fix tcg_out_vec_op argument type
Philippe Mathieu-Daudé (1):
tcg: Remove TCI experimental status
Richard Henderson (2):
tcg/optimize: Add an extra cast to fold_extract2
tcg: Document ctpop opcodes
docs/about/build-platforms.rst | 10 ++++++----
meson.build | 4 ++--
tcg/optimize.c | 2 +-
tcg/s390x/tcg-target.c.inc | 3 ++-
meson_options.txt | 2 +-
scripts/meson-buildoptions.sh | 3 +--
tcg/README | 6 ++++++
7 files changed, 19 insertions(+), 11 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2021-05-14 11:03 ` Peter Maydell
@ 2021-05-14 14:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-14 14:39 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson; +Cc: QEMU Developers
On 5/14/21 1:03 PM, Peter Maydell wrote:
> On Thu, 13 May 2021 at 13:20, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> The following changes since commit 3e9f48bcdabe57f8f90cf19f01bbbf3c86937267:
>>
>> Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging (2021-05-12 17:31:52 +0100)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210513
>>
>> for you to fetch changes up to 9bcf4c52f801966b10f802e65c3ecc8bbbd8c660:
>>
>> tcg: Add tcg_constant_tl (2021-05-13 05:42:44 -0500)
>>
>> ----------------------------------------------------------------
>> Minor gen-icount.h fix.
>> BSD cpu_signal_handler fix.
>> Add missing tcg_constant_tl symbol.
>>
>
> Fails to build on FreeBSD and OpenBSD:
>
>
> ../src/accel/tcg/user-exec.c:358:46: error: use of undeclared
> identifier 'T_PAGEFLT'
> TRAP_sig(uc) == PAGE_FAULT_TRAP ?
> ^
> ../src/accel/tcg/user-exec.c:334:31: note: expanded from macro 'PAGE_FAULT_TRAP'
> #define PAGE_FAULT_TRAP T_PAGEFLT
Good excuse to highlight my "gitlab-ci: Allow using FreeBSD runners"
series :)
https://www.mail-archive.com/qemu-devel@nongnu.org/msg806537.html
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2021-05-13 12:20 Richard Henderson
@ 2021-05-14 11:03 ` Peter Maydell
2021-05-14 14:39 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 21+ messages in thread
From: Peter Maydell @ 2021-05-14 11:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 13 May 2021 at 13:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 3e9f48bcdabe57f8f90cf19f01bbbf3c86937267:
>
> Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging (2021-05-12 17:31:52 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210513
>
> for you to fetch changes up to 9bcf4c52f801966b10f802e65c3ecc8bbbd8c660:
>
> tcg: Add tcg_constant_tl (2021-05-13 05:42:44 -0500)
>
> ----------------------------------------------------------------
> Minor gen-icount.h fix.
> BSD cpu_signal_handler fix.
> Add missing tcg_constant_tl symbol.
>
Fails to build on FreeBSD and OpenBSD:
../src/accel/tcg/user-exec.c:358:46: error: use of undeclared
identifier 'T_PAGEFLT'
TRAP_sig(uc) == PAGE_FAULT_TRAP ?
^
../src/accel/tcg/user-exec.c:334:31: note: expanded from macro 'PAGE_FAULT_TRAP'
#define PAGE_FAULT_TRAP T_PAGEFLT
^
thanks
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2021-05-13 12:20 Richard Henderson
2021-05-14 11:03 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2021-05-13 12:20 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 3e9f48bcdabe57f8f90cf19f01bbbf3c86937267:
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511' into staging (2021-05-12 17:31:52 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210513
for you to fetch changes up to 9bcf4c52f801966b10f802e65c3ecc8bbbd8c660:
tcg: Add tcg_constant_tl (2021-05-13 05:42:44 -0500)
----------------------------------------------------------------
Minor gen-icount.h fix.
BSD cpu_signal_handler fix.
Add missing tcg_constant_tl symbol.
----------------------------------------------------------------
Matheus Ferst (1):
tcg: Add tcg_constant_tl
Philippe Mathieu-Daudé (2):
MAINTAINERS: Add include/exec/gen-icount.h to 'Main Loop' section
exec/gen-icount.h: Add missing "exec/exec-all.h" include
Warner Losh (1):
tcg: Use correct trap number for page faults on *BSD systems
include/exec/gen-icount.h | 1 +
include/tcg/tcg-op.h | 2 ++
accel/tcg/user-exec.c | 14 ++++++++++++--
MAINTAINERS | 1 +
4 files changed, 16 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PULL 0/4] tcg patch queue
2019-11-11 15:55 Richard Henderson
@ 2019-11-11 17:36 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-11-11 17:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Mon, 11 Nov 2019 at 15:56, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 654efcb511d394c1d3f5292c28503d1d19e5b1d3:
>
> Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging (2019-11-11 09:23:46 +0000)
>
> are available in the Git repository at:
>
> https://github.com/rth7680/qemu.git tags/pull-tcg-20191111
>
> for you to fetch changes up to cb974c95df0e1c9e73a37facd3e13894bd3eedc2:
>
> tcg/LICENSE: Remove out of date claim about TCG subdirectory licensing (2019-11-11 15:11:21 +0100)
>
> ----------------------------------------------------------------
> Remove no-longer-true statement that TCG is BSD-licensed
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PULL 0/4] tcg patch queue
@ 2019-11-11 15:55 Richard Henderson
2019-11-11 17:36 ` Peter Maydell
0 siblings, 1 reply; 21+ messages in thread
From: Richard Henderson @ 2019-11-11 15:55 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 654efcb511d394c1d3f5292c28503d1d19e5b1d3:
Merge remote-tracking branch 'remotes/vivier/tags/q800-branch-pull-request' into staging (2019-11-11 09:23:46 +0000)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-20191111
for you to fetch changes up to cb974c95df0e1c9e73a37facd3e13894bd3eedc2:
tcg/LICENSE: Remove out of date claim about TCG subdirectory licensing (2019-11-11 15:11:21 +0100)
----------------------------------------------------------------
Remove no-longer-true statement that TCG is BSD-licensed
----------------------------------------------------------------
Peter Maydell (4):
tcg/aarch64/tcg-target.opc.h: Add copyright/license
tcg/i386/tcg-target.opc.h: Add copyright/license
tcg/ppc/tcg-target.opc.h: Add copyright/license
tcg/LICENSE: Remove out of date claim about TCG subdirectory licensing
tcg/aarch64/tcg-target.opc.h | 15 ++++++++++++---
tcg/i386/tcg-target.opc.h | 28 +++++++++++++++++++++++++---
tcg/ppc/tcg-target.opc.h | 20 ++++++++++++++++++++
LICENSE | 5 +++--
tcg/LICENSE | 3 ---
5 files changed, 60 insertions(+), 11 deletions(-)
delete mode 100644 tcg/LICENSE
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2024-01-11 15:18 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-10 21:52 [PULL 0/4] tcg patch queue Richard Henderson
2024-01-10 21:52 ` [PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128 Richard Henderson
2024-01-10 21:52 ` [PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates Richard Henderson
2024-01-10 21:52 ` [PULL 3/4] tcg/ppc: Use new registers for LQ destination Richard Henderson
2024-01-10 21:52 ` [PULL 4/4] util: fix build with musl libc on ppc64le Richard Henderson
2024-01-11 15:16 ` [PULL 0/4] tcg patch queue Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2023-08-29 17:02 Richard Henderson
2023-08-29 18:27 ` Richard Henderson
2022-04-20 19:16 Richard Henderson
2022-04-21 4:56 ` Richard Henderson
2022-03-14 17:36 Richard Henderson
2022-03-15 9:53 ` Peter Maydell
2022-01-05 0:40 Richard Henderson
2022-01-05 2:53 ` Richard Henderson
2021-11-11 11:06 Richard Henderson
2021-11-11 13:57 ` Richard Henderson
2021-05-13 12:20 Richard Henderson
2021-05-14 11:03 ` Peter Maydell
2021-05-14 14:39 ` Philippe Mathieu-Daudé
2019-11-11 15:55 Richard Henderson
2019-11-11 17:36 ` Peter Maydell
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