From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/12] riscv-to-apply queue
Date: Mon, 18 Jan 2021 12:03:39 +0000 [thread overview]
Message-ID: <CAFEAcA8joExf3krBSXEacPOUbwgQNRPHnJFAVFdBrfkmapWS_w@mail.gmail.com> (raw)
In-Reply-To: <20210117215403.2277103-1-alistair.francis@wdc.com>
On Sun, 17 Jan 2021 at 21:54, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 825a215c003cd028e26c7d19aa5049d957345f43:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/audio-20210115-pull-request' into staging (2021-01-15 22:21:21 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210117-3
>
> for you to fetch changes up to a8259b53230782f5e0a0d66013655c4ed5d71b7e:
>
> riscv: Pass RISCVHartArrayState by pointer (2021-01-16 14:34:46 -0800)
>
> ----------------------------------------------------------------
> First RISC-V PR for 6.0
>
> This PR:
> - Fixes some issues with the m25p80
> - Improves GDB support for RISC-V
> - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
> - Enforces PMP exceptions correctly
> - Fixes some Coverity issues
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
next prev parent reply other threads:[~2021-01-18 12:06 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-17 21:53 [PULL 00/12] riscv-to-apply queue Alistair Francis
2021-01-17 21:53 ` [PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled Alistair Francis
2021-01-17 21:53 ` [PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes Alistair Francis
2021-01-17 21:53 ` [PULL 03/12] gdb: riscv: Add target description Alistair Francis
2021-01-17 21:53 ` [PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB Alistair Francis
2021-01-17 21:53 ` [PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured Alistair Francis
2021-01-17 21:53 ` [PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type Alistair Francis
2021-01-17 21:53 ` [PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite Alistair Francis
2021-01-17 21:53 ` [PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external Alistair Francis
2021-01-17 21:54 ` [PULL 09/12] target/riscv: Add CSR name in the CSR function table Alistair Francis
2021-01-17 21:54 ` [PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically Alistair Francis
2021-01-17 21:54 ` [PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs Alistair Francis
2021-01-17 21:54 ` [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer Alistair Francis
2021-01-18 12:03 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-09-23 4:06 [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-26 19:28 ` Stefan Hajnoczi
2022-09-26 20:59 ` Alistair Francis
2022-09-26 21:04 ` Stefan Hajnoczi
2020-10-23 15:16 Alistair Francis
2020-10-26 13:16 ` Peter Maydell
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