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From: Stefan Hajnoczi <stefanha@gmail.com>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: qemu-devel@nongnu.org, alistair23@gmail.com,
	 Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/12] riscv-to-apply queue
Date: Mon, 26 Sep 2022 15:28:52 -0400	[thread overview]
Message-ID: <CAJSP0QWi_xpNynSKsxH5gdK8gqt1jOjZqEsJ=eiJkypVShuc4g@mail.gmail.com> (raw)
In-Reply-To: <20220923040704.428285-1-alistair.francis@opensource.wdc.com>

On Fri, 23 Sept 2022 at 00:08, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2

Hi Alistair,
Please use the HTTPS GitHub repo URL in pull requests. Setting
separate "url" (HTTPS) and "pushUrl" (ssh) settings for your remote in
git-config(1) should solve this problem.

Stefan


  parent reply	other threads:[~2022-09-26 19:31 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23  4:06 [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-23  4:06 ` [PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-23  4:06 ` [PULL 02/12] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-23  4:06 ` [PULL 03/12] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-23  4:06 ` [PULL 04/12] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-23  4:06 ` [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-23  4:06 ` [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-23  4:06 ` [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-23  4:07 ` [PULL 08/12] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-23  4:07 ` [PULL 09/12] hw/riscv: opentitan: Fixup resetvec Alistair Francis
2022-09-23  4:07 ` [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-23  4:07 ` [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-23  4:07 ` [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-26 19:28 ` Stefan Hajnoczi [this message]
2022-09-26 20:59   ` [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-26 21:04     ` Stefan Hajnoczi
  -- strict thread matches above, loose matches on Subject: below --
2021-01-17 21:53 Alistair Francis
2021-01-18 12:03 ` Peter Maydell
2020-10-23 15:16 Alistair Francis
2020-10-26 13:16 ` Peter Maydell

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