From: Alistair Francis <alistair23@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use
Date: Wed, 7 Apr 2021 09:55:37 -0400 [thread overview]
Message-ID: <CAKmqyKNDVPzteeWyeb+mnNaxfH9R9Ej12xY-wo7uO26oqiDcEg@mail.gmail.com> (raw)
In-Reply-To: <cover.1617290165.git.alistair.francis@wdc.com>
On Thu, Apr 1, 2021 at 11:19 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> V2:
> - Renmae the enum
> - Rebase on master
> - Fix a few incorrect returns
>
> Alistair Francis (5):
> target/riscv: Convert the RISC-V exceptions to an enum
> target/riscv: Use the RISCVException enum for CSR predicates
> target/riscv: Fix 32-bit HS mode access permissions
> target/riscv: Use the RISCVException enum for CSR operations
> target/riscv: Use RISCVException enum for CSR access
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 28 +-
> target/riscv/cpu_bits.h | 44 +--
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 4 +-
> target/riscv/csr.c | 740 ++++++++++++++++++++++----------------
> target/riscv/gdbstub.c | 8 +-
> target/riscv/op_helper.c | 18 +-
> 7 files changed, 492 insertions(+), 352 deletions(-)
>
> --
> 2.31.0
>
prev parent reply other threads:[~2021-04-07 14:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 15:17 [PATCH v2 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis
2021-04-01 15:17 ` [PATCH v2 1/5] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-04-02 17:11 ` Richard Henderson
2021-04-01 15:17 ` [PATCH v2 2/5] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-04-02 17:14 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-01 15:17 ` [PATCH v2 3/5] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-04-02 17:14 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-01 15:17 ` [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-04-02 17:17 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-01 15:18 ` [PATCH v2 5/5] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-04-02 17:18 ` Richard Henderson
2021-04-06 8:34 ` Bin Meng
2021-04-07 13:55 ` Alistair Francis [this message]
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