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From: Alistair Francis <alistair23@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@sifive.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong
Date: Fri, 23 Aug 2019 08:18:59 -0700
Message-ID: <CAKmqyKOaoUBQ5PsOuDB4AZ=XK+p13LVHEn-GGt9+k-LS_MirvA@mail.gmail.com> (raw)
In-Reply-To: <7e476df36a8c2ba53162e9a5f62e9fa171da00ad.1565904855.git.alistair.francis@wdc.com>

On Thu, Aug 15, 2019 at 2:38 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The mip register is an MXLEN-bit long register. Convert it to a
> target_ulong type instead of uint32_t.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

MIP is 32-bit to allow atomic access on 32-bit hosts, so I am going to
send a v4 with this patch dropped.

Alistair

> ---
>  target/riscv/cpu.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 2dc9b17678..0a7985c3f7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -130,7 +130,7 @@ struct CPURISCVState {
>       * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
>       * mip is 32-bits to allow atomic_read on 32-bit hosts.
>       */
> -    uint32_t mip;
> +    target_ulong mip;
>      uint32_t miclaim;
>
>      target_ulong mie;
> --
> 2.22.0
>


  parent reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-15 21:34 [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2 Alistair Francis
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:34 ` [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:35 ` [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-15 21:35 ` [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong Alistair Francis
2019-08-16 13:59   ` Bin Meng
2019-08-23 15:18   ` Alistair Francis [this message]
2019-08-15 22:13 ` [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2 no-reply

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