From: Alistair Francis <alistair23@gmail.com> To: Vijai Kumar K <vijai@behindbytes.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M Date: Fri, 2 Apr 2021 16:05:25 -0400 [thread overview] Message-ID: <CAKmqyKPAXLHPi_anf_Xbe6=9j-nkBP-b6QRqC4xDUT3u-7riUA@mail.gmail.com> (raw) In-Reply-To: <20210401181457.73039-1-vijai@behindbytes.com> On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K <vijai@behindbytes.com> wrote: > > Changes in v3: > - Drop SHAKTI_C_DEBUG register > > Changes in v2: > - Moved CPU addition to a separate patch(P1) > - Use riscv_setup_rom_resetvec API to setup reset vector > - Dropped unused DPRINTF and unwanted break statements > - Fixed uart_can_receive logic > - Reused sifive_u_cpu_init routine for shakti > - Error out when an unsupported CPU is specified > - Addressed formatting changes pointed out in review Thanks, I have reviewed these patches and applied them. Can you add details to the docs on how to build images and run this machine? This is an example for a different board: https://gitlab.com/qemu-project/qemu/-/blob/master/docs/system/riscv/microchip-icicle-kit.rst That way others can use this machine and I can generate tests for it. Alistair > > Vijai Kumar K (4): > target/riscv: Add Shakti C class CPU > riscv: Add initial support for Shakti C machine > hw/char: Add Shakti UART emulation > hw/riscv: Connect Shakti UART to Shakti platform > > MAINTAINERS | 9 + > default-configs/devices/riscv64-softmmu.mak | 1 + > hw/char/meson.build | 1 + > hw/char/shakti_uart.c | 185 ++++++++++++++++++++ > hw/char/trace-events | 4 + > hw/riscv/Kconfig | 10 ++ > hw/riscv/meson.build | 1 + > hw/riscv/shakti_c.c | 178 +++++++++++++++++++ > include/hw/char/shakti_uart.h | 74 ++++++++ > include/hw/riscv/shakti_c.h | 75 ++++++++ > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > 12 files changed, 540 insertions(+) > create mode 100644 hw/char/shakti_uart.c > create mode 100644 hw/riscv/shakti_c.c > create mode 100644 include/hw/char/shakti_uart.h > create mode 100644 include/hw/riscv/shakti_c.h > > -- > 2.25.1 > >
next prev parent reply other threads:[~2021-04-02 20:12 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-01 18:14 Vijai Kumar K 2021-04-01 18:14 ` [PATCH v3 1/4] target/riscv: Add Shakti C class CPU Vijai Kumar K 2021-04-02 13:04 ` Alistair Francis 2021-04-01 18:14 ` [PATCH v3 2/4] riscv: Add initial support for Shakti C machine Vijai Kumar K 2021-04-02 13:03 ` Alistair Francis 2021-04-01 18:14 ` [PATCH v3 3/4] hw/char: Add Shakti UART emulation Vijai Kumar K 2021-04-02 16:12 ` Alistair Francis 2021-04-01 18:14 ` [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform Vijai Kumar K 2021-04-02 13:05 ` Alistair Francis 2021-04-02 15:41 ` Vijai Kumar K 2021-04-02 20:05 ` Alistair Francis [this message] 2021-04-04 11:43 ` [PATCH v3 0/4] Add support for Shakti SoC from IIT-M Vijai Kumar K
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