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* [PATCH v5 00/17] support subsets of bitmanip extension
@ 2021-04-21  4:13 frank.chang
  2021-04-21  4:13 ` [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang
                   ` (16 more replies)
  0 siblings, 17 replies; 25+ messages in thread
From: frank.chang @ 2021-04-21  4:13 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv; +Cc: Frank Chang

From: Frank Chang <frank.chang@sifive.com>

This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
Zbs subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zba-, Zbb- and Zbs-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).

Specification:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf

The port is available here:
https://github.com/sifive/qemu/tree/rvb-upstream-v5

To test rvb implementation, specify cpu argument with 'x-b=true' or
'x-b=true,bext_spec=v0.93'to enable B-extension support.

Changelog:

v5:
 * add bext_spec cpu option, default set to v0.93.
 * rebase master branch.

v4:
 * Remove 'rd != 0' checks from immediate shift instructions.

v3:
 * Convert existing immediate shift instructions to use gen_shifti()
   and gen_shiftiw() interfaces.
 * Rename *u.w instructions to *.uw.
 * Rename sb* instructions to b*.
 * Rename pcnt* instructions to cpop*.

v2:
 * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
 * Remove addwu, subwu and addiwu instructions as they are not longer
   exist in latest draft.
 * Optimize implementation with cleaner tcg ops.

Frank Chang (5):
  target/riscv: rvb: count bits set
  target/riscv: add gen_shifti() and gen_shiftiw() helper functions
  target/riscv: rvb: generalized reverse
  target/riscv: rvb: generalized or-combine
  target/riscv: rvb: add b-ext version cpu option

Kito Cheng (12):
  target/riscv: reformat @sh format encoding for B-extension
  target/riscv: rvb: count leading/trailing zeros
  target/riscv: rvb: logic-with-negate
  target/riscv: rvb: pack two words into one register
  target/riscv: rvb: min/max instructions
  target/riscv: rvb: sign-extend instructions
  target/riscv: rvb: single-bit instructions
  target/riscv: rvb: shift ones
  target/riscv: rvb: rotate (left/right)
  target/riscv: rvb: address calculation
  target/riscv: rvb: add/shift with prefix zero-extend
  target/riscv: rvb: support and turn on B-extension from command line

 target/riscv/bitmanip_helper.c          | 102 ++++++
 target/riscv/cpu.c                      |  27 ++
 target/riscv/cpu.h                      |   5 +
 target/riscv/helper.h                   |   9 +
 target/riscv/insn32-64.decode           |  33 ++
 target/riscv/insn32.decode              |  54 ++-
 target/riscv/insn_trans/trans_rvb.c.inc | 417 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc |  54 +--
 target/riscv/meson.build                |   1 +
 target/riscv/translate.c                | 314 ++++++++++++++++++
 10 files changed, 960 insertions(+), 56 deletions(-)
 create mode 100644 target/riscv/bitmanip_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

--
2.17.1



^ permalink raw reply	[flat|nested] 25+ messages in thread

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Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-21  4:13 [PATCH v5 00/17] support subsets of bitmanip extension frank.chang
2021-04-21  4:13 ` [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-04-21  4:13 ` [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-04-27  6:01   ` Alistair Francis
2021-04-27  7:13     ` Frank Chang
2021-04-21  4:13 ` [PATCH v5 03/17] target/riscv: rvb: count bits set frank.chang
2021-04-27  6:03   ` Alistair Francis
2021-04-21  4:13 ` [PATCH v5 04/17] target/riscv: rvb: logic-with-negate frank.chang
2021-04-27  6:04   ` Alistair Francis
2021-04-21  4:13 ` [PATCH v5 05/17] target/riscv: rvb: pack two words into one register frank.chang
2021-04-27  6:05   ` Alistair Francis
2021-04-21  4:13 ` [PATCH v5 06/17] target/riscv: rvb: min/max instructions frank.chang
2021-04-27  6:06   ` Alistair Francis
2021-04-21  4:13 ` [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions frank.chang
2021-04-27  6:06   ` Alistair Francis
2021-04-21  4:13 ` [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-04-21  4:13 ` [PATCH v5 09/17] target/riscv: rvb: single-bit instructions frank.chang
2021-04-21  4:13 ` [PATCH v5 10/17] target/riscv: rvb: shift ones frank.chang
2021-04-21  4:13 ` [PATCH v5 11/17] target/riscv: rvb: rotate (left/right) frank.chang
2021-04-21  4:13 ` [PATCH v5 12/17] target/riscv: rvb: generalized reverse frank.chang
2021-04-21  4:13 ` [PATCH v5 13/17] target/riscv: rvb: generalized or-combine frank.chang
2021-04-21  4:13 ` [PATCH v5 14/17] target/riscv: rvb: address calculation frank.chang
2021-04-21  4:13 ` [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-04-21  4:13 ` [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-04-21  4:13 ` [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang

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