From: Sowjanya Komatineni <skomatineni@nvidia.com> To: thierry.reding@gmail.com, jonathanh@nvidia.com, talho@nvidia.com, skomatineni@nvidia.com, broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, kyarlagadda@nvidia.com Cc: ldewangan@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH V3 2/9] spi: expand mode support Date: Mon, 15 Apr 2019 14:30:27 -0700 [thread overview] Message-ID: <1555363834-32155-3-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> This patch changes mode and mode_bits from u16 to u32 to allow more mode configurations. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- include/linux/spi/spi.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 589f9dc9ac2b..053abd22ad31 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -143,7 +143,7 @@ struct spi_device { u32 max_speed_hz; u8 chip_select; u8 bits_per_word; - u16 mode; + u32 mode; #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ #define SPI_MODE_0 (0|0) /* (original MicroWire) */ @@ -443,7 +443,7 @@ struct spi_controller { u16 dma_alignment; /* spi_device.mode flags understood by this controller driver */ - u16 mode_bits; + u32 mode_bits; /* bitmask of supported bits_per_word for transfers */ u32 bits_per_word_mask; @@ -1291,7 +1291,7 @@ struct spi_board_info { /* mode becomes spi_device.mode, and is essential for chips * where the default of SPI_CS_HIGH = 0 is wrong. */ - u16 mode; + u32 mode; /* ... may need additional spi_device chip config data here. * avoid stuff protocol drivers can set; but include stuff -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <broonie@kernel.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <kyarlagadda@nvidia.com> Cc: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V3 2/9] spi: expand mode support Date: Mon, 15 Apr 2019 14:30:27 -0700 [thread overview] Message-ID: <1555363834-32155-3-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> This patch changes mode and mode_bits from u16 to u32 to allow more mode configurations. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- include/linux/spi/spi.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 589f9dc9ac2b..053abd22ad31 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -143,7 +143,7 @@ struct spi_device { u32 max_speed_hz; u8 chip_select; u8 bits_per_word; - u16 mode; + u32 mode; #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ #define SPI_MODE_0 (0|0) /* (original MicroWire) */ @@ -443,7 +443,7 @@ struct spi_controller { u16 dma_alignment; /* spi_device.mode flags understood by this controller driver */ - u16 mode_bits; + u32 mode_bits; /* bitmask of supported bits_per_word for transfers */ u32 bits_per_word_mask; @@ -1291,7 +1291,7 @@ struct spi_board_info { /* mode becomes spi_device.mode, and is essential for chips * where the default of SPI_CS_HIGH = 0 is wrong. */ - u16 mode; + u32 mode; /* ... may need additional spi_device chip config data here. * avoid stuff protocol drivers can set; but include stuff -- 2.7.4
next prev parent reply other threads:[~2019-04-15 21:30 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-15 21:30 [PATCH V3 0/9] bug fixes and more features to Tegra SPI Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 1/9] spi: tegra114: fix PIO transfer Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-16 16:32 ` Applied "spi: tegra114: fix PIO transfer" to the spi tree Mark Brown 2019-04-16 16:32 ` Mark Brown 2019-04-16 16:32 ` Mark Brown 2019-04-16 16:32 ` Mark Brown 2019-04-29 21:42 ` Sowjanya Komatineni 2019-05-02 2:42 ` Mark Brown 2019-04-15 21:30 ` Sowjanya Komatineni [this message] 2019-04-15 21:30 ` [PATCH V3 2/9] spi: expand mode support Sowjanya Komatineni 2019-04-18 10:26 ` Applied "spi: expand mode support" to the spi tree Mark Brown 2019-04-18 10:26 ` Mark Brown 2019-04-18 10:26 ` Mark Brown 2019-04-18 10:26 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-05-02 2:19 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 3/9] spi: add SPI_LSBYTE_FIRST mode Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-19 15:22 ` Mark Brown 2019-04-27 0:32 ` Sowjanya Komatineni 2019-05-06 4:49 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 4/9] spi: tegra114: add support for Tegra SPI LSBYTE_FIRST Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 5/9] spi: export spi core function spi_set_cs Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-19 15:18 ` Mark Brown 2019-04-29 22:02 ` Sowjanya Komatineni 2019-05-06 4:44 ` Mark Brown 2019-05-10 18:53 ` Sowjanya Komatineni 2019-05-12 3:12 ` Mark Brown 2019-04-15 21:30 ` [PATCH V3 6/9] spi: tegra114: add support for gpio based CS Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 7/9] spi: tegra114: add support for hw based cs Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 8/9] spi: tegra114: add support for HW CS timing Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni 2019-04-15 21:30 ` [PATCH V3 9/9] spi: tegra114: add support for TX and RX trimmers Sowjanya Komatineni 2019-04-15 21:30 ` Sowjanya Komatineni
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