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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [CI v12 20/23] i915/dp/fec: Add fec_enable to the crtc state.
Date: Tue, 27 Nov 2018 13:41:22 -0800	[thread overview]
Message-ID: <20181127214125.17658-20-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181127214125.17658-1-manasi.d.navare@intel.com>

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.

Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.

v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)

- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)

v3: Check for FEC support along with setting crtc state.

v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)

v5: Move fec check to intel_dp_supports_dsc(Ville)

v6: Remove warning. rebase.

v7: change crtc state to include DP sink and fec capability
of source.(Manasi)

v8: Set fec_enable in crtc in intel_dp_compute_config().

v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly

v10 (From Manasi):
* Rebase

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 27 ++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b7b2484696a4..afee9c76a341 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 			dsc_slice_count =
 				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 								true);
-		} else {
+		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 			dsc_max_output_bpp =
 				intel_dp_dsc_get_output_bpp(max_link_clock,
 							    max_lanes,
@@ -1710,14 +1710,25 @@ struct link_config_limits {
 	int min_bpp, max_bpp;
 };
 
-static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 					 const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	/* FIXME: FEC needed for external DP until then reject DSC on DP */
-	if (!intel_dp_is_edp(intel_dp))
-		return false;
+	return INTEL_GEN(dev_priv) >= 11 && pipe_config->cpu_transcoder != TRANSCODER_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *pipe_config)
+{
+	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
+		drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
+static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
+					 const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	return INTEL_GEN(dev_priv) >= 10 &&
 		pipe_config->cpu_transcoder != TRANSCODER_A;
@@ -1726,6 +1737,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *pipe_config)
 {
+	if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+		return false;
+
 	return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
 		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 }
@@ -2129,6 +2143,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return false;
 
+	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+				  intel_dp_supports_fec(intel_dp, pipe_config);
+
 	if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b5693cac26d7..8c582d53c00a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -946,6 +946,9 @@ struct intel_crtc_state {
 		u8 slice_count;
 	} dsc_params;
 	struct drm_dsc_config dp_dsc_cfg;
+
+	/* Forward Error correction State */
+	bool fec_enable;
 };
 
 struct intel_crtc {
-- 
2.19.1

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  parent reply	other threads:[~2018-11-27 21:38 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-27 21:41 [CI v12 01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 02/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-27 21:41 ` [CI v12 03/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-27 21:41 ` [CI v12 04/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-27 21:41 ` [CI v12 05/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-28  0:04   ` Srivatsa, Anusha
2018-11-27 21:41 ` [CI v12 06/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-27 21:41 ` [CI v12 07/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-27 21:41 ` [CI v12 08/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-27 21:41 ` [CI v12 09/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-27 21:41 ` [CI v12 10/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-27 21:41 ` [CI v12 11/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-27 21:41 ` [CI v12 12/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-27 21:41 ` [CI v12 13/23] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-27 21:41 ` [CI v12 14/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-27 21:41 ` [CI v12 15/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-27 21:41 ` [CI v12 16/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-27 21:41 ` [CI v12 17/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-27 21:41 ` [CI v12 18/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-27 21:41 ` [CI v12 19/23] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-27 21:41 ` Manasi Navare [this message]
2018-11-27 21:41 ` [CI v12 21/23] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION Manasi Navare
2018-11-27 21:41 ` [CI v12 22/23] i915/dp/fec: Configure the Forward Error Correction bits Manasi Navare
2018-11-27 21:41 ` [CI v12 23/23] drm/i915/fec: Disable FEC state Manasi Navare
2018-11-27 22:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to return complete DSC color depth capabilities Patchwork
2018-11-27 22:59 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-27 23:25 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-28 11:44 ` ✓ Fi.CI.IGT: " Patchwork

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