From: Like Xu <like.xu@linux.intel.com> To: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org>, Sean Christopherson <sean.j.christopherson@intel.com>, Vitaly Kuznetsov <vkuznets@redhat.com>, Wanpeng Li <wanpengli@tencent.com>, Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>, ak@linux.intel.com, wei.w.wang@intel.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu <like.xu@linux.intel.com>, Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com>, "Michael S. Tsirkin" <mst@redhat.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, Marcelo Tosatti <mtosatti@redhat.com>, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 2/2] target/i386: add -cpu,lbr=true support to enable guest LBR Date: Sat, 13 Jun 2020 16:09:58 +0800 [thread overview] Message-ID: <20200613080958.132489-14-like.xu@linux.intel.com> (raw) In-Reply-To: <20200613080958.132489-1-like.xu@linux.intel.com> The LBR feature would be enabled on the guest if: - the KVM is enabled and the PMU is enabled and, - the msr-based-feature IA32_PERF_CAPABILITIES is supporterd and, - the supported returned value for lbr_fmt from this msr is not zero. The LBR feature would be disabled on the guest if: - the msr-based-feature IA32_PERF_CAPABILITIES is unsupporterd OR, - qemu set the IA32_PERF_CAPABILITIES msr feature without lbr_fmt values OR, - the requested guest vcpu model doesn't support PDCM. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: qemu-devel@nongnu.org Signed-off-by: Like Xu <like.xu@linux.intel.com> --- hw/i386/pc.c | 1 + target/i386/cpu.c | 25 +++++++++++++++++++++++-- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 7 ++++++- 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2128f3d6fe..8d8d42a8ea 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -316,6 +316,7 @@ GlobalProperty pc_compat_1_5[] = { { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, { "virtio-net-pci", "any_layout", "off" }, { TYPE_X86_CPU, "pmu", "on" }, + { TYPE_X86_CPU, "lbr", "on" }, { "i440FX-pcihost", "short_root_bus", "0" }, { "q35-pcihost", "short_root_bus", "0" }, }; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e47c9d1604..262a2595fa 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1142,8 +1142,8 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_PERF_CAPABILITIES] = { .type = MSR_FEATURE_WORD, .feat_names = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + "lbr-fmt-bit-0", "lbr-fmt-bit-1", "lbr-fmt-bit-2", "lbr-fmt-bit-3", + "lbr-fmt-bit-4", "lbr-fmt-bit-5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "full-width-write", NULL, NULL, NULL, NULL, NULL, NULL, @@ -4187,6 +4187,13 @@ static bool lmce_supported(void) return !!(mce_cap & MCG_LMCE_P); } +static inline bool lbr_supported(void) +{ + return kvm_enabled() && (PERF_CAP_LBR_FMT & + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_PERF_CAPABILITIES)); +} + #define CPUID_MODEL_ID_SZ 48 /** @@ -4290,6 +4297,9 @@ static void max_x86_cpu_initfn(Object *obj) } object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); + if (lbr_supported()) { + object_property_set_bool(OBJECT(cpu), true, "lbr", &error_abort); + } } static const TypeInfo max_x86_cpu_type_info = { @@ -5510,6 +5520,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } if (!cpu->enable_pmu) { *ecx &= ~CPUID_EXT_PDCM; + if (cpu->enable_lbr) { + warn_report("LBR is unsupported since guest PMU is disabled."); + exit(1); + } } break; case 2: @@ -6528,6 +6542,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } } + if (!cpu->max_features && cpu->enable_lbr && + !(env->features[FEAT_1_ECX] & CPUID_EXT_PDCM)) { + warn_report("requested vcpu model doesn't support PDCM for LBR."); + exit(1); + } + if (cpu->ucode_rev == 0) { /* The default is the same as KVM's. */ if (IS_AMD_CPU(env)) { @@ -7165,6 +7185,7 @@ static Property x86_cpu_properties[] = { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), + DEFINE_PROP_BOOL("lbr", X86CPU, enable_lbr, false), DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_RETRY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fad2f874bd..e5f65e9b0c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -357,6 +357,7 @@ typedef enum X86Seg { #define ARCH_CAP_TSX_CTRL_MSR (1<<7) #define MSR_IA32_PERF_CAPABILITIES 0x345 +#define PERF_CAP_LBR_FMT 0x3f #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -1686,6 +1687,7 @@ struct X86CPU { * capabilities) directly to the guest. */ bool enable_pmu; + bool enable_lbr; /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is * disabled by default to avoid breaking migration between QEMU with diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 9be6f76b2c..524ae86b0c 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2652,8 +2652,10 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) uint64_t kvm_perf_cap = kvm_arch_get_supported_msr_feature(kvm_state, MSR_IA32_PERF_CAPABILITIES); - if (kvm_perf_cap) { + if (!cpu->enable_lbr) { + kvm_perf_cap &= ~PERF_CAP_LBR_FMT; + } kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); } @@ -2693,6 +2695,9 @@ static void kvm_init_msrs(X86CPU *cpu) if (has_msr_perf_capabs && cpu->enable_pmu) { kvm_msr_entry_add_perf(cpu, env->features); + } else if (!has_msr_perf_capabs && cpu->enable_lbr) { + warn_report("host doesn't support MSR_IA32_PERF_CAPABILITIES for LBR."); + exit(1); } if (has_msr_ucode_rev) { -- 2.21.3
WARNING: multiple messages have this Message-ID (diff)
From: Like Xu <like.xu@linux.intel.com> To: Paolo Bonzini <pbonzini@redhat.com> Cc: ak@linux.intel.com, Wanpeng Li <wanpengli@tencent.com>, Like Xu <like.xu@linux.intel.com>, kvm@vger.kernel.org, "Michael S. Tsirkin" <mst@redhat.com>, Peter Zijlstra <peterz@infradead.org>, Joerg Roedel <joro@8bytes.org>, Marcelo Tosatti <mtosatti@redhat.com>, linux-kernel@vger.kernel.org, Sean Christopherson <sean.j.christopherson@intel.com>, qemu-devel@nongnu.org, Eduardo Habkost <ehabkost@redhat.com>, wei.w.wang@intel.com, Vitaly Kuznetsov <vkuznets@redhat.com>, Richard Henderson <rth@twiddle.net>, Jim Mattson <jmattson@google.com> Subject: [Qemu-devel] [PATCH 2/2] target/i386: add -cpu, lbr=true support to enable guest LBR Date: Sat, 13 Jun 2020 16:09:58 +0800 [thread overview] Message-ID: <20200613080958.132489-14-like.xu@linux.intel.com> (raw) In-Reply-To: <20200613080958.132489-1-like.xu@linux.intel.com> The LBR feature would be enabled on the guest if: - the KVM is enabled and the PMU is enabled and, - the msr-based-feature IA32_PERF_CAPABILITIES is supporterd and, - the supported returned value for lbr_fmt from this msr is not zero. The LBR feature would be disabled on the guest if: - the msr-based-feature IA32_PERF_CAPABILITIES is unsupporterd OR, - qemu set the IA32_PERF_CAPABILITIES msr feature without lbr_fmt values OR, - the requested guest vcpu model doesn't support PDCM. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: qemu-devel@nongnu.org Signed-off-by: Like Xu <like.xu@linux.intel.com> --- hw/i386/pc.c | 1 + target/i386/cpu.c | 25 +++++++++++++++++++++++-- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 7 ++++++- 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2128f3d6fe..8d8d42a8ea 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -316,6 +316,7 @@ GlobalProperty pc_compat_1_5[] = { { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, { "virtio-net-pci", "any_layout", "off" }, { TYPE_X86_CPU, "pmu", "on" }, + { TYPE_X86_CPU, "lbr", "on" }, { "i440FX-pcihost", "short_root_bus", "0" }, { "q35-pcihost", "short_root_bus", "0" }, }; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e47c9d1604..262a2595fa 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1142,8 +1142,8 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_PERF_CAPABILITIES] = { .type = MSR_FEATURE_WORD, .feat_names = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + "lbr-fmt-bit-0", "lbr-fmt-bit-1", "lbr-fmt-bit-2", "lbr-fmt-bit-3", + "lbr-fmt-bit-4", "lbr-fmt-bit-5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "full-width-write", NULL, NULL, NULL, NULL, NULL, NULL, @@ -4187,6 +4187,13 @@ static bool lmce_supported(void) return !!(mce_cap & MCG_LMCE_P); } +static inline bool lbr_supported(void) +{ + return kvm_enabled() && (PERF_CAP_LBR_FMT & + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_PERF_CAPABILITIES)); +} + #define CPUID_MODEL_ID_SZ 48 /** @@ -4290,6 +4297,9 @@ static void max_x86_cpu_initfn(Object *obj) } object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); + if (lbr_supported()) { + object_property_set_bool(OBJECT(cpu), true, "lbr", &error_abort); + } } static const TypeInfo max_x86_cpu_type_info = { @@ -5510,6 +5520,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } if (!cpu->enable_pmu) { *ecx &= ~CPUID_EXT_PDCM; + if (cpu->enable_lbr) { + warn_report("LBR is unsupported since guest PMU is disabled."); + exit(1); + } } break; case 2: @@ -6528,6 +6542,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } } + if (!cpu->max_features && cpu->enable_lbr && + !(env->features[FEAT_1_ECX] & CPUID_EXT_PDCM)) { + warn_report("requested vcpu model doesn't support PDCM for LBR."); + exit(1); + } + if (cpu->ucode_rev == 0) { /* The default is the same as KVM's. */ if (IS_AMD_CPU(env)) { @@ -7165,6 +7185,7 @@ static Property x86_cpu_properties[] = { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), + DEFINE_PROP_BOOL("lbr", X86CPU, enable_lbr, false), DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_RETRY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fad2f874bd..e5f65e9b0c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -357,6 +357,7 @@ typedef enum X86Seg { #define ARCH_CAP_TSX_CTRL_MSR (1<<7) #define MSR_IA32_PERF_CAPABILITIES 0x345 +#define PERF_CAP_LBR_FMT 0x3f #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -1686,6 +1687,7 @@ struct X86CPU { * capabilities) directly to the guest. */ bool enable_pmu; + bool enable_lbr; /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is * disabled by default to avoid breaking migration between QEMU with diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 9be6f76b2c..524ae86b0c 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2652,8 +2652,10 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) uint64_t kvm_perf_cap = kvm_arch_get_supported_msr_feature(kvm_state, MSR_IA32_PERF_CAPABILITIES); - if (kvm_perf_cap) { + if (!cpu->enable_lbr) { + kvm_perf_cap &= ~PERF_CAP_LBR_FMT; + } kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); } @@ -2693,6 +2695,9 @@ static void kvm_init_msrs(X86CPU *cpu) if (has_msr_perf_capabs && cpu->enable_pmu) { kvm_msr_entry_add_perf(cpu, env->features); + } else if (!has_msr_perf_capabs && cpu->enable_lbr) { + warn_report("host doesn't support MSR_IA32_PERF_CAPABILITIES for LBR."); + exit(1); } if (has_msr_ucode_rev) { -- 2.21.3
next prev parent reply other threads:[~2020-06-13 8:11 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-13 8:09 [PATCH v12 00/11] Guest Last Branch Recording Enabling Like Xu 2020-06-13 8:09 ` [PATCH v12 01/11] perf/x86: Fix variable types for LBR registers Like Xu 2020-07-03 8:01 ` [tip: perf/core] " tip-bot2 for Wei Wang 2020-11-09 6:34 ` [PATCH v12 01/11] " Andi Kleen 2020-11-11 2:14 ` Xu, Like 2020-06-13 8:09 ` [PATCH v12 02/11] perf/x86/core: Refactor hw->idx checks and cleanup Like Xu 2020-07-03 8:01 ` [tip: perf/core] " tip-bot2 for Like Xu 2020-06-13 8:09 ` [PATCH v12 03/11] perf/x86/lbr: Add interface to get LBR information Like Xu 2020-07-03 8:01 ` [tip: perf/core] " tip-bot2 for Like Xu 2020-06-13 8:09 ` [PATCH v12 04/11] perf/x86: Add constraint to create guest LBR event without hw counter Like Xu 2020-06-13 8:09 ` [PATCH v12 05/11] perf/x86: Keep LBR records unchanged in host context for guest usage Like Xu 2020-06-13 8:09 ` [PATCH v12 06/11] KVM: vmx/pmu: Expose LBR to guest via MSR_IA32_PERF_CAPABILITIES Like Xu 2020-07-08 13:36 ` Andi Kleen 2020-07-08 14:38 ` Xu, Like 2020-06-13 8:09 ` [PATCH v12 07/11] KVM: vmx/pmu: Unmask LBR fields in the MSR_IA32_DEBUGCTLMSR emualtion Like Xu 2020-06-13 9:14 ` Xiaoyao Li 2020-06-13 9:42 ` Xu, Like 2020-07-07 20:21 ` Sean Christopherson 2020-07-08 1:37 ` Xiaoyao Li 2020-07-08 7:06 ` Xu, Like 2020-07-10 16:28 ` Sean Christopherson 2020-06-13 8:09 ` [PATCH v12 08/11] KVM: vmx/pmu: Pass-through LBR msrs when guest LBR event is scheduled Like Xu 2020-06-13 8:09 ` [PATCH v12 09/11] KVM: vmx/pmu: Emulate legacy freezing LBRs on virtual PMI Like Xu 2020-06-13 8:09 ` [PATCH v12 10/11] KVM: vmx/pmu: Reduce the overhead of LBR pass-through or cancellation Like Xu 2020-06-13 8:09 ` [PATCH v12 11/11] KVM: vmx/pmu: Release guest LBR event via lazy release mechanism Like Xu 2020-06-13 8:09 ` [Qemu-devel] [PATCH 1/2] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES Like Xu 2020-06-13 8:09 ` Like Xu 2020-06-13 8:09 ` Like Xu [this message] 2020-06-13 8:09 ` [Qemu-devel] [PATCH 2/2] target/i386: add -cpu, lbr=true support to enable guest LBR Like Xu 2020-06-23 13:13 ` [PATCH v12 00/11] Guest Last Branch Recording Enabling Like Xu 2020-07-01 2:38 ` Like Xu 2020-07-02 7:40 ` Peter Zijlstra 2020-07-02 13:11 ` Liang, Kan 2020-07-02 13:58 ` Peter Zijlstra 2020-07-03 7:56 ` Peter Zijlstra 2020-07-03 8:04 ` Xu, Like
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