From: "Pali Rohár" <pali@kernel.org> To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Russell King <linux@armlinux.org.uk>, Andrew Lunn <andrew@lunn.ch>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement <gregory.clement@bootlin.com>, Jason Gunthorpe <jgg@nvidia.com>, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup Date: Tue, 2 Nov 2021 10:02:46 +0100 [thread overview] Message-ID: <20211102090246.unmbruykfdjabfga@pali> (raw) In-Reply-To: <20211102084241.GA6134@alpha.franken.de> On Tuesday 02 November 2021 09:42:41 Thomas Bogendoerfer wrote: > On Mon, Nov 01, 2021 at 04:04:05PM +0100, Pali Rohár wrote: > > - The code relies on rc_pci_fixup being called, which only happens > > when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting > > this causes a booting failure with a non-obvious cause. > > - Update rc_pci_fixup to set the class properly, copying the > > more modern style from other places > > - Correct the rc_pci_fixup comment > > > > This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update > > PCI-E fixup") for all other Marvell platforms which use same buggy PCIe > > controller. > > [..] > > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > > index 771ca53af06d..c8d51bd20b84 100644 > > --- a/arch/mips/Kconfig > > +++ b/arch/mips/Kconfig > > @@ -346,6 +346,7 @@ config MIPS_COBALT > > select CEVT_GT641XX > > select DMA_NONCOHERENT > > select FORCE_PCI > > + select PCI_QUIRKS > > select I8253 > > select I8259 > > select IRQ_MIPS_CPU > > this is enabled by default, via drivers/pci/Kconfig IIRC 'default y' can be disabled but 'select' not. > > config PCI_QUIRKS > default y > bool "Enable PCI quirk workarounds" if EXPERT > help > This enables workarounds for various PCI chipset bugs/quirks. > Disable this only if your target machine is unaffected by PCI > quirks. > > > diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c > > index 44be65c3e6bb..202f3a0bd97d 100644 > > --- a/arch/mips/pci/fixup-cobalt.c > > +++ b/arch/mips/pci/fixup-cobalt.c > > @@ -36,6 +36,12 @@ > > #define VIA_COBALT_BRD_ID_REG 0x94 > > #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) > > > > +/* > > + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it > > + * is operating as a root complex this needs to be switched to > > + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on > > + * the device. Decoding setup is handled by the orion code. > > + */ > > static void qube_raq_galileo_early_fixup(struct pci_dev *dev) > > { > > if (dev->devfn == PCI_DEVFN(0, 0) && > > this is not a PCIe controller, so how is this patch related ? I put that comment into all quirk code which is related to Marvell PCIe device XX:00.0 and changes PCI class type from PCI_CLASS_MEMORY_OTHER to PCI_CLASS_BRIDGE_HOST. From all what I saw, I'm sure that this device with this specific characteristics is really (non-compliant) Marvell PCIe controller. But I do not have this hardware to verify it. > Thomas. > > -- > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a > good idea. [ RFC1925, 2.3 ]
WARNING: multiple messages have this Message-ID (diff)
From: "Pali Rohár" <pali@kernel.org> To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Russell King <linux@armlinux.org.uk>, Andrew Lunn <andrew@lunn.ch>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement <gregory.clement@bootlin.com>, Jason Gunthorpe <jgg@nvidia.com>, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup Date: Tue, 2 Nov 2021 10:02:46 +0100 [thread overview] Message-ID: <20211102090246.unmbruykfdjabfga@pali> (raw) In-Reply-To: <20211102084241.GA6134@alpha.franken.de> On Tuesday 02 November 2021 09:42:41 Thomas Bogendoerfer wrote: > On Mon, Nov 01, 2021 at 04:04:05PM +0100, Pali Rohár wrote: > > - The code relies on rc_pci_fixup being called, which only happens > > when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting > > this causes a booting failure with a non-obvious cause. > > - Update rc_pci_fixup to set the class properly, copying the > > more modern style from other places > > - Correct the rc_pci_fixup comment > > > > This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update > > PCI-E fixup") for all other Marvell platforms which use same buggy PCIe > > controller. > > [..] > > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > > index 771ca53af06d..c8d51bd20b84 100644 > > --- a/arch/mips/Kconfig > > +++ b/arch/mips/Kconfig > > @@ -346,6 +346,7 @@ config MIPS_COBALT > > select CEVT_GT641XX > > select DMA_NONCOHERENT > > select FORCE_PCI > > + select PCI_QUIRKS > > select I8253 > > select I8259 > > select IRQ_MIPS_CPU > > this is enabled by default, via drivers/pci/Kconfig IIRC 'default y' can be disabled but 'select' not. > > config PCI_QUIRKS > default y > bool "Enable PCI quirk workarounds" if EXPERT > help > This enables workarounds for various PCI chipset bugs/quirks. > Disable this only if your target machine is unaffected by PCI > quirks. > > > diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c > > index 44be65c3e6bb..202f3a0bd97d 100644 > > --- a/arch/mips/pci/fixup-cobalt.c > > +++ b/arch/mips/pci/fixup-cobalt.c > > @@ -36,6 +36,12 @@ > > #define VIA_COBALT_BRD_ID_REG 0x94 > > #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) > > > > +/* > > + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it > > + * is operating as a root complex this needs to be switched to > > + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on > > + * the device. Decoding setup is handled by the orion code. > > + */ > > static void qube_raq_galileo_early_fixup(struct pci_dev *dev) > > { > > if (dev->devfn == PCI_DEVFN(0, 0) && > > this is not a PCIe controller, so how is this patch related ? I put that comment into all quirk code which is related to Marvell PCIe device XX:00.0 and changes PCI class type from PCI_CLASS_MEMORY_OTHER to PCI_CLASS_BRIDGE_HOST. From all what I saw, I'm sure that this device with this specific characteristics is really (non-compliant) Marvell PCIe controller. But I do not have this hardware to verify it. > Thomas. > > -- > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a > good idea. [ RFC1925, 2.3 ] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-11-02 9:02 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-01 15:04 [PATCH] PCI: Marvell: Update PCIe fixup Pali Rohár 2021-11-01 15:04 ` Pali Rohár 2021-11-01 16:27 ` Jason Gunthorpe 2021-11-01 16:27 ` Jason Gunthorpe 2021-11-01 17:56 ` Pali Rohár 2021-11-01 17:56 ` Pali Rohár 2021-11-01 18:03 ` Jason Gunthorpe 2021-11-01 18:03 ` Jason Gunthorpe 2021-11-02 8:42 ` Thomas Bogendoerfer 2021-11-02 8:42 ` Thomas Bogendoerfer 2021-11-02 9:02 ` Pali Rohár [this message] 2021-11-02 9:02 ` Pali Rohár 2021-11-02 9:47 ` Thomas Bogendoerfer 2021-11-02 9:47 ` Thomas Bogendoerfer 2021-11-02 10:00 ` Pali Rohár 2021-11-02 10:00 ` Pali Rohár 2021-11-02 12:35 ` Maciej W. Rozycki 2021-11-02 12:35 ` Maciej W. Rozycki 2021-11-02 12:58 ` Pali Rohár 2021-11-02 12:58 ` Pali Rohár 2021-11-02 14:01 ` Maciej W. Rozycki 2021-11-02 14:01 ` Maciej W. Rozycki 2021-11-02 14:49 ` Pali Rohár 2021-11-02 14:49 ` Pali Rohár 2021-11-02 15:48 ` Pali Rohár 2021-11-02 15:48 ` Pali Rohár 2021-11-02 17:03 ` Stefan Roese 2021-11-02 17:03 ` Stefan Roese 2021-11-03 14:59 ` Maciej W. Rozycki 2021-11-03 14:59 ` Maciej W. Rozycki 2021-11-03 14:49 ` Maciej W. Rozycki 2021-11-03 14:49 ` Maciej W. Rozycki 2021-11-03 15:03 ` Pali Rohár 2021-11-03 15:03 ` Pali Rohár 2021-11-02 15:02 ` Thomas Bogendoerfer 2021-11-02 15:02 ` Thomas Bogendoerfer 2021-11-02 15:13 ` Pali Rohár 2021-11-02 15:13 ` Pali Rohár 2021-11-09 23:42 ` Pali Rohár 2021-11-09 23:42 ` Pali Rohár 2021-11-10 8:55 ` Thomas Bogendoerfer 2021-11-10 8:55 ` Thomas Bogendoerfer 2021-11-02 17:12 ` [PATCH v2 1/2] ARM: " Pali Rohár 2021-11-02 17:12 ` Pali Rohár 2021-11-02 17:12 ` [PATCH v2 2/2] MIPS: Cobalt: Explain GT64111 early PCI fixup Pali Rohár 2021-11-03 16:36 ` Thomas Bogendoerfer 2021-11-09 22:53 ` [PATCH v2 1/2] ARM: Marvell: Update PCIe fixup Pali Rohár 2021-11-09 22:53 ` Pali Rohár 2022-05-14 18:21 ` Pali Rohár 2022-05-14 18:21 ` Pali Rohár 2022-07-07 18:31 ` Pali Rohár 2022-07-07 18:31 ` Pali Rohár 2022-07-07 19:22 ` Russell King (Oracle) 2022-07-07 19:22 ` Russell King (Oracle) 2022-02-19 14:30 ` Pali Rohár 2022-02-19 14:30 ` Pali Rohár 2022-07-18 10:34 ` Gregory CLEMENT 2022-07-18 10:34 ` Gregory CLEMENT
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