All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Pali Rohár" <pali@kernel.org>
To: Russell King <linux@armlinux.org.uk>,
	Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Jason Gunthorpe <jgg@nvidia.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] ARM: Marvell: Update PCIe fixup
Date: Sat, 19 Feb 2022 15:30:06 +0100	[thread overview]
Message-ID: <20220219143006.bsr6wdagf5ytynxu@pali> (raw)
In-Reply-To: <20211102171259.9590-1-pali@kernel.org>

PING, Gente reminder for patch 1/2.

On Tuesday 02 November 2021 18:12:58 Pali Rohár wrote:
> - The code relies on rc_pci_fixup being called, which only happens
>   when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting
>   this causes a booting failure with a non-obvious cause.
> - Update rc_pci_fixup to set the class properly, copying the
>   more modern style from other places
> - Correct the rc_pci_fixup comment
> 
> This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update
> PCI-E fixup") for all other Marvell ARM platforms which have same buggy
> PCIe controller and do not use pci-mvebu.c controller driver yet.
> 
> Long-term goal for these Marvell ARM platforms should be conversion to
> pci-mvebu.c controller driver and removal of these fixups in arch code.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Cc: stable@vger.kernel.org
> 
> ---
> Changes in v2:
> * Move MIPS change into separate patch
> * Add information that this patch is for platforms which do not use pci-mvebu.c
> ---
>  arch/arm/Kconfig              |  1 +
>  arch/arm/mach-dove/pcie.c     | 11 ++++++++---
>  arch/arm/mach-mv78xx0/pcie.c  | 11 ++++++++---
>  arch/arm/mach-orion5x/Kconfig |  1 +
>  arch/arm/mach-orion5x/pci.c   | 12 +++++++++---
>  5 files changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fc196421b2ce..9f157e973555 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -400,6 +400,7 @@ config ARCH_DOVE
>  	select GENERIC_IRQ_MULTI_HANDLER
>  	select GPIOLIB
>  	select HAVE_PCI
> +	select PCI_QUIRKS if PCI
>  	select MVEBU_MBUS
>  	select PINCTRL
>  	select PINCTRL_DOVE
> diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
> index ee91ac6b5ebf..ecf057a0f5ba 100644
> --- a/arch/arm/mach-dove/pcie.c
> +++ b/arch/arm/mach-dove/pcie.c
> @@ -135,14 +135,19 @@ static struct pci_ops pcie_ops = {
>  	.write = pcie_wr_conf,
>  };
>  
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void rc_pci_fixup(struct pci_dev *dev)
>  {
> -	/*
> -	 * Prevent enumeration of root complex.
> -	 */
>  	if (dev->bus->parent == NULL && dev->devfn == 0) {
>  		int i;
>  
> +		dev->class &= 0xff;
> +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
>  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>  			dev->resource[i].start = 0;
>  			dev->resource[i].end   = 0;
> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
> index 636d84b40466..9362b5fc116f 100644
> --- a/arch/arm/mach-mv78xx0/pcie.c
> +++ b/arch/arm/mach-mv78xx0/pcie.c
> @@ -177,14 +177,19 @@ static struct pci_ops pcie_ops = {
>  	.write = pcie_wr_conf,
>  };
>  
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void rc_pci_fixup(struct pci_dev *dev)
>  {
> -	/*
> -	 * Prevent enumeration of root complex.
> -	 */
>  	if (dev->bus->parent == NULL && dev->devfn == 0) {
>  		int i;
>  
> +		dev->class &= 0xff;
> +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
>  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>  			dev->resource[i].start = 0;
>  			dev->resource[i].end   = 0;
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index e94a61901ffd..7189a5b1ec46 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -6,6 +6,7 @@ menuconfig ARCH_ORION5X
>  	select GPIOLIB
>  	select MVEBU_MBUS
>  	select FORCE_PCI
> +	select PCI_QUIRKS
>  	select PHYLIB if NETDEVICES
>  	select PLAT_ORION_LEGACY
>  	help
> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> index 76951bfbacf5..5145fe89702e 100644
> --- a/arch/arm/mach-orion5x/pci.c
> +++ b/arch/arm/mach-orion5x/pci.c
> @@ -509,14 +509,20 @@ static int __init pci_setup(struct pci_sys_data *sys)
>  /*****************************************************************************
>   * General PCIe + PCI
>   ****************************************************************************/
> +
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void rc_pci_fixup(struct pci_dev *dev)
>  {
> -	/*
> -	 * Prevent enumeration of root complex.
> -	 */
>  	if (dev->bus->parent == NULL && dev->devfn == 0) {
>  		int i;
>  
> +		dev->class &= 0xff;
> +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
>  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>  			dev->resource[i].start = 0;
>  			dev->resource[i].end   = 0;
> -- 
> 2.20.1
> 

WARNING: multiple messages have this Message-ID (diff)
From: "Pali Rohár" <pali@kernel.org>
To: Russell King <linux@armlinux.org.uk>,
	Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Gregory Clement <gregory.clement@bootlin.com>,
	Jason Gunthorpe <jgg@nvidia.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] ARM: Marvell: Update PCIe fixup
Date: Sat, 19 Feb 2022 15:30:06 +0100	[thread overview]
Message-ID: <20220219143006.bsr6wdagf5ytynxu@pali> (raw)
In-Reply-To: <20211102171259.9590-1-pali@kernel.org>

PING, Gente reminder for patch 1/2.

On Tuesday 02 November 2021 18:12:58 Pali Rohár wrote:
> - The code relies on rc_pci_fixup being called, which only happens
>   when CONFIG_PCI_QUIRKS is enabled, so add that to Kconfig. Omitting
>   this causes a booting failure with a non-obvious cause.
> - Update rc_pci_fixup to set the class properly, copying the
>   more modern style from other places
> - Correct the rc_pci_fixup comment
> 
> This patch just re-applies commit 1dc831bf53fd ("ARM: Kirkwood: Update
> PCI-E fixup") for all other Marvell ARM platforms which have same buggy
> PCIe controller and do not use pci-mvebu.c controller driver yet.
> 
> Long-term goal for these Marvell ARM platforms should be conversion to
> pci-mvebu.c controller driver and removal of these fixups in arch code.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Cc: Jason Gunthorpe <jgg@nvidia.com>
> Cc: stable@vger.kernel.org
> 
> ---
> Changes in v2:
> * Move MIPS change into separate patch
> * Add information that this patch is for platforms which do not use pci-mvebu.c
> ---
>  arch/arm/Kconfig              |  1 +
>  arch/arm/mach-dove/pcie.c     | 11 ++++++++---
>  arch/arm/mach-mv78xx0/pcie.c  | 11 ++++++++---
>  arch/arm/mach-orion5x/Kconfig |  1 +
>  arch/arm/mach-orion5x/pci.c   | 12 +++++++++---
>  5 files changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fc196421b2ce..9f157e973555 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -400,6 +400,7 @@ config ARCH_DOVE
>  	select GENERIC_IRQ_MULTI_HANDLER
>  	select GPIOLIB
>  	select HAVE_PCI
> +	select PCI_QUIRKS if PCI
>  	select MVEBU_MBUS
>  	select PINCTRL
>  	select PINCTRL_DOVE
> diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
> index ee91ac6b5ebf..ecf057a0f5ba 100644
> --- a/arch/arm/mach-dove/pcie.c
> +++ b/arch/arm/mach-dove/pcie.c
> @@ -135,14 +135,19 @@ static struct pci_ops pcie_ops = {
>  	.write = pcie_wr_conf,
>  };
>  
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void rc_pci_fixup(struct pci_dev *dev)
>  {
> -	/*
> -	 * Prevent enumeration of root complex.
> -	 */
>  	if (dev->bus->parent == NULL && dev->devfn == 0) {
>  		int i;
>  
> +		dev->class &= 0xff;
> +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
>  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>  			dev->resource[i].start = 0;
>  			dev->resource[i].end   = 0;
> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
> index 636d84b40466..9362b5fc116f 100644
> --- a/arch/arm/mach-mv78xx0/pcie.c
> +++ b/arch/arm/mach-mv78xx0/pcie.c
> @@ -177,14 +177,19 @@ static struct pci_ops pcie_ops = {
>  	.write = pcie_wr_conf,
>  };
>  
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void rc_pci_fixup(struct pci_dev *dev)
>  {
> -	/*
> -	 * Prevent enumeration of root complex.
> -	 */
>  	if (dev->bus->parent == NULL && dev->devfn == 0) {
>  		int i;
>  
> +		dev->class &= 0xff;
> +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
>  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>  			dev->resource[i].start = 0;
>  			dev->resource[i].end   = 0;
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index e94a61901ffd..7189a5b1ec46 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -6,6 +6,7 @@ menuconfig ARCH_ORION5X
>  	select GPIOLIB
>  	select MVEBU_MBUS
>  	select FORCE_PCI
> +	select PCI_QUIRKS
>  	select PHYLIB if NETDEVICES
>  	select PLAT_ORION_LEGACY
>  	help
> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> index 76951bfbacf5..5145fe89702e 100644
> --- a/arch/arm/mach-orion5x/pci.c
> +++ b/arch/arm/mach-orion5x/pci.c
> @@ -509,14 +509,20 @@ static int __init pci_setup(struct pci_sys_data *sys)
>  /*****************************************************************************
>   * General PCIe + PCI
>   ****************************************************************************/
> +
> +/*
> + * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
> + * is operating as a root complex this needs to be switched to
> + * PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
> + * the device. Decoding setup is handled by the orion code.
> + */
>  static void rc_pci_fixup(struct pci_dev *dev)
>  {
> -	/*
> -	 * Prevent enumeration of root complex.
> -	 */
>  	if (dev->bus->parent == NULL && dev->devfn == 0) {
>  		int i;
>  
> +		dev->class &= 0xff;
> +		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
>  		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
>  			dev->resource[i].start = 0;
>  			dev->resource[i].end   = 0;
> -- 
> 2.20.1
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-02-19 14:30 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-01 15:04 [PATCH] PCI: Marvell: Update PCIe fixup Pali Rohár
2021-11-01 15:04 ` Pali Rohár
2021-11-01 16:27 ` Jason Gunthorpe
2021-11-01 16:27   ` Jason Gunthorpe
2021-11-01 17:56   ` Pali Rohár
2021-11-01 17:56     ` Pali Rohár
2021-11-01 18:03     ` Jason Gunthorpe
2021-11-01 18:03       ` Jason Gunthorpe
2021-11-02  8:42 ` Thomas Bogendoerfer
2021-11-02  8:42   ` Thomas Bogendoerfer
2021-11-02  9:02   ` Pali Rohár
2021-11-02  9:02     ` Pali Rohár
2021-11-02  9:47     ` Thomas Bogendoerfer
2021-11-02  9:47       ` Thomas Bogendoerfer
2021-11-02 10:00       ` Pali Rohár
2021-11-02 10:00         ` Pali Rohár
2021-11-02 12:35         ` Maciej W. Rozycki
2021-11-02 12:35           ` Maciej W. Rozycki
2021-11-02 12:58           ` Pali Rohár
2021-11-02 12:58             ` Pali Rohár
2021-11-02 14:01             ` Maciej W. Rozycki
2021-11-02 14:01               ` Maciej W. Rozycki
2021-11-02 14:49               ` Pali Rohár
2021-11-02 14:49                 ` Pali Rohár
2021-11-02 15:48                 ` Pali Rohár
2021-11-02 15:48                   ` Pali Rohár
2021-11-02 17:03                   ` Stefan Roese
2021-11-02 17:03                     ` Stefan Roese
2021-11-03 14:59                   ` Maciej W. Rozycki
2021-11-03 14:59                     ` Maciej W. Rozycki
2021-11-03 14:49                 ` Maciej W. Rozycki
2021-11-03 14:49                   ` Maciej W. Rozycki
2021-11-03 15:03                   ` Pali Rohár
2021-11-03 15:03                     ` Pali Rohár
2021-11-02 15:02         ` Thomas Bogendoerfer
2021-11-02 15:02           ` Thomas Bogendoerfer
2021-11-02 15:13           ` Pali Rohár
2021-11-02 15:13             ` Pali Rohár
2021-11-09 23:42             ` Pali Rohár
2021-11-09 23:42               ` Pali Rohár
2021-11-10  8:55               ` Thomas Bogendoerfer
2021-11-10  8:55                 ` Thomas Bogendoerfer
2021-11-02 17:12 ` [PATCH v2 1/2] ARM: " Pali Rohár
2021-11-02 17:12   ` Pali Rohár
2021-11-02 17:12   ` [PATCH v2 2/2] MIPS: Cobalt: Explain GT64111 early PCI fixup Pali Rohár
2021-11-03 16:36     ` Thomas Bogendoerfer
2021-11-09 22:53   ` [PATCH v2 1/2] ARM: Marvell: Update PCIe fixup Pali Rohár
2021-11-09 22:53     ` Pali Rohár
2022-05-14 18:21     ` Pali Rohár
2022-05-14 18:21       ` Pali Rohár
2022-07-07 18:31       ` Pali Rohár
2022-07-07 18:31         ` Pali Rohár
2022-07-07 19:22         ` Russell King (Oracle)
2022-07-07 19:22           ` Russell King (Oracle)
2022-02-19 14:30   ` Pali Rohár [this message]
2022-02-19 14:30     ` Pali Rohár
2022-07-18 10:34     ` Gregory CLEMENT
2022-07-18 10:34       ` Gregory CLEMENT

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220219143006.bsr6wdagf5ytynxu@pali \
    --to=pali@kernel.org \
    --cc=andrew@lunn.ch \
    --cc=gregory.clement@bootlin.com \
    --cc=jgg@nvidia.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux@armlinux.org.uk \
    --cc=sebastian.hesselbarth@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.