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From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Eric Biederman <ebiederm@xmission.com>,
	Kees Cook <keescook@chromium.org>, Guo Ren <guoren@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>, Zong Li <zong.li@sifive.com>,
	Nick Knight <nick.knight@sifive.com>,
	Kefeng Wang <wangkefeng.wang@huawei.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Andrew Bresticker <abrestic@rivosinc.com>
Subject: [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv
Date: Wed, 25 Jan 2023 14:20:51 +0000	[thread overview]
Message-ID: <20230125142056.18356-15-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com>

From: Vincent Chen <vincent.chen@sifive.com>

The vector register belongs to the signal context. They need to be stored
and restored as entering and leaving the signal handler. According to the
V-extension specification, the maximum length of the vector registers can
be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a
sigframe, it may not be enough. To resolve this problem, this patch refers
to the commit 94b07c1f8c39c
("arm64: signal: Report signal frame size to userspace via auxv") to enable
userspace to know the minimum required sigframe size through the auxiliary
vector and use it to allocate enough memory for signal context.

Note that auxv always reports size of the sigframe as if V exists for
all starting processes, whenever the kernel has CONFIG_RISCV_ISA_V. The
reason is that users usually reference this value to allocate an
alternative signal stack, and the user may use V anytime. So the user
must reserve a space for V-context in sigframe in case that the signal
handler invokes after the kernel allocating V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/include/asm/elf.h         |  9 +++++++++
 arch/riscv/include/asm/processor.h   |  2 ++
 arch/riscv/include/uapi/asm/auxvec.h |  1 +
 arch/riscv/kernel/signal.c           | 20 +++++++++++++++-----
 4 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index e7acffdf21d2..c7eb40383453 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -103,6 +103,15 @@ do {								\
 		get_cache_size(3, CACHE_TYPE_UNIFIED));		\
 	NEW_AUX_ENT(AT_L3_CACHEGEOMETRY,			\
 		get_cache_geometry(3, CACHE_TYPE_UNIFIED));	\
+	/*							 \
+	 * Should always be nonzero unless there's a kernel bug. \
+	 * If we haven't determined a sensible value to give to	 \
+	 * userspace, omit the entry:				 \
+	 */							 \
+	if (likely(signal_minsigstksz))				 \
+		NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \
+	else							 \
+		NEW_AUX_ENT(AT_IGNORE, 0);			 \
 } while (0)
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES
 struct linux_binprm;
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 44d2eb381ca6..4f36c553605e 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -7,6 +7,7 @@
 #define _ASM_RISCV_PROCESSOR_H
 
 #include <linux/const.h>
+#include <linux/cache.h>
 
 #include <vdso/processor.h>
 
@@ -81,6 +82,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
+extern unsigned long signal_minsigstksz __ro_after_init;
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h
index fb187a33ce58..2c50d9ca30e0 100644
--- a/arch/riscv/include/uapi/asm/auxvec.h
+++ b/arch/riscv/include/uapi/asm/auxvec.h
@@ -35,5 +35,6 @@
 
 /* entries in ARCH_DLINFO */
 #define AT_VECTOR_SIZE_ARCH	9
+#define AT_MINSIGSTKSZ 51
 
 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index fe91475e63e4..8f5549c7eac5 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -21,6 +21,8 @@
 #include <asm/vector.h>
 #include <asm/csr.h>
 
+unsigned long __ro_after_init signal_minsigstksz;
+
 extern u32 __user_rt_sigreturn[2];
 static size_t rvv_sc_size;
 
@@ -195,7 +197,7 @@ static long restore_sigcontext(struct pt_regs *regs,
 	return -EINVAL;
 }
 
-static size_t cal_rt_frame_size(void)
+static size_t cal_rt_frame_size(bool cal_all)
 {
 	struct rt_sigframe __user *frame;
 	size_t frame_size;
@@ -203,8 +205,10 @@ static size_t cal_rt_frame_size(void)
 
 	frame_size = sizeof(*frame);
 
-	if (has_vector() && vstate_query(task_pt_regs(current)))
-		total_context_size += rvv_sc_size;
+	if (has_vector()) {
+		if (cal_all || vstate_query(task_pt_regs(current)))
+			total_context_size += rvv_sc_size;
+	}
 	/* Preserved a __riscv_ctx_hdr for END signal context header. */
 	total_context_size += sizeof(struct __riscv_ctx_hdr);
 
@@ -221,7 +225,7 @@ SYSCALL_DEFINE0(rt_sigreturn)
 	struct rt_sigframe __user *frame;
 	struct task_struct *task;
 	sigset_t set;
-	size_t frame_size = cal_rt_frame_size();
+	size_t frame_size = cal_rt_frame_size(false);
 
 	/* Always make any pending restarted system calls return -EINTR */
 	current->restart_block.fn = do_no_restart_syscall;
@@ -309,7 +313,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
 {
 	struct rt_sigframe __user *frame;
 	long err = 0;
-	size_t frame_size = cal_rt_frame_size();
+	size_t frame_size = cal_rt_frame_size(false);
 
 	frame = get_sigframe(ksig, regs, frame_size);
 	if (!access_ok(frame, frame_size))
@@ -472,4 +476,10 @@ void __init init_rt_signal_env(void)
 {
 	rvv_sc_size = sizeof(struct __riscv_ctx_hdr) +
 		      sizeof(struct __sc_riscv_v_state) + riscv_vsize;
+	/*
+	 * Determine the stack space required for guaranteed signal delivery.
+	 * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry
+	 * in the auxiliary array at process startup.
+	 */
+	signal_minsigstksz = cal_rt_frame_size(true);
 }
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: Kefeng Wang <wangkefeng.wang@huawei.com>,
	guoren@linux.alibaba.com, Kees Cook <keescook@chromium.org>,
	Nick Knight <nick.knight@sifive.com>,
	Andrew Bresticker <abrestic@rivosinc.com>,
	vineetg@rivosinc.com, Vincent Chen <vincent.chen@sifive.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
	Eric Biederman <ebiederm@xmission.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	greentime.hu@sifive.com, Zong Li <zong.li@sifive.com>,
	Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv
Date: Wed, 25 Jan 2023 14:20:51 +0000	[thread overview]
Message-ID: <20230125142056.18356-15-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com>

From: Vincent Chen <vincent.chen@sifive.com>

The vector register belongs to the signal context. They need to be stored
and restored as entering and leaving the signal handler. According to the
V-extension specification, the maximum length of the vector registers can
be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a
sigframe, it may not be enough. To resolve this problem, this patch refers
to the commit 94b07c1f8c39c
("arm64: signal: Report signal frame size to userspace via auxv") to enable
userspace to know the minimum required sigframe size through the auxiliary
vector and use it to allocate enough memory for signal context.

Note that auxv always reports size of the sigframe as if V exists for
all starting processes, whenever the kernel has CONFIG_RISCV_ISA_V. The
reason is that users usually reference this value to allocate an
alternative signal stack, and the user may use V anytime. So the user
must reserve a space for V-context in sigframe in case that the signal
handler invokes after the kernel allocating V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/include/asm/elf.h         |  9 +++++++++
 arch/riscv/include/asm/processor.h   |  2 ++
 arch/riscv/include/uapi/asm/auxvec.h |  1 +
 arch/riscv/kernel/signal.c           | 20 +++++++++++++++-----
 4 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index e7acffdf21d2..c7eb40383453 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -103,6 +103,15 @@ do {								\
 		get_cache_size(3, CACHE_TYPE_UNIFIED));		\
 	NEW_AUX_ENT(AT_L3_CACHEGEOMETRY,			\
 		get_cache_geometry(3, CACHE_TYPE_UNIFIED));	\
+	/*							 \
+	 * Should always be nonzero unless there's a kernel bug. \
+	 * If we haven't determined a sensible value to give to	 \
+	 * userspace, omit the entry:				 \
+	 */							 \
+	if (likely(signal_minsigstksz))				 \
+		NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \
+	else							 \
+		NEW_AUX_ENT(AT_IGNORE, 0);			 \
 } while (0)
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES
 struct linux_binprm;
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 44d2eb381ca6..4f36c553605e 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -7,6 +7,7 @@
 #define _ASM_RISCV_PROCESSOR_H
 
 #include <linux/const.h>
+#include <linux/cache.h>
 
 #include <vdso/processor.h>
 
@@ -81,6 +82,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
+extern unsigned long signal_minsigstksz __ro_after_init;
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h
index fb187a33ce58..2c50d9ca30e0 100644
--- a/arch/riscv/include/uapi/asm/auxvec.h
+++ b/arch/riscv/include/uapi/asm/auxvec.h
@@ -35,5 +35,6 @@
 
 /* entries in ARCH_DLINFO */
 #define AT_VECTOR_SIZE_ARCH	9
+#define AT_MINSIGSTKSZ 51
 
 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index fe91475e63e4..8f5549c7eac5 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -21,6 +21,8 @@
 #include <asm/vector.h>
 #include <asm/csr.h>
 
+unsigned long __ro_after_init signal_minsigstksz;
+
 extern u32 __user_rt_sigreturn[2];
 static size_t rvv_sc_size;
 
@@ -195,7 +197,7 @@ static long restore_sigcontext(struct pt_regs *regs,
 	return -EINVAL;
 }
 
-static size_t cal_rt_frame_size(void)
+static size_t cal_rt_frame_size(bool cal_all)
 {
 	struct rt_sigframe __user *frame;
 	size_t frame_size;
@@ -203,8 +205,10 @@ static size_t cal_rt_frame_size(void)
 
 	frame_size = sizeof(*frame);
 
-	if (has_vector() && vstate_query(task_pt_regs(current)))
-		total_context_size += rvv_sc_size;
+	if (has_vector()) {
+		if (cal_all || vstate_query(task_pt_regs(current)))
+			total_context_size += rvv_sc_size;
+	}
 	/* Preserved a __riscv_ctx_hdr for END signal context header. */
 	total_context_size += sizeof(struct __riscv_ctx_hdr);
 
@@ -221,7 +225,7 @@ SYSCALL_DEFINE0(rt_sigreturn)
 	struct rt_sigframe __user *frame;
 	struct task_struct *task;
 	sigset_t set;
-	size_t frame_size = cal_rt_frame_size();
+	size_t frame_size = cal_rt_frame_size(false);
 
 	/* Always make any pending restarted system calls return -EINTR */
 	current->restart_block.fn = do_no_restart_syscall;
@@ -309,7 +313,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
 {
 	struct rt_sigframe __user *frame;
 	long err = 0;
-	size_t frame_size = cal_rt_frame_size();
+	size_t frame_size = cal_rt_frame_size(false);
 
 	frame = get_sigframe(ksig, regs, frame_size);
 	if (!access_ok(frame, frame_size))
@@ -472,4 +476,10 @@ void __init init_rt_signal_env(void)
 {
 	rvv_sc_size = sizeof(struct __riscv_ctx_hdr) +
 		      sizeof(struct __sc_riscv_v_state) + riscv_vsize;
+	/*
+	 * Determine the stack space required for guaranteed signal delivery.
+	 * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry
+	 * in the auxiliary array at process startup.
+	 */
+	signal_minsigstksz = cal_rt_frame_size(true);
 }
-- 
2.17.1


_______________________________________________
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  parent reply	other threads:[~2023-01-25 14:23 UTC|newest]

Thread overview: 128+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu
2023-01-25 14:20 ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:15   ` Conor Dooley
2023-01-25 21:15     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:33   ` Conor Dooley
2023-01-25 21:33     ` Conor Dooley
2023-01-28  7:09     ` Guo Ren
2023-01-28  7:09       ` Guo Ren
2023-01-28 10:28       ` Conor Dooley
2023-01-28 10:28         ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 22:16   ` Conor Dooley
2023-01-25 22:16     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:54   ` Conor Dooley
2023-01-25 21:54     ` Conor Dooley
2023-01-25 21:57     ` Vineet Gupta
2023-01-25 21:57       ` Vineet Gupta
2023-01-25 22:18       ` Conor Dooley
2023-01-25 22:18         ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:51   ` Conor Dooley
2023-01-25 21:51     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:06   ` Conor Dooley
2023-01-26 21:06     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:24   ` Conor Dooley
2023-01-26 21:24     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:32   ` Conor Dooley
2023-01-26 21:32     ` Conor Dooley
2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 21:44   ` Conor Dooley
2023-01-26 21:44     ` Conor Dooley
2023-01-31  2:55   ` Vineet Gupta
2023-01-31  2:55     ` Vineet Gupta
2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-26 23:11   ` Conor Dooley
2023-01-26 23:11     ` Conor Dooley
2023-02-06 12:00     ` Andy Chiu
2023-02-06 12:00       ` Andy Chiu
2023-02-06 13:40       ` Conor Dooley
2023-02-06 13:40         ` Conor Dooley
2023-02-10 12:00         ` Andy Chiu
2023-02-10 12:00           ` Andy Chiu
2023-02-07 14:36   ` Björn Töpel
2023-02-07 14:36     ` Björn Töpel
2023-02-13 22:54     ` Vineet Gupta
2023-02-13 22:54       ` Vineet Gupta
2023-02-14  6:43       ` Björn Töpel
2023-02-14  6:43         ` Björn Töpel
2023-02-14 15:36         ` Andy Chiu
2023-02-14 15:36           ` Andy Chiu
2023-02-14 16:50           ` Björn Töpel
2023-02-14 16:50             ` Björn Töpel
2023-02-14 17:24             ` Vineet Gupta
2023-02-14 17:24               ` Vineet Gupta
2023-02-15  7:14               ` Björn Töpel
2023-02-15  7:14                 ` Björn Töpel
2023-02-15 14:39                 ` Andy Chiu
2023-02-15 14:39                   ` Andy Chiu
2023-02-07 21:18   ` Vineet Gupta
2023-02-07 21:18     ` Vineet Gupta
2023-02-08  9:20     ` Björn Töpel
2023-02-08  9:20       ` Björn Töpel
2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` Andy Chiu [this message]
2023-01-25 14:20   ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-01-26 23:19   ` Conor Dooley
2023-01-26 23:19     ` Conor Dooley
2023-01-31 12:34     ` Andy Chiu
2023-01-31 12:34       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-27 20:31   ` Conor Dooley
2023-01-27 20:31     ` Conor Dooley
2023-01-31 12:34     ` Andy Chiu
2023-01-31 12:34       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-27 20:43   ` Conor Dooley
2023-01-27 20:43     ` Conor Dooley
2023-01-30  9:58     ` Andy Chiu
2023-01-30  9:58       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-27 11:28   ` Anup Patel
2023-01-27 11:28     ` Anup Patel
2023-01-30  8:18     ` Andy Chiu
2023-01-30  8:18       ` Andy Chiu
2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-01-25 14:20   ` Andy Chiu
2023-01-25 21:04   ` Conor Dooley
2023-01-25 21:04     ` Conor Dooley
2023-01-25 21:38     ` Jessica Clarke
2023-01-25 21:38       ` Jessica Clarke
2023-01-25 22:24       ` Conor Dooley
2023-01-25 22:24         ` Conor Dooley
2023-01-30  6:38     ` Andy Chiu
2023-01-30  6:38       ` Andy Chiu
2023-01-30 18:38       ` Vineet Gupta
2023-01-30 18:38         ` Vineet Gupta
2023-01-30  7:46     ` Andy Chiu
2023-01-30  7:46       ` Andy Chiu
2023-01-30  8:13       ` Conor Dooley
2023-01-30  8:13         ` Conor Dooley
2023-02-08 18:19         ` Conor Dooley
2023-02-08 18:19           ` Conor Dooley

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