From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Vincent Chen <vincent.chen@sifive.com>, Han-Kuan Chen <hankuan.chen@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Nicolas Saenz Julienne <nsaenzju@redhat.com>, Frederic Weisbecker <frederic@kernel.org>, Andrew Bresticker <abrestic@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Changbin Du <changbin.du@intel.com>, Myrtle Shah <gatecat@ds0.me> Subject: [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Date: Wed, 25 Jan 2023 14:20:42 +0000 [thread overview] Message-ID: <20230125142056.18356-6-andy.chiu@sifive.com> (raw) In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com> Disable vector instructions execution for kernel mode at its entrances. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com> Co-developed-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> [vineetg: split off vecreg file clearing] Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/kernel/entry.S | 6 +++--- arch/riscv/kernel/head.S | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 99d38fdf8b18..e38676d9a0d6 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -77,10 +77,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index ea803c96eeff..7cc975ce619d 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -140,10 +140,10 @@ secondary_start_sbi: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 /* Set trap vector to spin forever to help debug */ @@ -234,10 +234,10 @@ pmp_done: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 #ifdef CONFIG_RISCV_BOOT_SPINWAIT -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Vincent Chen <vincent.chen@sifive.com>, Han-Kuan Chen <hankuan.chen@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>, Nicolas Saenz Julienne <nsaenzju@redhat.com>, Frederic Weisbecker <frederic@kernel.org>, Andrew Bresticker <abrestic@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Changbin Du <changbin.du@intel.com>, Myrtle Shah <gatecat@ds0.me> Subject: [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Date: Wed, 25 Jan 2023 14:20:42 +0000 [thread overview] Message-ID: <20230125142056.18356-6-andy.chiu@sifive.com> (raw) In-Reply-To: <20230125142056.18356-1-andy.chiu@sifive.com> Disable vector instructions execution for kernel mode at its entrances. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com> Co-developed-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> [vineetg: split off vecreg file clearing] Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- arch/riscv/kernel/entry.S | 6 +++--- arch/riscv/kernel/head.S | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 99d38fdf8b18..e38676d9a0d6 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -77,10 +77,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index ea803c96eeff..7cc975ce619d 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -140,10 +140,10 @@ secondary_start_sbi: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 /* Set trap vector to spin forever to help debug */ @@ -234,10 +234,10 @@ pmp_done: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 #ifdef CONFIG_RISCV_BOOT_SPINWAIT -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-25 14:21 UTC|newest] Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-25 14:20 [PATCH -next v13 00/19] riscv: Add vector ISA support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:15 ` Conor Dooley 2023-01-25 21:15 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:33 ` Conor Dooley 2023-01-25 21:33 ` Conor Dooley 2023-01-28 7:09 ` Guo Ren 2023-01-28 7:09 ` Guo Ren 2023-01-28 10:28 ` Conor Dooley 2023-01-28 10:28 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 03/19] riscv: Add new csr defines related to vector extension Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 22:16 ` Conor Dooley 2023-01-25 22:16 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 04/19] riscv: Clear vector regfile on bootup Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:54 ` Conor Dooley 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 21:57 ` Vineet Gupta 2023-01-25 22:18 ` Conor Dooley 2023-01-25 22:18 ` Conor Dooley 2023-01-25 14:20 ` Andy Chiu [this message] 2023-01-25 14:20 ` [PATCH -next v13 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu 2023-01-25 21:51 ` Conor Dooley 2023-01-25 21:51 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:06 ` Conor Dooley 2023-01-26 21:06 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 07/19] riscv: Introduce riscv_vsize to record size of Vector context Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:24 ` Conor Dooley 2023-01-26 21:24 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:32 ` Conor Dooley 2023-01-26 21:32 ` Conor Dooley 2023-01-25 14:20 ` [PATCH -next v13 09/19] riscv: Add task switch support for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 21:44 ` Conor Dooley 2023-01-26 21:44 ` Conor Dooley 2023-01-31 2:55 ` Vineet Gupta 2023-01-31 2:55 ` Vineet Gupta 2023-01-25 14:20 ` [PATCH -next v13 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:11 ` Conor Dooley 2023-01-26 23:11 ` Conor Dooley 2023-02-06 12:00 ` Andy Chiu 2023-02-06 12:00 ` Andy Chiu 2023-02-06 13:40 ` Conor Dooley 2023-02-06 13:40 ` Conor Dooley 2023-02-10 12:00 ` Andy Chiu 2023-02-10 12:00 ` Andy Chiu 2023-02-07 14:36 ` Björn Töpel 2023-02-07 14:36 ` Björn Töpel 2023-02-13 22:54 ` Vineet Gupta 2023-02-13 22:54 ` Vineet Gupta 2023-02-14 6:43 ` Björn Töpel 2023-02-14 6:43 ` Björn Töpel 2023-02-14 15:36 ` Andy Chiu 2023-02-14 15:36 ` Andy Chiu 2023-02-14 16:50 ` Björn Töpel 2023-02-14 16:50 ` Björn Töpel 2023-02-14 17:24 ` Vineet Gupta 2023-02-14 17:24 ` Vineet Gupta 2023-02-15 7:14 ` Björn Töpel 2023-02-15 7:14 ` Björn Töpel 2023-02-15 14:39 ` Andy Chiu 2023-02-15 14:39 ` Andy Chiu 2023-02-07 21:18 ` Vineet Gupta 2023-02-07 21:18 ` Vineet Gupta 2023-02-08 9:20 ` Björn Töpel 2023-02-08 9:20 ` Björn Töpel 2023-01-25 14:20 ` [PATCH -next v13 11/19] riscv: Add ptrace vector support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-26 23:19 ` Conor Dooley 2023-01-26 23:19 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 15/19] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:31 ` Conor Dooley 2023-01-27 20:31 ` Conor Dooley 2023-01-31 12:34 ` Andy Chiu 2023-01-31 12:34 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 16/19] riscv: Add V extension to KVM ISA Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 20:43 ` Conor Dooley 2023-01-27 20:43 ` Conor Dooley 2023-01-30 9:58 ` Andy Chiu 2023-01-30 9:58 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 17/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 18/19] riscv: kvm: redirect illegal instruction traps to guests Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-27 11:28 ` Anup Patel 2023-01-27 11:28 ` Anup Patel 2023-01-30 8:18 ` Andy Chiu 2023-01-30 8:18 ` Andy Chiu 2023-01-25 14:20 ` [PATCH -next v13 19/19] riscv: Enable Vector code to be built Andy Chiu 2023-01-25 14:20 ` Andy Chiu 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:04 ` Conor Dooley 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 21:38 ` Jessica Clarke 2023-01-25 22:24 ` Conor Dooley 2023-01-25 22:24 ` Conor Dooley 2023-01-30 6:38 ` Andy Chiu 2023-01-30 6:38 ` Andy Chiu 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 18:38 ` Vineet Gupta 2023-01-30 7:46 ` Andy Chiu 2023-01-30 7:46 ` Andy Chiu 2023-01-30 8:13 ` Conor Dooley 2023-01-30 8:13 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley 2023-02-08 18:19 ` Conor Dooley
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