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From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: linux-arm-msm@vger.kernel.org, andersson@kernel.org,
	agross@kernel.org, krzysztof.kozlowski@linaro.org
Cc: marijn.suijten@somainline.org,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Clark <robdclark@gmail.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	Akhil P Oommen <quic_akhilpo@quicinc.com>,
	Chia-I Wu <olvaffe@gmail.com>,
	Douglas Anderson <dianders@chromium.org>,
	dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 14/14] drm/msm/a6xx: Add A610 speedbin support
Date: Thu, 26 Jan 2023 16:16:18 +0100	[thread overview]
Message-ID: <20230126151618.225127-15-konrad.dybcio@linaro.org> (raw)
In-Reply-To: <20230126151618.225127-1-konrad.dybcio@linaro.org>

A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 89990bec897f..214d81537431 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2079,6 +2079,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 	return progress;
 }
 
+static u32 a610_get_speed_bin(u32 fuse)
+{
+	/*
+	 * There are (at least) three SoCs implementing A610: SM6125 (trinket),
+	 * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning,
+	 * as only a single SKU exists and we don't support khaje upstream yet.
+	 * Hence, this matching table is only valid for bengal and can be easily
+	 * expanded if need be.
+	 */
+
+	if (fuse == 0)
+		return 0;
+	else if (fuse == 206)
+		return 1;
+	else if (fuse == 200)
+		return 2;
+	else if (fuse == 157)
+		return 3;
+	else if (fuse == 127)
+		return 4;
+
+	return UINT_MAX;
+}
+
 static u32 a618_get_speed_bin(u32 fuse)
 {
 	if (fuse == 0)
@@ -2175,6 +2199,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 {
 	u32 val = UINT_MAX;
 
+	if (adreno_cmp_rev(ADRENO_REV(6, 1, 0, ANY_ID), rev))
+		val = a610_get_speed_bin(fuse);
+
 	if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
 		val = a618_get_speed_bin(fuse);
 
-- 
2.39.1


WARNING: multiple messages have this Message-ID (diff)
From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: linux-arm-msm@vger.kernel.org, andersson@kernel.org,
	agross@kernel.org, krzysztof.kozlowski@linaro.org
Cc: freedreno@lists.freedesktop.org,
	Akhil P Oommen <quic_akhilpo@quicinc.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	dri-devel@lists.freedesktop.org,
	Douglas Anderson <dianders@chromium.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	marijn.suijten@somainline.org, Sean Paul <sean@poorly.run>,
	linux-kernel@vger.kernel.org
Subject: [PATCH 14/14] drm/msm/a6xx: Add A610 speedbin support
Date: Thu, 26 Jan 2023 16:16:18 +0100	[thread overview]
Message-ID: <20230126151618.225127-15-konrad.dybcio@linaro.org> (raw)
In-Reply-To: <20230126151618.225127-1-konrad.dybcio@linaro.org>

A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 89990bec897f..214d81537431 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2079,6 +2079,30 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 	return progress;
 }
 
+static u32 a610_get_speed_bin(u32 fuse)
+{
+	/*
+	 * There are (at least) three SoCs implementing A610: SM6125 (trinket),
+	 * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning,
+	 * as only a single SKU exists and we don't support khaje upstream yet.
+	 * Hence, this matching table is only valid for bengal and can be easily
+	 * expanded if need be.
+	 */
+
+	if (fuse == 0)
+		return 0;
+	else if (fuse == 206)
+		return 1;
+	else if (fuse == 200)
+		return 2;
+	else if (fuse == 157)
+		return 3;
+	else if (fuse == 127)
+		return 4;
+
+	return UINT_MAX;
+}
+
 static u32 a618_get_speed_bin(u32 fuse)
 {
 	if (fuse == 0)
@@ -2175,6 +2199,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 {
 	u32 val = UINT_MAX;
 
+	if (adreno_cmp_rev(ADRENO_REV(6, 1, 0, ANY_ID), rev))
+		val = a610_get_speed_bin(fuse);
+
 	if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
 		val = a618_get_speed_bin(fuse);
 
-- 
2.39.1


  parent reply	other threads:[~2023-01-26 15:19 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-26 15:16 [PATCH 00/14] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio
2023-01-26 15:16 ` [PATCH 01/14] drm/msm/a6xx: De-staticize sptprac en/disable functions Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 02/14] drm/msm/a6xx: Extend UBWC config Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-02-01  9:30   ` Akhil P Oommen
2023-02-01  9:30     ` Akhil P Oommen
2023-02-01 10:51     ` Konrad Dybcio
2023-02-01 10:51       ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 03/14] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 04/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-02-06 18:30   ` Konrad Dybcio
2023-02-06 18:30     ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 07/14] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 08/14] drm/msm/a6xx: Add A610 support Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 09/14] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-02-08 18:21   ` [Freedreno] " Jordan Crouse
2023-02-08 18:21     ` Jordan Crouse
2023-02-14 11:25     ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 10/14] drm/msm/a6xx: Fix up A6XX protected registers Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 11/14] drm/msm/a6xx: Enable optional icc voting from OPP tables Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 12/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-26 15:16 ` [PATCH 13/14] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio
2023-01-26 15:16   ` Konrad Dybcio
2023-01-27 14:19   ` Dmitry Baryshkov
2023-01-27 14:19     ` Dmitry Baryshkov
2023-01-27 14:20     ` Konrad Dybcio
2023-01-27 14:20       ` Konrad Dybcio
2023-01-27 14:22     ` Konrad Dybcio
2023-01-27 14:22       ` Konrad Dybcio
2023-01-26 15:16 ` Konrad Dybcio [this message]
2023-01-26 15:16   ` [PATCH 14/14] drm/msm/a6xx: Add A610 " Konrad Dybcio

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