From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Cc: Fei Yang <fei.yang@intel.com>, dri-devel@lists.freedesktop.org Subject: [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl Date: Sun, 16 Apr 2023 23:25:00 -0700 [thread overview] Message-ID: <20230417062503.1884465-6-fei.yang@intel.com> (raw) In-Reply-To: <20230417062503.1884465-1-fei.yang@intel.com> From: Fei Yang <fei.yang@intel.com> The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. Signed-off-by: Fei Yang <fei.yang@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index d2d5a24301b2..bb3575b1479f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -337,6 +337,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..e602c323896b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snooping CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: fei.yang@intel.com To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl Date: Sun, 16 Apr 2023 23:25:00 -0700 [thread overview] Message-ID: <20230417062503.1884465-6-fei.yang@intel.com> (raw) In-Reply-To: <20230417062503.1884465-1-fei.yang@intel.com> From: Fei Yang <fei.yang@intel.com> The design is to keep Buffer Object's caching policy immutable through out its life cycle. This patch ends the support for set caching ioctl from MTL onward. While doing that we also set BO's to be 1-way coherent at creation time because GPU is no longer automatically snooping CPU cache. Signed-off-by: Fei Yang <fei.yang@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index d2d5a24301b2..bb3575b1479f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -337,6 +337,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, if (IS_DGFX(i915)) return -ENODEV; + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + return -EOPNOTSUPP; + switch (args->caching) { case I915_CACHING_NONE: level = I915_CACHE_NONE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 37d1efcd3ca6..e602c323896b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem, obj->write_domain = I915_GEM_DOMAIN_CPU; obj->read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(i915)) + /* + * MTL doesn't snooping CPU cache by default for GPU access (namely + * 1-way coherency). However some UMD's are currently depending on + * that. Make 1-way coherent the default setting for MTL. A follow + * up patch will extend the GEM_CREATE uAPI to allow UMD's specify + * caching mode at BO creation time + */ + if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than -- 2.25.1
next prev parent reply other threads:[~2023-04-17 6:24 UTC|newest] Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-17 6:24 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-17 6:24 ` [Intel-gfx] " fei.yang 2023-04-17 6:24 ` [PATCH 1/8] drm/i915/mtl: Set has_llc=0 fei.yang 2023-04-17 6:24 ` [Intel-gfx] " fei.yang 2023-04-19 10:59 ` Andi Shyti 2023-04-19 12:50 ` Andrzej Hajda 2023-04-19 14:10 ` Das, Nirmoy 2023-04-17 6:24 ` [PATCH 2/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-17 6:24 ` [Intel-gfx] " fei.yang 2023-04-19 11:01 ` Andi Shyti 2023-04-19 16:00 ` Yang, Fei 2023-04-19 16:00 ` Yang, Fei 2023-04-19 13:59 ` Andrzej Hajda 2023-04-19 16:03 ` Yang, Fei 2023-04-19 16:03 ` Yang, Fei 2023-04-19 14:36 ` Das, Nirmoy 2023-04-19 16:05 ` Yang, Fei 2023-04-19 16:05 ` Yang, Fei 2023-04-17 6:24 ` [PATCH 3/8] drm/i915/mtl: Add PTE encode function fei.yang 2023-04-17 6:24 ` [Intel-gfx] " fei.yang 2023-04-19 11:02 ` Andi Shyti 2023-04-19 12:51 ` Andrzej Hajda 2023-04-19 15:11 ` Das, Nirmoy 2023-04-19 15:11 ` [Intel-gfx] " Das, Nirmoy 2023-04-17 6:24 ` [PATCH 4/8] drm/i915/mtl: workaround coherency issue for Media fei.yang 2023-04-17 6:24 ` [Intel-gfx] " fei.yang 2023-04-19 10:59 ` Andi Shyti 2023-04-19 12:38 ` Andi Shyti 2023-04-19 15:14 ` Das, Nirmoy 2023-04-19 15:14 ` [Intel-gfx] " Das, Nirmoy 2023-04-19 15:40 ` Andrzej Hajda 2023-04-19 16:37 ` Yang, Fei 2023-04-19 16:37 ` Yang, Fei 2023-04-19 18:49 ` Yang, Fei 2023-04-19 18:49 ` Yang, Fei 2023-04-17 6:25 ` fei.yang [this message] 2023-04-17 6:25 ` [Intel-gfx] [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang 2023-04-19 11:08 ` Andi Shyti 2023-04-19 13:05 ` Andrzej Hajda 2023-04-19 16:56 ` Yang, Fei 2023-04-19 16:56 ` Yang, Fei 2023-04-17 6:25 ` [PATCH 6/8] drm/i915: preparation for using PAT index fei.yang 2023-04-17 6:25 ` [Intel-gfx] " fei.yang 2023-04-19 11:17 ` Andi Shyti 2023-04-19 11:17 ` [Intel-gfx] " Andi Shyti 2023-04-17 6:25 ` [PATCH 7/8] drm/i915: use pat_index instead of cache_level fei.yang 2023-04-17 6:25 ` [Intel-gfx] " fei.yang 2023-04-19 12:16 ` Andi Shyti 2023-04-17 6:25 ` [PATCH 8/8] drm/i915: Allow user to set cache at BO creation fei.yang 2023-04-17 6:25 ` [Intel-gfx] " fei.yang 2023-04-19 12:23 ` Andi Shyti 2023-04-19 12:23 ` [Intel-gfx] " Andi Shyti 2023-04-17 6:32 ` [Intel-gfx] [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL Timo Aaltonen 2023-04-17 6:43 ` Yang, Fei 2023-04-17 6:43 ` Yang, Fei 2023-04-24 20:00 ` Jordan Justen 2023-04-24 20:00 ` Jordan Justen 2023-04-17 11:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL (rev5) Patchwork 2023-04-17 11:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2023-04-17 12:15 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2023-04-19 18:09 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-19 18:09 ` [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang 2023-04-19 21:12 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-19 21:12 ` [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang 2023-04-19 23:00 [PATCH 0/8] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang 2023-04-19 23:00 ` [PATCH 5/8] drm/i915/mtl: end support for set caching ioctl fei.yang
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