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From: Andrew Davis <afd@ti.com>
To: "Frank Binns" <frank.binns@imgtec.com>,
	"Donald Robson" <donald.robson@imgtec.com>,
	"Matt Coster" <matt.coster@imgtec.com>,
	"H . Nikolaus Schaller" <hns@goldelico.com>,
	"Adam Ford" <aford173@gmail.com>,
	"Ivaylo Dimitrov" <ivo.g.dimitrov.75@gmail.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Benoît Cousson" <bcousson@baylibre.com>,
	"Tony Lindgren" <tony@atomide.com>, "Nishanth Menon" <nm@ti.com>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	"Tero Kristo" <kristo@kernel.org>,
	"Paul Cercueil" <paul@crapouillou.net>
Cc: <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-sunxi@lists.linux.dev>, <linux-omap@vger.kernel.org>,
	<linux-mips@vger.kernel.org>, Andrew Davis <afd@ti.com>
Subject: [PATCH RFC v2 02/11] dt-bindings: gpu: Add PowerVR Series5 SGX GPUs
Date: Mon, 8 Jan 2024 12:32:53 -0600	[thread overview]
Message-ID: <20240108183302.255055-3-afd@ti.com> (raw)
In-Reply-To: <20240108183302.255055-1-afd@ti.com>

The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
multiple vendors. Describe how the SGX GPU is integrated in these SoC,
including register space and interrupts. Clocks, reset, and power domain
information is SoC specific.

Signed-off-by: Andrew Davis <afd@ti.com>
---
 .../bindings/gpu/img,powervr-sgx.yaml         | 124 ++++++++++++++++++
 MAINTAINERS                                   |   1 +
 2 files changed, 125 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml

diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
new file mode 100644
index 0000000000000..bb821e1184de9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Imagination Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR SGX GPUs
+
+maintainers:
+  - Frank Binns <frank.binns@imgtec.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - ti,omap3430-gpu # Rev 121
+              - ti,omap3630-gpu # Rev 125
+          - const: img,powervr-sgx530
+      - items:
+          - enum:
+              - ingenic,jz4780-gpu # Rev 130
+              - ti,omap4430-gpu # Rev 120
+          - const: img,powervr-sgx540
+      - items:
+          - enum:
+              - allwinner,sun6i-a31-gpu # MP2 Rev 115
+              - ti,omap4470-gpu # MP1 Rev 112
+              - ti,omap5432-gpu # MP2 Rev 105
+              - ti,am5728-gpu # MP2 Rev 116
+              - ti,am6548-gpu # MP1 Rev 117
+          - const: img,powervr-sgx544
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks: true
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: core
+      - const: mem
+      - const: sys
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am6548-gpu
+    then:
+      required:
+        - power-domains
+    else:
+      properties:
+        power-domains: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - allwinner,sun6i-a31-gpu
+              - ingenic,jz4780-gpu
+    then:
+      allOf:
+        - if:
+            properties:
+              compatible:
+                contains:
+                  const: allwinner,sun6i-a31-gpu
+          then:
+            properties:
+              clocks:
+                minItems: 2
+                maxItems: 2
+              clock-names:
+                minItems: 2
+                maxItems: 2
+        - if:
+            properties:
+              compatible:
+                contains:
+                  const: ingenic,jz4780-gpu
+          then:
+            properties:
+              clocks:
+                maxItems: 1
+              clock-names:
+                maxItems: 1
+      required:
+        - clocks
+        - clock-names
+    else:
+      properties:
+        clocks: false
+        clock-names: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    gpu@7000000 {
+        compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+        reg = <0x7000000 0x10000>;
+        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+        power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b205795da04e..00ba13e019fa6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10462,6 +10462,7 @@ M:	Matt Coster <matt.coster@imgtec.com>
 S:	Supported
 T:	git git://anongit.freedesktop.org/drm/drm-misc
 F:	Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+F:	Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
 F:	Documentation/gpu/imagination/
 F:	drivers/gpu/drm/imagination/
 F:	include/uapi/drm/pvr_drm.h
-- 
2.39.2


WARNING: multiple messages have this Message-ID (diff)
From: Andrew Davis <afd@ti.com>
To: "Frank Binns" <frank.binns@imgtec.com>,
	"Donald Robson" <donald.robson@imgtec.com>,
	"Matt Coster" <matt.coster@imgtec.com>,
	"H . Nikolaus Schaller" <hns@goldelico.com>,
	"Adam Ford" <aford173@gmail.com>,
	"Ivaylo Dimitrov" <ivo.g.dimitrov.75@gmail.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Benoît Cousson" <bcousson@baylibre.com>,
	"Tony Lindgren" <tony@atomide.com>, "Nishanth Menon" <nm@ti.com>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	"Tero Kristo" <kristo@kernel.org>,
	"Paul Cercueil" <paul@crapouillou.net>
Cc: <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-sunxi@lists.linux.dev>, <linux-omap@vger.kernel.org>,
	<linux-mips@vger.kernel.org>, Andrew Davis <afd@ti.com>
Subject: [PATCH RFC v2 02/11] dt-bindings: gpu: Add PowerVR Series5 SGX GPUs
Date: Mon, 8 Jan 2024 12:32:53 -0600	[thread overview]
Message-ID: <20240108183302.255055-3-afd@ti.com> (raw)
In-Reply-To: <20240108183302.255055-1-afd@ti.com>

The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
multiple vendors. Describe how the SGX GPU is integrated in these SoC,
including register space and interrupts. Clocks, reset, and power domain
information is SoC specific.

Signed-off-by: Andrew Davis <afd@ti.com>
---
 .../bindings/gpu/img,powervr-sgx.yaml         | 124 ++++++++++++++++++
 MAINTAINERS                                   |   1 +
 2 files changed, 125 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml

diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
new file mode 100644
index 0000000000000..bb821e1184de9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Imagination Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR SGX GPUs
+
+maintainers:
+  - Frank Binns <frank.binns@imgtec.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - ti,omap3430-gpu # Rev 121
+              - ti,omap3630-gpu # Rev 125
+          - const: img,powervr-sgx530
+      - items:
+          - enum:
+              - ingenic,jz4780-gpu # Rev 130
+              - ti,omap4430-gpu # Rev 120
+          - const: img,powervr-sgx540
+      - items:
+          - enum:
+              - allwinner,sun6i-a31-gpu # MP2 Rev 115
+              - ti,omap4470-gpu # MP1 Rev 112
+              - ti,omap5432-gpu # MP2 Rev 105
+              - ti,am5728-gpu # MP2 Rev 116
+              - ti,am6548-gpu # MP1 Rev 117
+          - const: img,powervr-sgx544
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks: true
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: core
+      - const: mem
+      - const: sys
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am6548-gpu
+    then:
+      required:
+        - power-domains
+    else:
+      properties:
+        power-domains: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - allwinner,sun6i-a31-gpu
+              - ingenic,jz4780-gpu
+    then:
+      allOf:
+        - if:
+            properties:
+              compatible:
+                contains:
+                  const: allwinner,sun6i-a31-gpu
+          then:
+            properties:
+              clocks:
+                minItems: 2
+                maxItems: 2
+              clock-names:
+                minItems: 2
+                maxItems: 2
+        - if:
+            properties:
+              compatible:
+                contains:
+                  const: ingenic,jz4780-gpu
+          then:
+            properties:
+              clocks:
+                maxItems: 1
+              clock-names:
+                maxItems: 1
+      required:
+        - clocks
+        - clock-names
+    else:
+      properties:
+        clocks: false
+        clock-names: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    gpu@7000000 {
+        compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+        reg = <0x7000000 0x10000>;
+        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+        power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b205795da04e..00ba13e019fa6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10462,6 +10462,7 @@ M:	Matt Coster <matt.coster@imgtec.com>
 S:	Supported
 T:	git git://anongit.freedesktop.org/drm/drm-misc
 F:	Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+F:	Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
 F:	Documentation/gpu/imagination/
 F:	drivers/gpu/drm/imagination/
 F:	include/uapi/drm/pvr_drm.h
-- 
2.39.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Davis <afd@ti.com>
To: "Frank Binns" <frank.binns@imgtec.com>,
	"Donald Robson" <donald.robson@imgtec.com>,
	"Matt Coster" <matt.coster@imgtec.com>,
	"H . Nikolaus Schaller" <hns@goldelico.com>,
	"Adam Ford" <aford173@gmail.com>,
	"Ivaylo Dimitrov" <ivo.g.dimitrov.75@gmail.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Samuel Holland" <samuel@sholland.org>,
	"Benoît Cousson" <bcousson@baylibre.com>,
	"Tony Lindgren" <tony@atomide.com>, "Nishanth Menon" <nm@ti.com>,
	"Vignesh Raghavendra" <vigneshr@ti.com>,
	"Tero Kristo" <kristo@kernel.org>,
	"Paul Cercueil" <paul@crapouillou.net>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-mips@vger.kernel.org,
	Andrew Davis <afd@ti.com>,
	linux-omap@vger.kernel.org, linux-sunxi@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC v2 02/11] dt-bindings: gpu: Add PowerVR Series5 SGX GPUs
Date: Mon, 8 Jan 2024 12:32:53 -0600	[thread overview]
Message-ID: <20240108183302.255055-3-afd@ti.com> (raw)
In-Reply-To: <20240108183302.255055-1-afd@ti.com>

The Imagination PowerVR Series5 "SGX" GPU is part of several SoCs from
multiple vendors. Describe how the SGX GPU is integrated in these SoC,
including register space and interrupts. Clocks, reset, and power domain
information is SoC specific.

Signed-off-by: Andrew Davis <afd@ti.com>
---
 .../bindings/gpu/img,powervr-sgx.yaml         | 124 ++++++++++++++++++
 MAINTAINERS                                   |   1 +
 2 files changed, 125 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml

diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
new file mode 100644
index 0000000000000..bb821e1184de9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Imagination Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR SGX GPUs
+
+maintainers:
+  - Frank Binns <frank.binns@imgtec.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - ti,omap3430-gpu # Rev 121
+              - ti,omap3630-gpu # Rev 125
+          - const: img,powervr-sgx530
+      - items:
+          - enum:
+              - ingenic,jz4780-gpu # Rev 130
+              - ti,omap4430-gpu # Rev 120
+          - const: img,powervr-sgx540
+      - items:
+          - enum:
+              - allwinner,sun6i-a31-gpu # MP2 Rev 115
+              - ti,omap4470-gpu # MP1 Rev 112
+              - ti,omap5432-gpu # MP2 Rev 105
+              - ti,am5728-gpu # MP2 Rev 116
+              - ti,am6548-gpu # MP1 Rev 117
+          - const: img,powervr-sgx544
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks: true
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: core
+      - const: mem
+      - const: sys
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am6548-gpu
+    then:
+      required:
+        - power-domains
+    else:
+      properties:
+        power-domains: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - allwinner,sun6i-a31-gpu
+              - ingenic,jz4780-gpu
+    then:
+      allOf:
+        - if:
+            properties:
+              compatible:
+                contains:
+                  const: allwinner,sun6i-a31-gpu
+          then:
+            properties:
+              clocks:
+                minItems: 2
+                maxItems: 2
+              clock-names:
+                minItems: 2
+                maxItems: 2
+        - if:
+            properties:
+              compatible:
+                contains:
+                  const: ingenic,jz4780-gpu
+          then:
+            properties:
+              clocks:
+                maxItems: 1
+              clock-names:
+                maxItems: 1
+      required:
+        - clocks
+        - clock-names
+    else:
+      properties:
+        clocks: false
+        clock-names: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    gpu@7000000 {
+        compatible = "ti,am6548-gpu", "img,powervr-sgx544";
+        reg = <0x7000000 0x10000>;
+        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+        power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b205795da04e..00ba13e019fa6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10462,6 +10462,7 @@ M:	Matt Coster <matt.coster@imgtec.com>
 S:	Supported
 T:	git git://anongit.freedesktop.org/drm/drm-misc
 F:	Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+F:	Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
 F:	Documentation/gpu/imagination/
 F:	drivers/gpu/drm/imagination/
 F:	include/uapi/drm/pvr_drm.h
-- 
2.39.2


  parent reply	other threads:[~2024-01-08 18:33 UTC|newest]

Thread overview: 93+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-08 18:32 [PATCH RFC v2 00/11] Device tree support for Imagination Series5 GPU Andrew Davis
2024-01-08 18:32 ` Andrew Davis
2024-01-08 18:32 ` Andrew Davis
2024-01-08 18:32 ` [PATCH RFC v2 01/11] dt-bindings: gpu: Rename img,powervr to img,powervr-rogue Andrew Davis
2024-01-08 18:32   ` [PATCH RFC v2 01/11] dt-bindings: gpu: Rename img, powervr to img, powervr-rogue Andrew Davis
2024-01-08 18:32   ` [PATCH RFC v2 01/11] dt-bindings: gpu: Rename img,powervr to img,powervr-rogue Andrew Davis
2024-01-09  8:14   ` [PATCH RFC v2 01/11] dt-bindings: gpu: Rename img, powervr to img, powervr-rogue Javier Martinez Canillas
2024-01-09  8:14     ` Javier Martinez Canillas
2024-01-09  8:14     ` Javier Martinez Canillas
2024-01-09  9:40   ` [PATCH RFC v2 01/11] dt-bindings: gpu: Rename img,powervr to img,powervr-rogue Frank Binns
2024-01-09  9:40     ` Frank Binns
2024-01-09  9:40     ` Frank Binns
2024-01-09 11:28   ` Krzysztof Kozlowski
2024-01-09 11:28     ` Krzysztof Kozlowski
2024-01-09 11:28     ` Krzysztof Kozlowski
2024-01-09 16:14     ` Andrew Davis
2024-01-09 16:14       ` Andrew Davis
2024-01-09 16:14       ` Andrew Davis
2024-01-09 18:55       ` Krzysztof Kozlowski
2024-01-09 18:55         ` Krzysztof Kozlowski
2024-01-09 18:55         ` Krzysztof Kozlowski
2024-01-08 18:32 ` Andrew Davis [this message]
2024-01-08 18:32   ` [PATCH RFC v2 02/11] dt-bindings: gpu: Add PowerVR Series5 SGX GPUs Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09 11:32   ` Krzysztof Kozlowski
2024-01-09 11:32     ` Krzysztof Kozlowski
2024-01-09 11:32     ` Krzysztof Kozlowski
2024-01-09 16:53     ` Andrew Davis
2024-01-09 16:53       ` Andrew Davis
2024-01-09 16:53       ` Andrew Davis
2024-01-09 18:58       ` Krzysztof Kozlowski
2024-01-09 18:58         ` Krzysztof Kozlowski
2024-01-09 18:58         ` Krzysztof Kozlowski
2024-01-08 18:32 ` [PATCH RFC v2 03/11] ARM: dts: omap3: Add device tree entry for SGX GPU Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09  8:17   ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-08 18:32 ` [PATCH RFC v2 04/11] ARM: dts: omap4: " Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09  8:17   ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-12 17:33   ` H. Nikolaus Schaller
2024-01-12 17:33     ` H. Nikolaus Schaller
2024-01-12 17:33     ` H. Nikolaus Schaller
2024-01-15  8:25     ` Maxime Ripard
2024-01-15  8:25       ` Maxime Ripard
2024-01-15  8:25       ` Maxime Ripard
2024-01-15  8:55       ` H. Nikolaus Schaller
2024-01-15  8:55         ` H. Nikolaus Schaller
2024-01-15  8:55         ` H. Nikolaus Schaller
2024-01-15  9:50         ` Andreas Kemnade
2024-01-15  9:50           ` Andreas Kemnade
2024-01-15  9:50           ` Andreas Kemnade
2024-01-15 14:45         ` Maxime Ripard
2024-01-15 14:45           ` Maxime Ripard
2024-01-15 14:45           ` Maxime Ripard
2024-01-08 18:32 ` [PATCH RFC v2 05/11] ARM: dts: omap5: " Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09  8:17   ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-08 18:32 ` [PATCH RFC v2 06/11] ARM: dts: AM33xx: " Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09  8:17   ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-09  8:17     ` Javier Martinez Canillas
2024-01-08 18:32 ` [PATCH RFC v2 07/11] ARM: dts: AM437x: " Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09  8:18   ` Javier Martinez Canillas
2024-01-09  8:18     ` Javier Martinez Canillas
2024-01-09  8:18     ` Javier Martinez Canillas
2024-01-08 18:32 ` [PATCH RFC v2 08/11] ARM: dts: DRA7xx: " Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-08 18:32   ` Andrew Davis
2024-01-09  8:18   ` Javier Martinez Canillas
2024-01-09  8:18     ` Javier Martinez Canillas
2024-01-09  8:18     ` Javier Martinez Canillas
2024-01-08 18:33 ` [PATCH RFC v2 09/11] arm64: dts: ti: k3-am654-main: " Andrew Davis
2024-01-08 18:33   ` Andrew Davis
2024-01-08 18:33   ` Andrew Davis
2024-01-08 18:33 ` [PATCH RFC v2 10/11] ARM: dts: sun6i: " Andrew Davis
2024-01-08 18:33   ` Andrew Davis
2024-01-08 18:33   ` Andrew Davis
2024-01-08 18:33 ` [PATCH RFC v2 11/11] MIPS: DTS: jz4780: " Andrew Davis
2024-01-08 18:33   ` Andrew Davis
2024-01-08 18:33   ` Andrew Davis

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