From: Joshua Yeong <joshua.yeong@starfivetech.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, geert+renesas@glider.be, joshua.yeong@starfivetech.com, prabhakar.mahadev-lad.rj@bp.renesas.com, conor.dooley@microchip.com, alexghiti@rivosinc.com, evan@rivosinc.com, ajones@ventanamicro.com, heiko@sntech.de, guoren@kernel.org, uwu@icenowy.me, jszhang@kernel.org, conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, leyfoon.tan@starfivetech.com, jeeheng.sia@starfivetech.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] dt-bindings: cache: Add docs for StarFive StarLink-500 cache controller Date: Thu, 14 Mar 2024 14:12:05 +0800 [thread overview] Message-ID: <20240314061205.26143-5-joshua.yeong@starfivetech.com> (raw) In-Reply-To: <20240314061205.26143-1-joshua.yeong@starfivetech.com> Add DT binding documentation used by StarFive's Starlink-500 cache controller. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> --- .../cache/starfive,starlink-500-cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml new file mode 100644 index 000000000000..97ddf7db39e9 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive StarLink-500 Cache Controller + +maintainers: + - Joshua Yeong <joshua.yeong@starfivetech.com> + +description: + StarFive's StarLink-500 controller manages cache shared between clusters of + CPU cores. The cache driver provides mechanism to perform invalidate and write + back functionality to the shared memory. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +# We need a select here so we don't match all nodes with 'cache' +select: + properties: + compatible: + contains: + enum: + - starfive,starlink-500-cache + + required: + - compatible + +properties: + compatible: + items: + - const: starfive,starlink-500-cache + - const: cache + + reg: + maxItems: 1 + + cache-size: true + cache-sets: true + cache-block-size: true + cache-level: true + cache-unified: true + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + cache-controller@15000000 { + compatible = "starfive,starlink-500-cache", "cache"; + reg = <0x15000000 0x278>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Joshua Yeong <joshua.yeong@starfivetech.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, geert+renesas@glider.be, joshua.yeong@starfivetech.com, prabhakar.mahadev-lad.rj@bp.renesas.com, conor.dooley@microchip.com, alexghiti@rivosinc.com, evan@rivosinc.com, ajones@ventanamicro.com, heiko@sntech.de, guoren@kernel.org, uwu@icenowy.me, jszhang@kernel.org, conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, leyfoon.tan@starfivetech.com, jeeheng.sia@starfivetech.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] dt-bindings: cache: Add docs for StarFive StarLink-500 cache controller Date: Thu, 14 Mar 2024 14:12:05 +0800 [thread overview] Message-ID: <20240314061205.26143-5-joshua.yeong@starfivetech.com> (raw) In-Reply-To: <20240314061205.26143-1-joshua.yeong@starfivetech.com> Add DT binding documentation used by StarFive's Starlink-500 cache controller. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> --- .../cache/starfive,starlink-500-cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml new file mode 100644 index 000000000000..97ddf7db39e9 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive StarLink-500 Cache Controller + +maintainers: + - Joshua Yeong <joshua.yeong@starfivetech.com> + +description: + StarFive's StarLink-500 controller manages cache shared between clusters of + CPU cores. The cache driver provides mechanism to perform invalidate and write + back functionality to the shared memory. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +# We need a select here so we don't match all nodes with 'cache' +select: + properties: + compatible: + contains: + enum: + - starfive,starlink-500-cache + + required: + - compatible + +properties: + compatible: + items: + - const: starfive,starlink-500-cache + - const: cache + + reg: + maxItems: 1 + + cache-size: true + cache-sets: true + cache-block-size: true + cache-level: true + cache-unified: true + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + cache-controller@15000000 { + compatible = "starfive,starlink-500-cache", "cache"; + reg = <0x15000000 0x278>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; -- 2.25.1
next prev parent reply other threads:[~2024-03-14 6:13 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-14 6:12 [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller Joshua Yeong 2024-03-14 6:12 ` Joshua Yeong 2024-03-14 6:12 ` [PATCH 1/4] riscv: asm: vendorid_list: Add StarFive Technology to vendors list Joshua Yeong 2024-03-14 6:12 ` Joshua Yeong 2024-03-14 6:12 ` [PATCH 2/4] riscv: errata: Add StarFive alternative ports Joshua Yeong 2024-03-14 6:12 ` Joshua Yeong 2024-03-15 23:13 ` Samuel Holland 2024-03-15 23:13 ` Samuel Holland 2024-03-17 15:04 ` Conor Dooley 2024-03-17 15:04 ` Conor Dooley 2024-03-14 6:12 ` [PATCH 3/4] cache: Add StarLink-500 cache management for StarFive JH8100 RISC-V core Joshua Yeong 2024-03-14 6:12 ` Joshua Yeong 2024-03-15 8:22 ` kernel test robot 2024-03-15 8:22 ` kernel test robot 2024-03-15 23:33 ` Samuel Holland 2024-03-15 23:33 ` Samuel Holland 2024-03-14 6:12 ` Joshua Yeong [this message] 2024-03-14 6:12 ` [PATCH 4/4] dt-bindings: cache: Add docs for StarFive StarLink-500 cache controller Joshua Yeong 2024-03-15 16:36 ` Rob Herring 2024-03-15 16:36 ` Rob Herring 2024-03-17 14:58 ` Conor Dooley 2024-03-17 14:58 ` Conor Dooley 2024-03-17 15:01 ` [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller Conor Dooley 2024-03-17 15:01 ` Conor Dooley 2024-03-20 8:08 ` Conor Dooley 2024-03-20 8:08 ` Conor Dooley 2024-03-22 6:16 ` Joshua Yeong 2024-03-22 6:16 ` Joshua Yeong
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