From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Subject: [Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Date: Tue, 30 Jul 2019 16:35:16 -0700 [thread overview] Message-ID: <cover.1564529681.git.alistair.francis@wdc.com> (raw) The first three patches are ones that I have pulled out of my original Hypervisor series at an attempt to reduce the number of patches in the series. These three patches all make sense without the Hypervisor series so can be merged seperatley and will reduce the review burden of the next version of the patches. The fource patch is a prep patch for the new v0.4 Hypervisor spec. The final patch is unreleated to Hypervisor that I'm just slipping in here because it seems easier then sending it by itself. v2: - Small corrections based on feedback - Remove the CSR permission check patch Alistair Francis (4): target/riscv: Don't set write permissions on dirty PTEs riscv: plic: Remove unused interrupt functions target/riscv: Create function to test if FP is enabled target/riscv: Update the Hypervisor CSRs to v0.4 Atish Patra (1): target/riscv: Fix Floating Point register names hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_bits.h | 35 +++++++++++++++++----------------- target/riscv/cpu_helper.c | 16 ++++++++++++---- target/riscv/csr.c | 20 ++++++++++--------- 7 files changed, 50 insertions(+), 50 deletions(-) -- 2.22.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [Qemu-riscv] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Date: Tue, 30 Jul 2019 16:35:16 -0700 [thread overview] Message-ID: <cover.1564529681.git.alistair.francis@wdc.com> (raw) The first three patches are ones that I have pulled out of my original Hypervisor series at an attempt to reduce the number of patches in the series. These three patches all make sense without the Hypervisor series so can be merged seperatley and will reduce the review burden of the next version of the patches. The fource patch is a prep patch for the new v0.4 Hypervisor spec. The final patch is unreleated to Hypervisor that I'm just slipping in here because it seems easier then sending it by itself. v2: - Small corrections based on feedback - Remove the CSR permission check patch Alistair Francis (4): target/riscv: Don't set write permissions on dirty PTEs riscv: plic: Remove unused interrupt functions target/riscv: Create function to test if FP is enabled target/riscv: Update the Hypervisor CSRs to v0.4 Atish Patra (1): target/riscv: Fix Floating Point register names hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_bits.h | 35 +++++++++++++++++----------------- target/riscv/cpu_helper.c | 16 ++++++++++++---- target/riscv/csr.c | 20 ++++++++++--------- 7 files changed, 50 insertions(+), 50 deletions(-) -- 2.22.0
next reply other threads:[~2019-07-30 23:41 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-30 23:35 Alistair Francis [this message] 2019-07-30 23:35 ` [Qemu-riscv] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 Alistair Francis 2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis 2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis 2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 2/5] riscv: plic: Remove unused interrupt functions Alistair Francis 2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis 2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled Alistair Francis 2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis 2019-08-05 6:59 ` [Qemu-devel] " Chih-Min Chao 2019-08-05 6:59 ` [Qemu-riscv] " Chih-Min Chao 2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4 Alistair Francis 2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis 2019-08-05 6:19 ` [Qemu-devel] " Chih-Min Chao 2019-08-05 6:19 ` [Qemu-riscv] " Chih-Min Chao 2019-07-30 23:35 ` [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names Alistair Francis 2019-07-30 23:35 ` [Qemu-riscv] " Alistair Francis 2019-08-12 23:08 ` [Qemu-devel] " Palmer Dabbelt 2019-08-12 23:08 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-13 17:06 ` [Qemu-devel] " Alistair Francis 2019-08-13 17:06 ` [Qemu-riscv] " Alistair Francis 2019-08-14 18:07 ` [Qemu-devel] " Palmer Dabbelt 2019-08-14 18:07 ` [Qemu-riscv] " Palmer Dabbelt
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