From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <jagan@amarulasolutions.com>, <vigneshr@ti.com>, <p.yadav@ti.com>
Cc: <u-boot@lists.denx.de>, <nicolas.ferre@microchip.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: [PATCH v2 1/4] mtd: spi-nor-core: Introduce SPI_NOR_SOFT_RESET flash_info flag
Date: Thu, 4 Nov 2021 01:49:47 +0200 [thread overview]
Message-ID: <20211103234950.202289-2-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20211103234950.202289-1-tudor.ambarus@microchip.com>
Some flashes can determine if Soft Reset is supported by parsing
BFPT_DWORD(16). There are however flashes that do not define any of
the SFDP tables, so they can't discover this capability at SFDP
parsing time. For such cases introduce the SPI_NOR_SOFT_RESET
flash_info flag to be able to specify statically this support.
This flag must be used together with the SPI_NOR_SKIP_SFDP flag.
For flashes that support Soft Reset and define BFPT, but have
the BFPT_DWORD(16) missing or with a wrong value, a post_sfdp()
fixup hook should be used instead, where SNOR_F_SOFT_RESET should
be set.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi/sf_internal.h | 5 +++++
drivers/mtd/spi/spi-nor-core.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d3ef69ec74..9a16e07bc4 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -69,6 +69,11 @@ struct flash_info {
#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
+#define SPI_NOR_SOFT_RESET BIT(18) /*
+ * Used by flashes that do not define
+ * any SFDP tables, i.e. in conjunction
+ * with SPI_NOR_SKIP_SFDP.
+ */
};
extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 4388a08a90..ce1ecae899 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3813,6 +3813,9 @@ int spi_nor_scan(struct spi_nor *nor)
if (info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE;
+ if (info->flags & SPI_NOR_SOFT_RESET)
+ nor->flags |= SNOR_F_SOFT_RESET;
+
nor->page_size = params.page_size;
mtd->writebufsize = nor->page_size;
--
2.25.1
next prev parent reply other threads:[~2021-11-03 23:50 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-03 23:49 [PATCH v2 0/4] mtd: spi-nor: Fix software reset; add mx66lm1g45g Tudor Ambarus
2021-11-03 23:49 ` Tudor Ambarus [this message]
2021-11-09 19:31 ` [PATCH v2 1/4] mtd: spi-nor-core: Introduce SPI_NOR_SOFT_RESET flash_info flag Pratyush Yadav
2021-11-03 23:49 ` [PATCH v2 2/4] mtd: spi-nor-core: macronix: Add support for mx66lm1g45g Tudor Ambarus
2021-11-12 21:50 ` Pratyush Yadav
2021-11-13 13:48 ` Jagan Teki
2021-11-15 5:25 ` Tudor.Ambarus
2021-11-03 23:49 ` [PATCH v2 3/4] Revert "mtd: spi-nor-core: Perform a Soft Reset on boot" Tudor Ambarus
2021-11-09 19:26 ` Pratyush Yadav
2021-11-10 8:44 ` Tudor.Ambarus
2021-11-12 13:13 ` Pratyush Yadav
2021-11-15 5:44 ` Tudor.Ambarus
2021-12-16 18:45 ` Pratyush Yadav
2021-12-17 6:27 ` Tudor.Ambarus
2021-12-17 10:40 ` Pratyush Yadav
2021-11-03 23:49 ` [PATCH v2 4/4] mtd: spi-nor-core: Fix the opcode extension for the software reset sequence Tudor Ambarus
2021-11-09 19:29 ` Pratyush Yadav
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