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From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <jagan@amarulasolutions.com>, <vigneshr@ti.com>, <p.yadav@ti.com>
Cc: <u-boot@lists.denx.de>, <nicolas.ferre@microchip.com>,
	Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: [PATCH v2 3/4] Revert "mtd: spi-nor-core: Perform a Soft Reset on boot"
Date: Thu, 4 Nov 2021 01:49:49 +0200	[thread overview]
Message-ID: <20211103234950.202289-4-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20211103234950.202289-1-tudor.ambarus@microchip.com>

This reverts commit 0be8ab1f166844d53477387dc9a1184161ef44ef.

There are multiple reset commands and it was used one at guess,
see BFPT[dword(16)]. It is preferable to avoid issuing unsupported
commands to a flash. Since there's no config in mainline that actually
uses SPI_FLASH_SOFT_RESET_ON_BOOT, remove it entirely until proper
support is added. One should instead determine the mode in which the
flash device is configured, then to parse SFDP to determine the
cmd_ext_type and then to issue a READID command if flash identification
is really a must. JESD216D-01 proposes an algorithm to try to read the
SFDP signature to determine the mode in which the flash is configured:
'''
try to read the SFDP signature (see 6.1) in 4-4-4 mode, if that fails
try 2-2-2 mode, and if that fails try 1-1-1 mode. For Octal devices,
these typically support SFDP read operation in both 1S-1S-1S mode and
8D-8D-8D mode. If the host controller does not know exactly which
protocol mode is used for SFDP in 8D-8D-8D mode, this information can be
found by reading SFDP in 1S-1S-1S mode first. (To read an unknown device
directly in 8D-8D-8D mode, the host controller may read from address 0,
and count the number of dummy clocks required before the SFDP signature
is received.)
'''
If the flash does not support SFDP at all, one should introduce dedicated
configs for each reset type and issue just the needed reset command.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi/Kconfig        |  9 ---------
 drivers/mtd/spi/spi-nor-core.c | 27 ---------------------------
 2 files changed, 36 deletions(-)

diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 2d2b71c52d..14800b5e93 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -103,15 +103,6 @@ config SPI_FLASH_SOFT_RESET
 	 Enable support for xSPI Software Reset. It will be used to switch from
 	 Octal DTR mode to legacy mode on shutdown and boot (if enabled).
 
-config SPI_FLASH_SOFT_RESET_ON_BOOT
-	bool "Perform a Software Reset on boot on flashes that boot in stateful mode"
-	depends on SPI_FLASH_SOFT_RESET
-	help
-	 Perform a Software Reset on boot to allow detecting flashes that are
-	 handed to us in Octal DTR mode. Do not enable this config on flashes
-	 that are not supposed to be handed to U-Boot in Octal DTR mode, even
-	 if they _do_ support the Soft Reset sequence.
-
 config SPI_FLASH_BAR
 	bool "SPI flash Bank/Extended address register support"
 	help
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index df66a73495..caf764720c 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3796,33 +3796,6 @@ int spi_nor_scan(struct spi_nor *nor)
 
 	nor->setup = spi_nor_default_setup;
 
-#ifdef CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT
-	/*
-	 * When the flash is handed to us in a stateful mode like 8D-8D-8D, it
-	 * is difficult to detect the mode the flash is in. One option is to
-	 * read SFDP in all modes and see which one gives the correct "SFDP"
-	 * signature, but not all flashes support SFDP in 8D-8D-8D mode.
-	 *
-	 * Further, even if you detect the mode of the flash via SFDP, you
-	 * still have the problem of actually reading the ID. The Read ID
-	 * command is not standardized across flash vendors. Flashes can have
-	 * different dummy cycles needed for reading the ID. Some flashes even
-	 * expect a 4-byte dummy address with the Read ID command. All this
-	 * information cannot be obtained from the SFDP table.
-	 *
-	 * So, perform a Software Reset sequence before reading the ID and
-	 * initializing the flash. A Soft Reset will bring back the flash in
-	 * its default protocol mode assuming no non-volatile configuration was
-	 * set. This will let us detect the flash even if ROM hands it to us in
-	 * Octal DTR mode.
-	 *
-	 * To accommodate cases where there is more than one flash on a board,
-	 * and only one of them needs a soft reset, failure to reset is not
-	 * made fatal, and we still try to read ID if possible.
-	 */
-	spi_nor_soft_reset(nor);
-#endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */
-
 	info = spi_nor_read_id(nor);
 	if (IS_ERR_OR_NULL(info))
 		return -ENOENT;
-- 
2.25.1


  parent reply	other threads:[~2021-11-03 23:50 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-03 23:49 [PATCH v2 0/4] mtd: spi-nor: Fix software reset; add mx66lm1g45g Tudor Ambarus
2021-11-03 23:49 ` [PATCH v2 1/4] mtd: spi-nor-core: Introduce SPI_NOR_SOFT_RESET flash_info flag Tudor Ambarus
2021-11-09 19:31   ` Pratyush Yadav
2021-11-03 23:49 ` [PATCH v2 2/4] mtd: spi-nor-core: macronix: Add support for mx66lm1g45g Tudor Ambarus
2021-11-12 21:50   ` Pratyush Yadav
2021-11-13 13:48   ` Jagan Teki
2021-11-15  5:25     ` Tudor.Ambarus
2021-11-03 23:49 ` Tudor Ambarus [this message]
2021-11-09 19:26   ` [PATCH v2 3/4] Revert "mtd: spi-nor-core: Perform a Soft Reset on boot" Pratyush Yadav
2021-11-10  8:44     ` Tudor.Ambarus
2021-11-12 13:13       ` Pratyush Yadav
2021-11-15  5:44         ` Tudor.Ambarus
2021-12-16 18:45           ` Pratyush Yadav
2021-12-17  6:27             ` Tudor.Ambarus
2021-12-17 10:40               ` Pratyush Yadav
2021-11-03 23:49 ` [PATCH v2 4/4] mtd: spi-nor-core: Fix the opcode extension for the software reset sequence Tudor Ambarus
2021-11-09 19:29   ` Pratyush Yadav

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