RE: [PATCH] configs: ast2600: Move SPL bss section to DRAM space

From: ChiaWei Wang <chiawei_wang@aspeedtech.com>
To: Joel Stanley <joel@jms.id.au>, Tom Rini <trini@konsulko.com>
Cc: "Ryan Chen" <ryan_chen@aspeedtech.com>,
	BMC-SW <BMC-SW@aspeedtech.com>,
	"U-Boot Mailing List" <u-boot@lists.denx.de>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: RE: [PATCH] configs: ast2600: Move SPL bss section to DRAM space
Date: Wed, 29 Jun 2022 00:36:04 +0000	[thread overview]
Message-ID: <HK0PR06MB3779EDBF16AC6E113EC3F1A391BB9@HK0PR06MB3779.apcprd06.prod.outlook.com> (raw)
In-Reply-To: <CACPK8Xfq6N9BaAhb1Y+UgWDeDCxpYD3j9-tC8heUg5hh398Nyg@mail.gmail.com>

Hi Joel,

> From: Joel Stanley <joel@jms.id.au>
> Sent: Tuesday, June 28, 2022 12:24 PM
> 
> Hi Chai Wei,
> 
> On Wed, 1 Jun 2022 at 08:21, Chia-Wei Wang
> <chiawei_wang@aspeedtech.com> wrote:
> >
> > The commit b583348ca8c8 ("image: fit: Align hash output buffers")
> > places the hash output buffer at the .bss section. However, AST2600 by
> > default executes SPL in the NOR flash XIP way. This results in the
> > hash output cannot be written to the buffer as it is located at the R/X only
> region.
> >
> > We need to move the .bss section out of the SPL body to the DRAM
> > space, where hash output can be written to. This patch includes:
> >  - Define the .bss section base and size
> >  - A new SPL linker script is added with a separate .bss region
> > specified
> >  - Enable CONFIG_SPL_SEPARATE_BSS kconfig option
> >
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> 
> This patch breaks booting for me.
> 
> My concern with the approach is it creates extra maintenance work.
> When changes are made to the main linker script they need to be mirrored
> here, or else the aspeed port will miss out. (Having the machine tested in CI
> will help this somewhat, but only for the code paths we can test under
> emulation).

The patch was trying to solve the hash buffer allocation change to common code and to avoid similar issues.
But I agree there is additional maintenance work on the customized linker script.

> 
> I know the patch has been merged, but I have a few questions:
> 
> I imagine the ast2600 is not the only board that runs XIP. How do other boards
> solve the problem?
> 
> What happens when a symbol that is used before DRAM training has
> completed is placed in bss?

Honestly, I am not sure how other platforms/boards dealing with this.
But like U-Boot REAME stated, the initial global data is read-only.
I guess we have to be careful about the global variable use before DRAM initialization or even variable relocation.

> 
> How do you plan to support systems that don't have NOR?

We would like to have another defconfig for eMMC booting.
If the NOR-based linker script is not applicable, the default one can be used.

Chiawei