* [PATCH v1 0/9] Add Nuvoton NPCM845 support
@ 2021-12-15 2:57 Stanley Chu
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
` (8 more replies)
0 siblings, 9 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
The patch series add basic supoorts for NPCM845, which
is Nuvoton's 4th-generation BMC (Baseboard Management
Controller).
Add drivers to support Clock,Timer,Uart,GPIO, Pinctrl,
SPI Flash Access for NPCM8xx SoC.
Stanley Chu (9):
arm: nuvoton: Add support for Nuvoton NPCM845 BMC
clk: nuvoton: Add support for NPCM845
timer: npcm: Add NPCM timer support
serial: npcm: Add support for Nuvoton NPCM SoCs
gpio: npcm: Add support for Nuvoton NPCM SoCs
pinctrl: nuvoton: Add NPCM8xx pinctrl driver
spi: npcm-fiu: add NPCM8xx FIU controller driver
ARM: dts: Add Nuvoton NPCM845 device tree
ARM: configs: Add defconfig for Nuvoton NPCM845
arch/arm/Kconfig | 9 +
arch/arm/Makefile | 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 598 ++++++
arch/arm/dts/nuvoton-npcm845-evb.dts | 264 +++
arch/arm/dts/nuvoton-npcm845-pincfg.dtsi | 2007 ++++++++++++++++++++
arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi | 623 +++++++
arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++
arch/arm/include/asm/arch-npcm8xx/espi.h | 23 +
arch/arm/include/asm/arch-npcm8xx/fiu.h | 61 +
arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++
arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +
arch/arm/include/asm/arch-npcm8xx/uart.h | 82 +
arch/arm/mach-nuvoton/Kconfig | 24 +
arch/arm/mach-nuvoton/Makefile | 1 +
arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 +
arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++
arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 +
board/nuvoton/arbel/Kconfig | 18 +
board/nuvoton/arbel/MAINTAINERS | 7 +
board/nuvoton/arbel/Makefile | 1 +
board/nuvoton/arbel/arbel.c | 33 +
configs/arbel_evb_defconfig | 77 +
drivers/clk/Makefile | 1 +
drivers/clk/nuvoton/Makefile | 1 +
drivers/clk/nuvoton/clk_npcm8xx.c | 213 +++
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 1 +
drivers/gpio/npcm_gpio.c | 133 ++
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/nuvoton/Kconfig | 6 +
drivers/pinctrl/nuvoton/Makefile | 1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2042 +++++++++++++++++++++
drivers/serial/Kconfig | 7 +
drivers/serial/Makefile | 1 +
drivers/serial/serial_npcm.c | 137 ++
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/npcm_fiu_spi.c | 311 ++++
drivers/timer/Kconfig | 7 +
drivers/timer/Makefile | 1 +
drivers/timer/npcm_timer.c | 82 +
include/configs/arbel.h | 54 +
include/dt-bindings/clock/npcm845-clock.h | 17 +
47 files changed, 7622 insertions(+)
create mode 100644 arch/arm/dts/nuvoton-common-npcm8xx.dtsi
create mode 100644 arch/arm/dts/nuvoton-npcm845-evb.dts
create mode 100644 arch/arm/dts/nuvoton-npcm845-pincfg.dtsi
create mode 100644 arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi
create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/fiu.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/uart.h
create mode 100644 arch/arm/mach-nuvoton/Kconfig
create mode 100644 arch/arm/mach-nuvoton/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
create mode 100644 board/nuvoton/arbel/Kconfig
create mode 100644 board/nuvoton/arbel/MAINTAINERS
create mode 100644 board/nuvoton/arbel/Makefile
create mode 100644 board/nuvoton/arbel/arbel.c
create mode 100644 configs/arbel_evb_defconfig
create mode 100644 drivers/clk/nuvoton/Makefile
create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
create mode 100644 drivers/gpio/npcm_gpio.c
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
create mode 100644 drivers/serial/serial_npcm.c
create mode 100644 drivers/spi/npcm_fiu_spi.c
create mode 100644 drivers/timer/npcm_timer.c
create mode 100644 include/configs/arbel.h
create mode 100644 include/dt-bindings/clock/npcm845-clock.h
--
2.17.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 12:12 ` Giulio Benetti
` (2 more replies)
2021-12-15 2:57 ` [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845 Stanley Chu
` (7 subsequent siblings)
8 siblings, 3 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add basic support for the Nuvoton NPCM845 BMC.
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
arch/arm/Kconfig | 9 +
arch/arm/Makefile | 1 +
arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
arch/arm/mach-nuvoton/Kconfig | 24 ++
arch/arm/mach-nuvoton/Makefile | 1 +
arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
board/nuvoton/arbel/Kconfig | 18 ++
board/nuvoton/arbel/Makefile | 1 +
board/nuvoton/arbel/arbel.c | 33 +++
include/configs/arbel.h | 54 ++++
17 files changed, 924 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
create mode 100644 arch/arm/mach-nuvoton/Kconfig
create mode 100644 arch/arm/mach-nuvoton/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
create mode 100644 board/nuvoton/arbel/Kconfig
create mode 100644 board/nuvoton/arbel/Makefile
create mode 100644 board/nuvoton/arbel/arbel.c
create mode 100644 include/configs/arbel.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7f03837fe..80ec42f6be 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
select LINUX_KERNEL_IMAGE_HEADER
select XEN_SERIAL
select SSCANF
+
+config ARCH_NPCM
+ bool "Support Nuvoton SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+
endchoice
config SUPPORT_PASSING_ATAGS
@@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-nexell/Kconfig"
+source "arch/arm/mach-nuvoton/Kconfig"
+
source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ad757e982e..29a0250ab6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
+machine-$(CONFIG_ARCH_NPCM) += nuvoton
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
new file mode 100644
index 0000000000..088b536b7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_CLOCK_H_
+#define _NPCM_CLOCK_H_
+
+#define NPCM_CLK_BA 0xF0801000
+enum {
+ APB1 = 1,
+ APB2 = 2,
+ APB3 = 3,
+ APB4 = 4,
+ APB5 = 5,
+ SPI0 = 10,
+ SPI1 = 11,
+ SPI3 = 13,
+ SPIX = 14,
+};
+
+/* Clock Select Register (CLKSEL) */
+#define CLKSEL_RCPCKSEL 27
+#define CLKSEL_RGSEL 25
+#define CLKSEL_GFXMSEL 21
+#define CLKSEL_CLKOUTSEL 18
+#define CLKSEL_PCICKSEL 16
+#define CLKSEL_ADCCKSEL 14
+#define CLKSEL_MCCKSEL 12
+#define CLKSEL_SUCKSEL 10
+#define CLKSEL_UARTCKSEL 8
+#define CLKSEL_SDCKSEL 6
+#define CLKSEL_PIXCKSEL 4
+#define CLKSEL_CPUCKSEL 0
+
+/* Clock Divider Control Register 1 (CLKDIV1) */
+#define CLKDIV1_ADCCKDIV 28
+#define CLKDIV1_CLK4DIV 26
+#define CLKDIV1_PRE_ADCCKDIV 21
+#define CLKDIV1_UARTDIV 16
+#define CLKDIV1_MMCCKDIV 11
+#define CLKDIV1_SPI3CKDIV 6
+#define CLKDIV1_PCICKDIV 2
+
+/* Clock Divider Control Register 2 (CLKDIV2) */
+#define CLKDIV2_APB4CKDIV 30
+#define CLKDIV2_APB3CKDIV 28
+#define CLKDIV2_APB2CKDIV 26
+#define CLKDIV2_APB1CKDIV 24
+#define CLKDIV2_APB5CKDIV 22
+#define CLKDIV2_CLKOUTDIV 16
+#define CLKDIV2_GFXCKDIV 13
+#define CLKDIV2_SUCKDIV 8
+#define CLKDIV2_SU48CKDIV 4
+
+/* PLL Control Register 2 (PLLCON2) */
+#define PLLCON_LOKI 31
+#define PLLCON_LOKS 30
+#define PLLCON_FBDV 16
+#define PLLCON_OTDV2 13
+#define PLLCON_PWDEN 12
+#define PLLCON_OTDV1 8
+#define PLLCON_INDV 0
+
+/* CPUCKSEL (CPU/AMBA/MC Clock Source Select Bit) */
+#define CLKSEL_CPUCKSEL_PLL0 0x00 /* 0 0: PLL0 clock*/
+#define CLKSEL_CPUCKSEL_PLL1 0x01 /* 0 1: PLL1 clock */
+#define CLKSEL_CPUCKSEL_CLKREF 0x02 /* 1 0: CLKREF input (25 MHZ, default) */
+#define CLKSEL_CPUCKSEL_SYSBPCK 0x03 /* 1 1: Bypass clock from pin SYSBPCK */
+
+/* UARTCKSEL (Core and Host UART Clock Source Select Bit). */
+#define CLKSEL_UARTCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
+#define CLKSEL_UARTCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
+#define CLKSEL_UARTCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
+#define CLKSEL_UARTCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
+
+/* SDCKSEL (SDHC Clock Source Select Bit). */
+#define CLKSEL_SDCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
+#define CLKSEL_SDCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
+#define CLKSEL_SDCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
+#define CLKSEL_SDCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
+
+/* IP Software Reset Register 1 (IPSRST1), offset 0x20 */
+#define IPSRST1_USBDEV1 5
+#define IPSRST1_USBDEV2 8
+#define IPSRST1_USBDEV3 25
+#define IPSRST1_USBDEV4 22
+#define IPSRST1_USBDEV5 23
+#define IPSRST1_USBDEV6 24
+#define IPSRST1_GMAC4 21
+#define IPSRST1_GMAC3 6
+
+/* IP Software Reset Register 2 (IPSRST2), offset 0x24 */
+#define IPSRST2_GMAC1 28
+#define IPSRST2_GMAC2 25
+#define IPSRST2_USBHOST1 26
+#define IPSRST2_SDHC 9
+#define IPSRST2_MMC 8
+
+/* IP Software Reset Register 3 (IPSRST3), offset 0x34 */
+#define IPSRST3_USBPHY1 24
+#define IPSRST3_USBPHY2 25
+#define IPSRST3_USBHUB 8
+#define IPSRST3_USBDEV9 7
+#define IPSRST3_USBDEV8 6
+#define IPSRST3_USBDEV7 5
+#define IPSRST3_USBDEV0 4
+
+/* IP Software Reset Register 4 (IPSRST4), offset 0x74 */
+#define IPSRST4_USBHOST2 31
+#define IPSRST4_USBPHY3 25
+
+#define EXT_CLOCK_FREQUENCY_KHZ 25 * 1000 * 1UL
+#define EXT_CLOCK_FREQUENCY_MHZ 25
+
+struct clk_ctl {
+ unsigned int clken1;
+ unsigned int clksel;
+ unsigned int clkdiv1;
+ unsigned int pllcon0;
+ unsigned int pllcon1;
+ unsigned int swrstr;
+ unsigned char res1[0x8];
+ unsigned int ipsrst1;
+ unsigned int ipsrst2;
+ unsigned int clken2;
+ unsigned int clkdiv2;
+ unsigned int clken3;
+ unsigned int ipsrst3;
+ unsigned int wd0rcr;
+ unsigned int wd1rcr;
+ unsigned int wd2rcr;
+ unsigned int swrstc1;
+ unsigned int swrstc2;
+ unsigned int swrstc3;
+ unsigned int tiprstc;
+ unsigned int pllcon2;
+ unsigned int clkdiv3;
+ unsigned int corstc;
+ unsigned int pllcong;
+ unsigned int ahbckfi;
+ unsigned int seccnt;
+ unsigned int cntr25m;
+ unsigned int clken4;
+ unsigned int ipsrst4;
+ unsigned int busto;
+ unsigned int clkdiv4;
+ unsigned int wd0rcrb;
+ unsigned int wd1rcrb;
+ unsigned int wd2rcrb;
+ unsigned int swrstc1b;
+ unsigned int swrstc2b;
+ unsigned int swrstc3b;
+ unsigned int tiprstcb;
+ unsigned int corstcb;
+ unsigned int ipsrstdis1;
+ unsigned int ipsrstdis2;
+ unsigned int ipsrstdis3;
+ unsigned int ipsrstdis4;
+ unsigned char res2[0x10];
+ unsigned int thrtl_cnt;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/espi.h b/arch/arm/include/asm/arch-npcm8xx/espi.h
new file mode 100644
index 0000000000..d4de012b02
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/espi.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_ESPI_H_
+#define _NPCM_ESPI_H_
+
+#define NPCM_ESPI_BA 0xF009F000
+/* Register offsets */
+#define ESPICFG 0x04
+#define ESPIHINDP 0x80
+
+/* Channel Supported */
+#define ESPICFG_CHNSUPP_MASK 0x0F
+#define ESPICFG_CHNSUPP_SHFT 24
+
+/* I/O Mode Supported */
+#define ESPICFG_IOMODE_SHIFT 8
+#define ESPI_IO_MODE_SINGLE_DUAL_QUAD 3
+
+/* Maximum Frequency Supported */
+#define ESPICFG_MAXFREQ_SHIFT 10
+#define ESPI_MAX_33_MHZ 2
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
new file mode 100644
index 0000000000..14a4b2dbfb
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_GCR_H_
+#define _NPCM_GCR_H_
+
+#define NPCM_GCR_BA 0xF0800000
+/* On-Chip ARBEL NPCM8XX VERSIONS */
+
+#define ARBEL_Z1 0x00A35850
+#define ARBEL_A1 0x04a35850
+#define ARBEL_NPCM845 0x00000000
+#define ARBEL_NPCM830 0x00300395
+#define ARBEL_NPCM810 0x00000220
+
+/* Function Lock Register 2 (FLOCKR2) */
+#define FLOCKR2_MMCRST 12
+#define FLOCKR2_MMCRSTLK 13
+#define FLOCKR2_G35DA2P 18
+
+/* Power-On Setting Register (PWRON) */
+#define PWRON_BSPA 4 /* STRAP5 */
+#define PWRON_SECEN 7 /* STRAP8 */
+
+/* Multiple Function Pin Select Register 1 (MFSEL1) */
+#define MFSEL1_SIRQSE 31
+#define MFSEL1_IOX1SEL 30
+#define MFSEL1_HSI2BSEL 29
+#define MFSEL1_HSI1BSEL 28
+#define MFSEL1_DVH1SEL 27
+#define MFSEL1_LPCSEL 26
+#define MFSEL1_PECIB 25
+#define MFSEL1_GSPISEL 24
+#define MFSEL1_SMISEL 22
+#define MFSEL1_CLKOSEL 21
+#define MFSEL1_DVOSEL 18
+#define MFSEL1_KBCICSEL 17
+#define MFSEL1_R2MDSEL 16
+#define MFSEL1_R2ERRSEL 15
+#define MFSEL1_RMII2SEL 14
+#define MFSEL1_R1MDSEL 13
+#define MFSEL1_R1ERRSEL 12
+#define MFSEL1_HSI2ASEL 11
+#define MFSEL1_HSI1ASEL 10
+#define MFSEL1_BSPSEL 9
+#define MFSEL1_SMB2SEL 8
+#define MFSEL1_SMB1SEL 7
+#define MFSEL1_SMB0SEL 6
+#define MFSEL1_HSI2CSEL 5
+#define MFSEL1_HSI1CSEL 4
+#define MFSEL1_S0CS1SEL 3
+#define MFSEL1_SMB5SEL 2
+#define MFSEL1_SMB4SEL 1
+#define MFSEL1_SMB3SEL 0
+
+/* Multiple Function Pin Select Register 3 (MFSEL3) */
+#define MFSEL3_DVODEDLY 27
+#define MFSEL3_DDRDVOSEL 26
+#define MFSEL3_MMCCDSEL 25
+#define MFSEL3_BU1SEL 24
+#define MFSEL3_I3C5SEL 22
+#define MFSEL3_WDO2SEL 20
+#define MFSEL3_WDO1SEL 19
+#define MFSEL3_IOXHSEL 18
+#define MFSEL3_PCIEPUSE 17
+#define MFSEL3_CLKRUNSEL 16
+#define MFSEL3_IOX2SEL 14
+#define MFSEL3_PSPISEL 13
+#define MFSEL3_MMC8SEL 11
+#define MFSEL3_MMCSEL 10
+#define MFSEL3_RMII1SEL 9
+#define MFSEL3_SMB15SEL 8
+#define MFSEL3_SMB14SEL 7
+#define MFSEL3_SMB13SEL 6
+#define MFSEL3_SMB12SEL 5
+#define MFSEL3_SPI1SEL 4
+#define MFSEL3_FIN1916SELB 3
+#define MFSEL3_SMB7SEL 2
+#define MFSEL3_SMB6SEL 1
+#define MFSEL3_SCISEL 0
+
+/* Multiple Function Pin Select Register 4 (MFSEL4) */
+#define MFSEL4_SMB11DDC 29
+#define MFSEL4_SXCS1SEL 28
+#define MFSEL4_SPXSEL 27
+#define MFSEL4_RG2SEL 24
+#define MFSEL4_RG2MSEL 23
+#define MFSEL4_BU2SELB 22
+#define MFSEL4_SG1MSEL 21
+#define MFSEL4_SP3QSEL 20
+#define MFSEL4_S3CS3SEL 19
+#define MFSEL4_S3CS2SEL 18
+#define MFSEL4_S3CS1SEL 17
+#define MFSEL4_SP3SEL 16
+#define MFSEL4_SP0QSEL 15
+#define MFSEL4_SMB11SEL 14
+#define MFSEL4_SMB10SEL 13
+#define MFSEL4_SMB9SEL 12
+#define MFSEL4_SMB8SEL 11
+#define MFSEL4_DBGTRSEL 10
+#define MFSEL4_CKRQSEL 9
+#define MFSEL4_ESPISEL 8
+#define MFSEL4_MMCRSEL 6
+#define MFSEL4_SD1PSEL 5
+#define MFSEL4_ROSEL 4
+#define MFSEL4_ESPIPMESEL 2
+#define MFSEL4_BSPASEL 1
+#define MFSEL4_JTAG2SEL 0
+
+/* Multiple Function Pin Select Register 5 (MFSEL5) */
+#define MFSEL5_R3OENSEL 14
+#define MFSEL5_RMII3SEL 11
+#define MFSEL5_R2OENSEL 10
+#define MFSEL5_R1OENSEL 9
+#define MFSEL5_NSPI1CS3SEL 5
+#define MFSEL5_NSPI1CS2SEL 4
+#define MFSEL5_SPI1D23SEL 3
+#define MFSEL5_NSPI1CS1SEL 0
+
+/* Multiple Function Pin Select Register 6 (MFSEL6) */
+#define MFSEL6_GPIO1836SEL 19
+#define MFSEL6_FM1SEL 17
+
+/* Multiple Function Pin Select Register 7 (MFSEL7) */
+#define MFSEL7_SMB15SELB 27
+#define MFSEL7_GPIO1889SEL 25
+
+/* USB PHY1 Control Register (USB1PHYCTL) */
+#define USB1PHYCTL_RS 28
+/* USB PHY2 Control Register (USB2PHYCTL) */
+#define USB2PHYCTL_RS 28
+/* USB PHY2 Control Register (USB3PHYCTL) */
+#define USB3PHYCTL_RS 28
+
+/* Integration Control Register (INTCR) */
+#define INTCR_DUDKSMOD 30
+#define INTCR_DDC3I 29
+#define INTCR_KVMSI 28
+#define INTCR_DEHS 27
+#define INTCR_GGPCT2_0 24
+#define INTCR_SGC2 23
+#define INTCR_DSNS_TRIG 21
+#define INTCR_DAC_SNS 20
+#define INTCR_SGC1 19
+#define INTCR_LDDRB 18
+#define INTCR_GIRST 17
+#define INTCR_DUDKSEN 16
+#define INTCR_DACOFF 15
+#define INTCR_DACSEL 14
+#define INTCR_GFXINT 12
+#define INTCR_DACOSOVR 10
+#define INTCR_GFXIFDIS 8
+#define INTCR_H2RQDIS 9
+#define INTCR_H2DISPOFF 8
+#define INTCR_GFXINT2 7
+#define INTCR_VGAIOEN 6
+#define INTCR_PSPIFEN 4
+#define INTCR_HIFEN 3
+#define INTCR_SMBFEN 2
+#define INTCR_MFTFEN 1
+#define INTCR_KCSRST_MODE 0
+
+/* Integration Control Register (INTCR2) */
+#define INTCR2_WDC 21
+
+/* Integration Control Register (INTCR3) */
+#define INTCR3_USBLPBK2 31 /* USB loop-backed HOST 1/2 */
+#define INTCR3_USBLPBK 24 /* USB loop-backed mode on/off */
+#define INTCR3_USBPHY3SW 14 /* 2 bits */
+#define INTCR3_USBPHY2SW 12 /* 2 bits */
+#define INTCR3_USBPPS 6
+#define INTCR3_UHUB_RWUD 5
+
+/* Integration Control Register (INTCR4) */
+#define INTCR4_GMMAP1 24
+#define INTCR4_GMMAP0 16
+#define INTCR4_R3EN 14
+#define INTCR4_R2EN 13
+#define INTCR4_R1EN 12
+#define INTCR4_RGMIIREF 6
+
+/* I2C Segment Pin Select Register (I2CSEGSEL) */
+#define I2CSEGSEL_S0DECFG 3
+#define I2CSEGSEL_S4DECFG 17
+
+/* I2C Segment Control Register (I2CSEGCTL) */
+#define I2CSEGCTL_S0DEN 20
+#define I2CSEGCTL_S0DWE 21
+#define I2CSEGCTL_S4DEN 24
+#define I2CSEGCTL_S4DWE 25
+#define I2CSEGCTL_INIT_VAL 0x9333F000
+
+struct npcm_gcr {
+ unsigned int pdid;
+ unsigned int pwron;
+ unsigned int swstrps;
+ unsigned int rsvd1[2];
+ unsigned int miscpe;
+ unsigned int spldcnt;
+ unsigned int rsvd2[1];
+ unsigned int flockr2;
+ unsigned int flockr3;
+ unsigned int rsvd3[3];
+ unsigned int a35_mode;
+ unsigned int spswc;
+ unsigned int intcr;
+ unsigned int intsr;
+ unsigned int obscr1;
+ unsigned int obsdr1;
+ unsigned int rsvd4[1];
+ unsigned int hifcr;
+ unsigned int rsvd5[3];
+ unsigned int intcr2;
+ unsigned int rsvd6[1];
+ unsigned int srcnt;
+ unsigned int ressr;
+ unsigned int rlockr1;
+ unsigned int flockr1;
+ unsigned int dscnt;
+ unsigned int mdlr;
+ unsigned int scrpad_c;
+ /* scrpad_b: holds the active dram size (value set by bootblock) */
+ unsigned int scrpad_b;
+ unsigned int rsvd7[4];
+ unsigned int daclvlr;
+ unsigned int intcr3;
+ unsigned int pcirctl;
+ unsigned int rsvd8[2];
+ unsigned int vsintr;
+ unsigned int rsvd9[1];
+ unsigned int sd2sur1;
+ unsigned int sd2sur2;
+ unsigned int sd2irv3;
+ unsigned int intcr4;
+ unsigned int obscr2;
+ unsigned int obsdr2;
+ unsigned int rsvd10[5];
+ unsigned int i2csegsel;
+ unsigned int i2csegctl;
+ unsigned int vsrcr;
+ unsigned int mlockr;
+ unsigned int rsvd11[8];
+ unsigned int etsr;
+ unsigned int dft1r;
+ unsigned int dft2r;
+ unsigned int dft3r;
+ unsigned int edffsr;
+ unsigned int rsvd12[1];
+ unsigned int intcrpce3;
+ unsigned int intcrpce2;
+ unsigned int intcrpce0;
+ unsigned int intcrpce1;
+ unsigned int dactest;
+ unsigned int scrpad;
+ unsigned int usb1phyctl;
+ unsigned int usb2phyctl;
+ unsigned int usb3phyctl;
+ unsigned int intsr2;
+ unsigned int intcrpce2b;
+ unsigned int intcrpce0b;
+ unsigned int intcrpce1b;
+ unsigned int intcrpce3b;
+ unsigned int rsvd13[4];
+ unsigned int intcrpce2c;
+ unsigned int intcrpce0c;
+ unsigned int intcrpce1c;
+ unsigned int intcrpce3c;
+ unsigned int rsvd14[40];
+ unsigned int sd2irv4;
+ unsigned int sd2irv5;
+ unsigned int sd2irv6;
+ unsigned int sd2irv7;
+ unsigned int sd2irv8;
+ unsigned int sd2irv9;
+ unsigned int sd2irv10;
+ unsigned int sd2irv11;
+ unsigned int rsvd15[8];
+ unsigned int mfsel1;
+ unsigned int mfsel2;
+ unsigned int mfsel3;
+ unsigned int mfsel4;
+ unsigned int mfsel5;
+ unsigned int mfsel6;
+ unsigned int mfsel7;
+ unsigned int rsvd16[1];
+ unsigned int mfsel_lk1;
+ unsigned int mfsel_lk2;
+ unsigned int mfsel_lk3;
+ unsigned int mfsel_lk4;
+ unsigned int mfsel_lk5;
+ unsigned int mfsel_lk6;
+ unsigned int mfsel_lk7;
+ unsigned int rsvd17[1];
+ unsigned int mfsel_set1;
+ unsigned int mfsel_set2;
+ unsigned int mfsel_set3;
+ unsigned int mfsel_set4;
+ unsigned int mfsel_set5;
+ unsigned int mfsel_set6;
+ unsigned int mfsel_set7;
+ unsigned int rsvd18[1];
+ unsigned int mfsel_clr1;
+ unsigned int mfsel_clr2;
+ unsigned int mfsel_clr3;
+ unsigned int mfsel_clr4;
+ unsigned int mfsel_clr5;
+ unsigned int mfsel_clr6;
+ unsigned int mfsel_clr7;
+ };
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/gpio.h b/arch/arm/include/asm/arch-npcm8xx/gpio.h
new file mode 100644
index 0000000000..234a1d3de9
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_GPIO_H_
+#define _NPCM_GPIO_H_
+
+#define NPCM_GPIO_BA 0xF0010000
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
new file mode 100644
index 0000000000..ffaff50fe2
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_RST_H_
+#define _NPCM_RST_H_
+
+enum reset_type {
+ PORST_TYPE = 0x01,
+ CORST_TYPE = 0x02,
+ WD0RST_TYPE = 0x03,
+ SWR1ST_TYPE = 0x04,
+ SWR2ST_TYPE = 0x05,
+ SWR3ST_TYPE = 0x06,
+ SWR4ST_TYPE = 0x07,
+ WD1RST_TYPE = 0x08,
+ WD2RST_TYPE = 0x09,
+ UNKNOWN_TYPE = 0x10,
+};
+
+#define PORST 0x80000000
+#define CORST 0x40000000
+#define WD0RST 0x20000000
+#define SWR1ST 0x10000000
+#define SWR2ST 0x08000000
+#define SWR3ST 0x04000000
+#define SWR4ST 0x02000000
+#define WD1RST 0x01000000
+#define WD2RST 0x00800000
+#define RESSR_MASK 0xff800000
+
+enum reset_type npcm8xx_reset_reason(void);
+
+#endif
diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig
new file mode 100644
index 0000000000..e014dd4b79
--- /dev/null
+++ b/arch/arm/mach-nuvoton/Kconfig
@@ -0,0 +1,24 @@
+if ARCH_NPCM
+
+config SYS_ARCH
+ default "arm"
+
+config SYS_TEXT_BASE
+ default 0x8000
+
+choice
+ prompt "Nuvoton SoC select"
+ default ARCH_NPCM8XX
+
+config ARCH_NPCM8XX
+ bool "Support Nuvoton NPCM8xx SoC"
+ select ARM64
+ help
+ General support for NPCM8xx BMC (Arbel).
+ Nuvoton NPCM8xx BMC is based on the Cortex A35.
+
+endchoice
+
+source "arch/arm/mach-nuvoton/npcm8xx/Kconfig"
+
+endif
diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile
new file mode 100644
index 0000000000..e75689a1a0
--- /dev/null
+++ b/arch/arm/mach-nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
diff --git a/arch/arm/mach-nuvoton/npcm8xx/Kconfig b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
new file mode 100644
index 0000000000..478a046ad5
--- /dev/null
+++ b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_NPCM8XX
+
+config SYS_CPU
+ default "armv8"
+
+config SYS_SOC
+ default "npcm8xx"
+
+config TARGET_ARBEL_EVB
+ bool "Arbel-EVB"
+ help
+ ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
+ supports general functions of Basebase Management Controller
+ (BMC).
+
+source "board/nuvoton/arbel/Kconfig"
+
+endif
diff --git a/arch/arm/mach-nuvoton/npcm8xx/Makefile b/arch/arm/mach-nuvoton/npcm8xx/Makefile
new file mode 100644
index 0000000000..c62a4aa20a
--- /dev/null
+++ b/arch/arm/mach-nuvoton/npcm8xx/Makefile
@@ -0,0 +1 @@
+obj-y += reset.o cpu.o
diff --git a/arch/arm/mach-nuvoton/npcm8xx/cpu.c b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
new file mode 100644
index 0000000000..8a7315d535
--- /dev/null
+++ b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <cpu_func.h>
+#include <asm/io.h>
+#include <asm/arch/gcr.h>
+#include <asm/arch/espi.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+#include <asm/global_data.h>
+
+/* System Counter */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 cntfid2;
+ u32 resv2[1001];
+ u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE BIT(0)
+#define SC_CNTCR_HDBG BIT(1)
+#define SC_CNTCR_FREQ0 BIT(8)
+#define SC_CNTCR_FREQ1 BIT(9)
+
+#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int print_cpuinfo(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+ unsigned int id = 0;
+ unsigned long mpidr_val = 0;
+ unsigned int mdlr = 0;
+
+ asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
+
+ mdlr = readl(&gcr->mdlr);
+
+ printf("CPU-%d: ", (unsigned int)(mpidr_val & 0x3));
+
+ switch (mdlr) {
+ case ARBEL_NPCM845:
+ printf("NPCM845 ");
+ break;
+ case ARBEL_NPCM830:
+ printf("NPCM830 ");
+ break;
+ case ARBEL_NPCM810:
+ printf("NPCM810 ");
+ break;
+ default:
+ printf("NPCM8XX ");
+ break;
+ }
+
+ id = readl(&gcr->pdid);
+ switch (id) {
+ case ARBEL_Z1:
+ printf("Z1 @ ");
+ break;
+ case ARBEL_A1:
+ printf("A1 @ ");
+ break;
+ default:
+ printf("Unknown\n");
+ break;
+ }
+
+ return 0;
+}
+
+static void npcm_sysintf_init(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+ u32 espi_ch_supp, val;
+
+ espi_ch_supp = ofnode_conf_read_int("espi-channel-support", 0);
+
+ if (espi_ch_supp) {
+ /* Use eSPI function and initialize ESPICFG */
+ u32 hindp = 0x00011110 | espi_ch_supp;
+
+ writel((readl(&gcr->mfsel4) | (1 << MFSEL4_ESPISEL)), &gcr->mfsel4);
+ writel(hindp, NPCM_ESPI_BA + ESPIHINDP);
+ val = readl(NPCM_ESPI_BA + ESPICFG);
+ val |= ESPI_IO_MODE_SINGLE_DUAL_QUAD << ESPICFG_IOMODE_SHIFT;
+ val |= ESPI_MAX_33_MHZ << ESPICFG_MAXFREQ_SHIFT;
+ val |= ((espi_ch_supp & ESPICFG_CHNSUPP_MASK) << ESPICFG_CHNSUPP_SHFT);
+ writel(val, NPCM_ESPI_BA + ESPICFG);
+ } else {
+ /* Use LPC function */
+ writel((readl(&gcr->mfsel1) | (1 << MFSEL1_LPCSEL)), &gcr->mfsel1);
+ }
+}
+
+int arch_cpu_init(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+
+ if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
+ /* enable cache to speed up system running */
+ if (get_sctlr() & CR_M)
+ return 0;
+
+ icache_enable();
+ __asm_invalidate_dcache_all();
+ __asm_invalidate_tlb_all();
+ set_sctlr(get_sctlr() | CR_C);
+ }
+
+ /* Power voltage select setup */
+ setbits_le32(&gcr->vsrcr, BIT(30));
+
+ npcm_sysintf_init();
+
+ return 0;
+}
+
+static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
+ {
+ /* DRAM */
+ .phys = 0x0UL,
+ .virt = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ .phys = 0x80000000UL,
+ .virt = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = npcm_mem_map;
+
+int timer_init(void)
+{
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned int cntfrq_el0;
+
+ __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
+ writel(cntfrq_el0, &sctr->cntfid0);
+
+ clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
diff --git a/arch/arm/mach-nuvoton/npcm8xx/reset.c b/arch/arm/mach-nuvoton/npcm8xx/reset.c
new file mode 100644
index 0000000000..7fbed7ba76
--- /dev/null
+++ b/arch/arm/mach-nuvoton/npcm8xx/reset.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/rst.h>
+#include <asm/arch/gcr.h>
+
+void reset_cpu(void)
+{
+ /* Watcdog reset - WTCR register set WTE-BIT7 WTRE-BIT1 WTR-BIT0 */
+ writel(0x83, 0xf000801c);
+
+ while (1)
+ ;
+}
+
+void reset_misc(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+
+ /* clear WDC */
+ writel(readl(&gcr->intcr2) & ~(1 << INTCR2_WDC), &gcr->intcr2);
+}
+
+enum reset_type npcm8xx_reset_reason(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+ enum reset_type type = UNKNOWN_TYPE;
+ u32 value = readl(&gcr->ressr);
+
+ if (value == 0)
+ value = ~readl(&gcr->intcr2);
+
+ value &= RESSR_MASK;
+
+ if (value & CORST)
+ type = CORST;
+ if (value & WD0RST)
+ type = WD0RST;
+ if (value & WD1RST)
+ type = WD1RST;
+ if (value & WD2RST)
+ type = WD2RST;
+ if (value & PORST)
+ type = PORST;
+
+ return type;
+}
diff --git a/board/nuvoton/arbel/Kconfig b/board/nuvoton/arbel/Kconfig
new file mode 100644
index 0000000000..4a03ea1abf
--- /dev/null
+++ b/board/nuvoton/arbel/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ARBEL_EVB
+
+config SYS_BOARD
+ default "arbel"
+
+config SYS_VENDOR
+ default "nuvoton"
+
+config SYS_CONFIG_NAME
+ default "arbel"
+
+config SYS_MEM_TOP_HIDE
+ hex "Reserved TOP memory"
+ default 0xB000000
+ help
+ Reserve memory for ECC/GFX/VCD/ECE.
+
+endif
diff --git a/board/nuvoton/arbel/Makefile b/board/nuvoton/arbel/Makefile
new file mode 100644
index 0000000000..f9ad1dea34
--- /dev/null
+++ b/board/nuvoton/arbel/Makefile
@@ -0,0 +1 @@
+obj-y += arbel.o
diff --git a/board/nuvoton/arbel/arbel.c b/board/nuvoton/arbel/arbel.c
new file mode 100644
index 0000000000..86cef98c5f
--- /dev/null
+++ b/board/nuvoton/arbel/arbel.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/gcr.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_NPCMX50;
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100UL);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+
+ /*
+ * get dram active size value from bootblock.
+ * Value sent using scrpad_02 register.
+ */
+ gd->ram_size = readl(&gcr->scrpad_b);
+
+ return 0;
+}
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
new file mode 100644
index 0000000000..2cb658c3e6
--- /dev/null
+++ b/include/configs/arbel.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef __CONFIG_ARBEL_H
+#define __CONFIG_ARBEL_H
+
+#define CONFIG_GICV2
+#define GICD_BASE (0xDFFF9000)
+#define GICC_BASE (0xDFFFA000)
+
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BOOTM_LEN (20 << 20)
+#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
+#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_BITBANGMII_MULTI
+
+/* Default environemnt variables */
+#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot"
+#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "ethact=gmac1\0" \
+ "autostart=no\0" \
+ "ethaddr=00:00:F7:A0:00:FC\0" \
+ "eth1addr=00:00:F7:A0:00:FD\0" \
+ "eth2addr=00:00:F7:A0:00:FE\0" \
+ "eth3addr=00:00:F7:A0:00:FF\0" \
+ "gatewayip=192.168.0.17\0" \
+ "serverip=192.168.0.17\0" \
+ "ipaddr=192.168.0.15\0" \
+ "romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
+ "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
+ "earlycon=uart8250,mmio32,0xf0000000\0" \
+ "console=ttyS0,115200n8\0" \
+ "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
+ "console=${console} ramdisk_size=48000\0" \
+ "\0"
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 18:32 ` Sean Anderson
2022-02-16 16:25 ` Tom Rini
2021-12-15 2:57 ` [PATCH v1 3/9] timer: npcm: Add NPCM timer support Stanley Chu
` (6 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add clock controller driver for NPCM845
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
drivers/clk/Makefile | 1 +
drivers/clk/nuvoton/Makefile | 1 +
drivers/clk/nuvoton/clk_npcm8xx.c | 213 ++++++++++++++++++++++
include/dt-bindings/clock/npcm845-clock.h | 17 ++
4 files changed, 232 insertions(+)
create mode 100644 drivers/clk/nuvoton/Makefile
create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
create mode 100644 include/dt-bindings/clock/npcm845-clock.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 711ae5bc29..a3b64b73c2 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile
new file mode 100644
index 0000000000..998e5329bb
--- /dev/null
+++ b/drivers/clk/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_NPCM8XX) += clk_npcm8xx.o
diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c
new file mode 100644
index 0000000000..c547c47e82
--- /dev/null
+++ b/drivers/clk/nuvoton/clk_npcm8xx.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk-uclass.h>
+#include <asm/types.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <dt-bindings/clock/npcm845-clock.h>
+
+struct npcm_clk_priv {
+ struct clk_ctl *regs;
+};
+
+enum regss {
+ PLL_0,
+ PLL_1,
+ PLL_2,
+ PLL_CLKREF,
+};
+
+static u32 clk_get_pll_freq(struct clk_ctl *regs, enum regss pll)
+{
+ u32 pllval;
+ u32 fin = EXT_CLOCK_FREQUENCY_KHZ; /* 25KHz */
+ u32 fout, nr, nf, no;
+
+ switch (pll) {
+ case PLL_0:
+ pllval = readl(®s->pllcon0);
+ break;
+ case PLL_1:
+ pllval = readl(®s->pllcon1);
+ break;
+ case PLL_2:
+ pllval = readl(®s->pllcon2);
+ break;
+ case PLL_CLKREF:
+ default:
+ return 0;
+ }
+
+ /* PLL Input Clock Divider */
+ nr = (pllval >> PLLCON_INDV) & 0x1f;
+ /* PLL VCO Output Clock Feedback Divider */
+ nf = (pllval >> PLLCON_FBDV) & 0xfff;
+ /* PLL Output Clock Divider 1 */
+ no = ((pllval >> PLLCON_OTDV1) & 0x7) *
+ ((pllval >> PLLCON_OTDV2) & 0x7);
+
+ fout = ((10 * fin * nf) / (no * nr));
+
+ return fout * 100;
+}
+
+static u32 npcm_mmc_set_rate(struct clk_ctl *regs, ulong rate)
+{
+ u32 pll0_freq, div, sdhci_clk;
+
+ /* To acquire PLL0 frequency. */
+ pll0_freq = clk_get_pll_freq(regs, PLL_0);
+
+ /* Calculate rounded up div to produce closest to
+ * target output clock
+ */
+ div = (pll0_freq % rate == 0) ? (pll0_freq / rate) :
+ (pll0_freq / rate) + 1;
+
+ writel((readl(®s->clkdiv1) & ~(0x1f << CLKDIV1_MMCCKDIV))
+ | (div - 1) << CLKDIV1_MMCCKDIV, ®s->clkdiv1);
+
+ /* Wait to the div to stabilize */
+ udelay(100);
+
+ /* Select PLL0 as source */
+ writel((readl(®s->clksel) & ~(0x3 << CLKSEL_SDCKSEL))
+ | (CLKSEL_SDCKSEL_PLL0 << CLKSEL_SDCKSEL),
+ ®s->clksel);
+
+ sdhci_clk = pll0_freq / div;
+
+ return sdhci_clk;
+}
+
+static u32 npcm_uart_set_rate(struct clk_ctl *regs, ulong rate)
+{
+ u32 src_freq, div;
+
+ src_freq = clk_get_pll_freq(regs, PLL_2) / 2;
+ div = (src_freq % rate == 0) ? (src_freq / rate) :
+ (src_freq / rate) + 1;
+ writel((readl(®s->clkdiv1) & ~(0x1f << CLKDIV1_UARTDIV))
+ | (div - 1) << CLKDIV1_UARTDIV, ®s->clkdiv1);
+ writel((readl(®s->clksel) & ~(3 << CLKSEL_UARTCKSEL))
+ | (CLKSEL_UARTCKSEL_PLL2 << CLKSEL_UARTCKSEL),
+ ®s->clksel);
+
+ return (src_freq / div);
+}
+
+static ulong npcm_get_cpu_freq(struct clk_ctl *regs)
+{
+ ulong fout = 0;
+ u32 clksel = readl(®s->clksel) & (0x3 << CLKSEL_CPUCKSEL);
+
+ if (clksel == CLKSEL_CPUCKSEL_PLL0)
+ fout = (ulong)clk_get_pll_freq(regs, PLL_0);
+ else if (clksel == CLKSEL_CPUCKSEL_PLL1)
+ fout = (ulong)clk_get_pll_freq(regs, PLL_1);
+ else if (clksel == CLKSEL_CPUCKSEL_CLKREF)
+ fout = EXT_CLOCK_FREQUENCY_MHZ; /* FOUT is specified in MHz */
+ else
+ fout = EXT_CLOCK_FREQUENCY_MHZ; /* FOUT is specified in MHz */
+
+ return fout;
+}
+
+static u32 npcm_get_apb_divisor(struct clk_ctl *regs, u32 apb)
+{
+ u32 apb_divisor = 2;
+
+ /* AHBn div */
+ apb_divisor = apb_divisor * (1 << ((readl(®s->clkdiv1)
+ >> CLKDIV1_CLK4DIV) & 0x3));
+
+ switch (apb) {
+ case APB2: /* APB divisor */
+ apb_divisor = apb_divisor *
+ (1 << ((readl(®s->clkdiv2)
+ >> CLKDIV2_APB2CKDIV) & 0x3));
+ break;
+ case APB5: /* APB divisor */
+ apb_divisor = apb_divisor *
+ (1 << ((readl(®s->clkdiv2)
+ >> CLKDIV2_APB5CKDIV) & 0x3));
+ break;
+ default:
+ apb_divisor = 0xFFFFFFFF;
+ break;
+ }
+
+ return apb_divisor;
+}
+
+static ulong npcm_clk_get_rate(struct clk *clk)
+{
+ struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLK_APB2:
+ return npcm_get_cpu_freq(priv->regs) /
+ npcm_get_apb_divisor(priv->regs, APB2);
+ case CLK_APB5:
+ return npcm_get_cpu_freq(priv->regs) /
+ npcm_get_apb_divisor(priv->regs, APB5);
+ }
+
+ return 0;
+}
+
+static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLK_EMMC:
+ return npcm_mmc_set_rate(priv->regs, rate);
+
+ case CLK_UART:
+ return npcm_uart_set_rate(priv->regs, rate);
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static int npcm_clk_probe(struct udevice *dev)
+{
+ struct npcm_clk_priv *priv = dev_get_priv(dev);
+ void *base;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENOENT;
+
+ priv->regs = (struct clk_ctl *)base;
+
+ return 0;
+}
+
+static struct clk_ops npcm_clk_ops = {
+ .get_rate = npcm_clk_get_rate,
+ .set_rate = npcm_clk_set_rate,
+};
+
+static const struct udevice_id npcm_clk_ids[] = {
+ { .compatible = "nuvoton,npcm845-clock" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_npcm) = {
+ .name = "clk_npcm",
+ .id = UCLASS_CLK,
+ .of_match = npcm_clk_ids,
+ .ops = &npcm_clk_ops,
+ .priv_auto = sizeof(struct npcm_clk_priv),
+ .probe = npcm_clk_probe,
+};
diff --git a/include/dt-bindings/clock/npcm845-clock.h b/include/dt-bindings/clock/npcm845-clock.h
new file mode 100644
index 0000000000..fca10d39c8
--- /dev/null
+++ b/include/dt-bindings/clock/npcm845-clock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _DT_BINDINGS_NPCM845_CLOCK_H_
+#define _DT_BINDINGS_NPCM845_CLOCK_H_
+
+#define CLK_TIMER 0
+#define CLK_UART 1
+#define CLK_SD 2
+#define CLK_EMMC 3
+#define CLK_APB1 4
+#define CLK_APB2 5
+#define CLK_APB3 6
+#define CLK_APB4 7
+#define CLK_APB5 8
+#define CLK_AHB 9
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 3/9] timer: npcm: Add NPCM timer support
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
2021-12-15 2:57 ` [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845 Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 2:57 ` [PATCH v1 4/9] serial: npcm: Add support for Nuvoton NPCM SoCs Stanley Chu
` (5 subsequent siblings)
8 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver.
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
drivers/timer/Kconfig | 7 ++++
drivers/timer/Makefile | 1 +
drivers/timer/npcm_timer.c | 82 ++++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+)
create mode 100644 drivers/timer/npcm_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 8913142654..c17bc5b8b9 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -234,4 +234,11 @@ config IMX_GPT_TIMER
Select this to enable support for the timer found on
NXP i.MX devices.
+config NPCM_TIMER
+ bool "Nuvoton NPCM timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ Nuvoton NPCM devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index e2bd530eb0..d6f04f1cf4 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o
obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o
+obj-$(CONFIG_NPCM_TIMER) += npcm_timer.o
diff --git a/drivers/timer/npcm_timer.c b/drivers/timer/npcm_timer.c
new file mode 100644
index 0000000000..499c1003ff
--- /dev/null
+++ b/drivers/timer/npcm_timer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define NPCM_CLOCK_RATE 1000000
+#define NPCM_TIMER_INIT_VAL 0xFFFFFFFF
+
+/* Register offsets */
+#define TCR0 0x0
+#define TICR0 0x8
+#define TDR0 0x10
+
+/* TCR fields */
+#define TCR_MODE_PERIODIC BIT(27)
+#define TCR_EN BIT(30)
+#define TCR_PRESCALE_25 (25 - 1)
+
+struct npcm_timer_priv {
+ void __iomem *base;
+};
+
+static u64 npcm_timer_get_count(struct udevice *dev)
+{
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ val = NPCM_TIMER_INIT_VAL - readl(priv->base + TDR0);
+
+ return timer_conv_64(val);
+}
+
+static int npcm_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct npcm_timer_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+ uc_priv->clock_rate = NPCM_CLOCK_RATE;
+
+ writel(0, priv->base + TCR0);
+ writel(NPCM_TIMER_INIT_VAL, priv->base + TICR0);
+
+ /*
+ * Configure timer and start
+ * periodic mode
+ * input clock freq = 25Mhz
+ * prescale = 25
+ * clock rate = 25Mhz/25 = 1Mhz
+ */
+ writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE_25,
+ priv->base + TCR0);
+
+ return 0;
+}
+
+static const struct timer_ops npcm_timer_ops = {
+ .get_count = npcm_timer_get_count,
+};
+
+static const struct udevice_id npcm_timer_ids[] = {
+ { .compatible = "nuvoton,npcm845-timer" },
+ { .compatible = "nuvoton,npcm750-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(npcm_timer) = {
+ .name = "npcm_timer",
+ .id = UCLASS_TIMER,
+ .of_match = npcm_timer_ids,
+ .priv_auto = sizeof(struct npcm_timer_priv),
+ .probe = npcm_timer_probe,
+ .ops = &npcm_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 4/9] serial: npcm: Add support for Nuvoton NPCM SoCs
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
` (2 preceding siblings ...)
2021-12-15 2:57 ` [PATCH v1 3/9] timer: npcm: Add NPCM timer support Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 2:57 ` [PATCH v1 5/9] gpio: " Stanley Chu
` (4 subsequent siblings)
8 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add Nuvoton BMC NPCM7xx/NPCM8xx uart driver
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
arch/arm/include/asm/arch-npcm8xx/uart.h | 82 ++++++++++++++
drivers/serial/Kconfig | 7 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_npcm.c | 137 +++++++++++++++++++++++
4 files changed, 227 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/uart.h
create mode 100644 drivers/serial/serial_npcm.c
diff --git a/arch/arm/include/asm/arch-npcm8xx/uart.h b/arch/arm/include/asm/arch-npcm8xx/uart.h
new file mode 100644
index 0000000000..e3c86849f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/uart.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_UART_H_
+#define _NPCM_UART_H_
+
+struct npcm_uart {
+ union {
+ unsigned int rbr;
+ unsigned int thr;
+ unsigned int dll;
+ };
+ union {
+ unsigned int ier;
+ unsigned int dlm;
+ };
+ union {
+ unsigned int iir;
+ unsigned int fcr;
+ };
+ unsigned int lcr;
+ unsigned int mcr;
+ unsigned int lsr;
+ unsigned int msr;
+ unsigned int tor;
+};
+
+#define IER_DBGACK BIT(4)
+#define IER_MSIE BIT(3)
+#define IER_RLSE BIT(2)
+#define IER_THREIE BIT(1)
+#define IER_RDAIE BIT(0)
+
+#define IIR_FMES BIT(7)
+#define IIR_RFTLS BIT(5)
+#define IIR_DMS BIT(4)
+#define IIR_IID BIT(1)
+#define IIR_NIP BIT(0)
+
+#define FCR_RFITL_1B (0 << 4)
+#define FCR_RFITL_4B (4 << 4)
+#define FCR_RFITL_8B (8 << 4)
+#define FCR_RFITL_14B (12 << 4)
+#define FCR_DMS BIT(3)
+#define FCR_TFR BIT(2)
+#define FCR_RFR BIT(1)
+#define FCR_FME BIT(0)
+
+#define LCR_DLAB BIT(7)
+#define LCR_BCB BIT(6)
+#define LCR_SPE BIT(5)
+#define LCR_EPS BIT(4)
+#define LCR_PBE BIT(3)
+#define LCR_NSB BIT(2)
+#define LCR_WLS_8b 3
+#define LCR_WLS_7b 2
+#define LCR_WLS_6b 1
+#define LCR_WLS_5b 0
+
+#define MCR_LBME BIT(4)
+#define MCR_OUT2 BIT(3)
+#define MCR_RTS BIT(1)
+#define MCR_DTR BIT(0)
+
+#define LSR_ERR_RX BIT(7)
+#define LSR_TE BIT(6)
+#define LSR_THRE BIT(5)
+#define LSR_BII BIT(4)
+#define LSR_FEI BIT(3)
+#define LSR_PEI BIT(2)
+#define LSR_OEI BIT(1)
+#define LSR_RFDR BIT(0)
+
+#define MSR_DCD BIT(7)
+#define MSR_RI BIT(6)
+#define MSR_DSR BIT(5)
+#define MSR_CTS BIT(4)
+#define MSR_DDCD BIT(3)
+#define MSR_DRI BIT(2)
+#define MSR_DDSR BIT(1)
+#define MSR_DCTS BIT(0)
+
+#endif
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 6c8fdda9a0..3982bc9426 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -975,4 +975,11 @@ config SYS_SDMR
depends on MPC8XX_CONS
default 0
+config NPCM_SERIAL
+ bool "Nuvoton NPCM UART driver"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for Nuvoton BMCs
+ (NPCM7xx and NPCM8xx)
+
endif
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8168af640f..1b86acf5cf 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o
obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
+obj-$(CONFIG_NPCM_SERIAL) += serial_npcm.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
new file mode 100644
index 0000000000..330c544e5a
--- /dev/null
+++ b/drivers/serial/serial_npcm.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <serial.h>
+#include <clk.h>
+#include <asm/arch/uart.h>
+
+struct npcm_serial_plat {
+ struct npcm_uart *reg;
+ u32 uart_clk;
+};
+
+static int npcm_serial_init(struct npcm_uart *uart)
+{
+ u8 val;
+
+ /* Disable all UART interrupt */
+ writeb(0, &uart->ier);
+
+ /* Set port for 8 bit, 1 stop, no parity */
+ val = LCR_WLS_8b;
+ writeb(val, &uart->lcr);
+
+ /* Set the RX FIFO trigger level, reset RX, TX FIFO */
+ val = FCR_FME | FCR_RFR | FCR_TFR | FCR_RFITL_4B;
+ writeb(val, &uart->fcr);
+
+ return 0;
+}
+
+static int npcm_serial_pending(struct udevice *dev, bool input)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *const uart = plat->reg;
+
+ if (input)
+ return (readb(&uart->lsr) & LSR_RFDR);
+ else
+ return !(readb(&uart->lsr) & LSR_THRE);
+
+ return 0;
+}
+
+static int npcm_serial_putc(struct udevice *dev, const char ch)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *const uart = plat->reg;
+
+ while (!(readl(&uart->lsr) & LSR_THRE))
+ ;
+
+ writeb(ch, &uart->thr);
+
+ return 0;
+}
+
+static int npcm_serial_getc(struct udevice *dev)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *const uart = plat->reg;
+
+ while (!(readl(&uart->lsr) & LSR_RFDR))
+ ;
+
+ return (int)(readb(&uart->rbr) & 0xff);
+}
+
+static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *const uart = plat->reg;
+ int ret = 0;
+ u32 divisor;
+
+ /* BaudOut = UART Clock / (16 * [Divisor + 2]) */
+ divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
+
+ writeb(readb(&uart->lcr) | LCR_DLAB, &uart->lcr);
+ writeb(divisor & 0xff, &uart->dll);
+ writeb(divisor >> 8, &uart->dlm);
+ writeb(readb(&uart->lcr) & (~LCR_DLAB), &uart->lcr);
+
+ return ret;
+}
+
+static int npcm_serial_probe(struct udevice *dev)
+{
+ struct npcm_serial_plat *plat = dev_get_plat(dev);
+ struct npcm_uart *const uart = plat->reg;
+ struct clk clk;
+ u32 freq;
+ int ret;
+
+ plat->reg = (struct npcm_uart *)dev_read_addr_ptr(dev);
+ freq = dev_read_u32_default(dev, "clock-frequency", 0);
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ printf("Cannot get clk for uart\n");
+ return ret;
+ }
+ ret = clk_set_rate(&clk, freq);
+ if (ret < 0)
+ return ret;
+ plat->uart_clk = ret;
+
+ npcm_serial_init(uart);
+
+ return 0;
+}
+
+static const struct dm_serial_ops npcm_serial_ops = {
+ .getc = npcm_serial_getc,
+ .setbrg = npcm_serial_setbrg,
+ .putc = npcm_serial_putc,
+ .pending = npcm_serial_pending,
+};
+
+static const struct udevice_id npcm_serial_ids[] = {
+ { .compatible = "nuvoton,npcm750-uart" },
+ { .compatible = "nuvoton,npcm845-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_npcm) = {
+ .name = "serial_npcm",
+ .id = UCLASS_SERIAL,
+ .of_match = npcm_serial_ids,
+ .plat_auto = sizeof(struct npcm_serial_plat),
+ .probe = npcm_serial_probe,
+ .ops = &npcm_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 5/9] gpio: npcm: Add support for Nuvoton NPCM SoCs
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
` (3 preceding siblings ...)
2021-12-15 2:57 ` [PATCH v1 4/9] serial: npcm: Add support for Nuvoton NPCM SoCs Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 2:57 ` [PATCH v1 6/9] pinctrl: nuvoton: Add NPCM8xx pinctrl driver Stanley Chu
` (3 subsequent siblings)
8 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
drivers/gpio/Kconfig | 7 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/npcm_gpio.c | 133 +++++++++++++++++++++++++++++++++++++++
3 files changed, 141 insertions(+)
create mode 100644 drivers/gpio/npcm_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 40abc33772..2aed8fdae3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -523,4 +523,11 @@ config NOMADIK_GPIO
into a number of banks each with 32 GPIOs. The GPIOs for a device are
defined in the device tree with one node for each bank.
+config NPCM_GPIO
+ bool "NuvoTon NPCM GPIO driver"
+ depends on DM_GPIO
+ help
+ Support GPIO controllers on NuvoTon NPCM SoCs.
+ It contains eight GPIO modules with total 256 pins.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3c851b38c7..d0206580c4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o
obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o
obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o
obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o
+obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o
diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c
new file mode 100644
index 0000000000..703d2e4815
--- /dev/null
+++ b/drivers/gpio/npcm_gpio.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define NPCM_GPIO_PORTS_PER_BANK 32
+
+#define NPCM_GPIO_REG_DIN 0x04 /* RO - Data In */
+#define NPCM_GPIO_REG_DOUT 0x0C /* RW - Data Out */
+#define NPCM_GPIO_REG_IEM 0x58 /* RW - Input Enable Mask */
+#define NPCM_GPIO_REG_OE 0x10 /* RW - Output Enable */
+#define NPCM_GPIO_REG_OES 0x70 /* WO - Output Enable Register Set */
+#define NPCM_GPIO_REG_OEC 0x74 /* WO - Output Enable Register Clear */
+
+struct npcm_gpio_priv {
+ void __iomem *base;
+};
+
+static void npcm_gpio_offset_write(struct udevice *dev, unsigned int offset,
+ unsigned int reg, int value)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+ u32 tmp;
+
+ tmp = readl(priv->base + reg);
+
+ if (value)
+ tmp |= BIT(offset);
+ else
+ tmp &= ~BIT(offset);
+
+ writel(tmp, priv->base + reg);
+}
+
+static int npcm_gpio_offset_read(struct udevice *dev, unsigned int offset,
+ unsigned int reg)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+
+ return !!(readl(priv->base + reg) & BIT(offset));
+}
+
+static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_OEC, 1);
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_IEM, 1);
+
+ return 0;
+}
+
+static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_IEM, 0);
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_OES, 1);
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_DOUT, value);
+
+ return 0;
+}
+
+static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_IEM))
+ return npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_DIN);
+
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_OE))
+ return npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_DOUT);
+
+ return -EINVAL;
+}
+
+static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ npcm_gpio_offset_write(dev, offset, NPCM_GPIO_REG_DOUT, value);
+
+ return 0;
+}
+
+static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_IEM))
+ return GPIOF_INPUT;
+
+ if (npcm_gpio_offset_read(dev, offset, NPCM_GPIO_REG_OE))
+ return GPIOF_OUTPUT;
+
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops npcm_gpio_ops = {
+ .direction_input = npcm_gpio_direction_input,
+ .direction_output = npcm_gpio_direction_output,
+ .get_value = npcm_gpio_get_value,
+ .set_value = npcm_gpio_set_value,
+ .get_function = npcm_gpio_get_function,
+};
+
+static int npcm_gpio_probe(struct udevice *dev)
+{
+ struct npcm_gpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ uc_priv->gpio_count = NPCM_GPIO_PORTS_PER_BANK;
+ uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
+
+ return 0;
+}
+
+static const struct udevice_id npcm_gpio_match[] = {
+ { .compatible = "nuvoton,npcm845-gpio" },
+ { .compatible = "nuvoton,npcm750-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(npcm_gpio) = {
+ .name = "npcm_gpio",
+ .id = UCLASS_GPIO,
+ .of_match = npcm_gpio_match,
+ .probe = npcm_gpio_probe,
+ .priv_auto = sizeof(struct npcm_gpio_priv),
+ .ops = &npcm_gpio_ops,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 6/9] pinctrl: nuvoton: Add NPCM8xx pinctrl driver
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
` (4 preceding siblings ...)
2021-12-15 2:57 ` [PATCH v1 5/9] gpio: " Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 2:57 ` [PATCH v1 7/9] spi: npcm-fiu: add NPCM8xx FIU controller driver Stanley Chu
` (2 subsequent siblings)
8 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/nuvoton/Kconfig | 6 +
drivers/pinctrl/nuvoton/Makefile | 1 +
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 2042 +++++++++++++++++++++
5 files changed, 2051 insertions(+)
create mode 100644 drivers/pinctrl/nuvoton/Kconfig
create mode 100644 drivers/pinctrl/nuvoton/Makefile
create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 30eaa376c8..276b7aaa56 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -313,5 +313,6 @@ source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 05b71f2f13..2c19eb00f5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o
obj-y += broadcom/
+obj-$(CONFIG_PINCTRL_NPCM8XX) += nuvoton/
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 0000000000..e7063f13ab
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,6 @@
+config PINCTRL_NPCM8XX
+ bool "Pinctrl and GPIO driver for Nuvoton NPCM8XX"
+ depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+ help
+ Say Y here to enable pin controller and GPIO support
+ for Nuvoton NPCM8xx SoCs.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 0000000000..b05aa62d33
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+ obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 0000000000..0252e80312
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,2042 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Nuvoton Technology Corp.
+ * Author: Joseph Liu <kwliu@nuvoton.com>
+ * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/gcr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rst.h>
+#include <dm/pinctrl.h>
+#include <dm/device_compat.h>
+
+/* GCR registers */
+#define NPCM8XX_GCR_PDID 0x00
+#define NPCM8XX_GCR_SRCNT 0x68
+#define NPCM8XX_GCR_FLOCKR1 0x74
+#define NPCM8XX_GCR_DSCNT 0x78
+#define NPCM8XX_GCR_INTCR4 0xC0
+#define NPCM8XX_GCR_I2CSEGCTL 0xE4
+#define NPCM8XX_GCR_I2CSEGSEL 0xE0
+#define NPCM8XX_GCR_MFSEL1 0x260
+#define NPCM8XX_GCR_MFSEL2 0x264
+#define NPCM8XX_GCR_MFSEL3 0x268
+#define NPCM8XX_GCR_MFSEL4 0x26C
+#define NPCM8XX_GCR_MFSEL5 0x270
+#define NPCM8XX_GCR_MFSEL6 0x274
+#define NPCM8XX_GCR_MFSEL7 0x278
+#define NPCM8XX_GCR_MFSEL7 0x278
+
+#define SRCNT_ESPI BIT(3)
+
+/* reset registers */
+#define NPCM8XX_RST_WD0RCR 0x38
+#define NPCM8XX_RST_WD1RCR 0x3C
+#define NPCM8XX_RST_WD2RCR 0x40
+#define NPCM8XX_RST_SWRSTC1 0x44
+#define NPCM8XX_RST_SWRSTC2 0x48
+#define NPCM8XX_RST_SWRSTC3 0x4C
+#define NPCM8XX_RST_SWRSTC4 0x50
+#define NPCM8XX_RST_CORSTC 0x5C
+
+#define GPIOX_MODULE_RESET 16
+#define CA9C_MODULE_RESET BIT(0)
+
+/* GPIO registers */
+#define NPCM8XX_GP_N_TLOCK1 0x00
+#define NPCM8XX_GP_N_DIN 0x04 /* Data IN */
+#define NPCM8XX_GP_N_POL 0x08 /* Polarity */
+#define NPCM8XX_GP_N_DOUT 0x0c /* Data OUT */
+#define NPCM8XX_GP_N_OE 0x10 /* Output Enable */
+#define NPCM8XX_GP_N_OTYP 0x14
+#define NPCM8XX_GP_N_MP 0x18
+#define NPCM8XX_GP_N_PU 0x1c /* Pull-up */
+#define NPCM8XX_GP_N_PD 0x20 /* Pull-down */
+#define NPCM8XX_GP_N_DBNC 0x24 /* Debounce */
+#define NPCM8XX_GP_N_EVTYP 0x28 /* Event Type */
+#define NPCM8XX_GP_N_EVBE 0x2c /* Event Both Edge */
+#define NPCM8XX_GP_N_OBL0 0x30
+#define NPCM8XX_GP_N_OBL1 0x34
+#define NPCM8XX_GP_N_OBL2 0x38
+#define NPCM8XX_GP_N_OBL3 0x3c
+#define NPCM8XX_GP_N_EVEN 0x40 /* Event Enable */
+#define NPCM8XX_GP_N_EVENS 0x44 /* Event Set (enable) */
+#define NPCM8XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
+#define NPCM8XX_GP_N_EVST 0x4c /* Event Status */
+#define NPCM8XX_GP_N_SPLCK 0x50
+#define NPCM8XX_GP_N_MPLCK 0x54
+#define NPCM8XX_GP_N_IEM 0x58 /* Input Enable */
+#define NPCM8XX_GP_N_OSRC 0x5c
+#define NPCM8XX_GP_N_ODSC 0x60
+#define NPCM8XX_GP_N_DOS 0x68 /* Data OUT Set */
+#define NPCM8XX_GP_N_DOC 0x6c /* Data OUT Clear */
+#define NPCM8XX_GP_N_OES 0x70 /* Output Enable Set */
+#define NPCM8XX_GP_N_OEC 0x74 /* Output Enable Clear */
+#define NPCM8XX_GP_N_DBNCS0 0x80
+#define NPCM8XX_GP_N_DBNCS1 0x84
+#define NPCM8XX_GP_N_DBNCP0 0x88
+#define NPCM8XX_GP_N_DBNCP1 0x8C
+#define NPCM8XX_GP_N_DBNCP2 0x90
+#define NPCM8XX_GP_N_DBNCP3 0x94
+#define NPCM8XX_GP_N_TLOCK2 0xAC
+
+#define NPCM8XX_GPIO_BANK_OFFSET 0x1000
+#define NPCM8XX_GPIO_PER_BITS 32
+#define NPCM8XX_GPIO_PER_BANK 32
+#define NPCM8XX_GPIO_BANK_NUM 8
+#define NPCM8XX_GCR_NONE 0
+/* not gpio */
+static const unsigned int gpi35_pins[] = { 35 };
+static const unsigned int gpi36_pins[] = { 36 };
+
+static const unsigned int tp_jtag3_pins[] = { 44, 62, 45, 46 };
+static const unsigned int tp_uart_pins[] = { 50, 51 };
+
+static const unsigned int tp_smb2_pins[] = { 24, 25 };
+static const unsigned int tp_smb1_pins[] = { 142, 143 };
+
+static const unsigned int tp_gpio7_pins[] = { 96 };
+static const unsigned int tp_gpio6_pins[] = { 97 };
+static const unsigned int tp_gpio5_pins[] = { 98 };
+static const unsigned int tp_gpio4_pins[] = { 99 };
+static const unsigned int tp_gpio3_pins[] = { 100 };
+static const unsigned int tp_gpio2_pins[] = { 16 };
+static const unsigned int tp_gpio1_pins[] = { 9 };
+static const unsigned int tp_gpio0_pins[] = { 8 };
+
+static const unsigned int tp_gpio2b_pins[] = { 101 };
+static const unsigned int tp_gpio1b_pins[] = { 92 };
+static const unsigned int tp_gpio0b_pins[] = { 91 };
+
+static const unsigned int vgadig_pins[] = { 102, 103, 104, 105 };
+
+static const unsigned int nbu1crts_pins[] = { 44, 62 };
+
+static const unsigned int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 };
+static const unsigned int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 };
+static const unsigned int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 };
+
+static const unsigned int gpio1836_pins[] = { 183, 184, 185, 186 };
+static const unsigned int gpio1889_pins[] = { 188, 189 };
+static const unsigned int gpio187_pins[] = { 187 };
+
+static const unsigned int cp1urxd_pins[] = { 41 };
+static const unsigned int r3rxer_pins[] = { 212 };
+
+static const unsigned int cp1gpio2c_pins[] = { 101 };
+static const unsigned int cp1gpio3c_pins[] = { 100 };
+
+static const unsigned int cp1gpio0b_pins[] = { 127 };
+static const unsigned int cp1gpio1b_pins[] = { 126 };
+static const unsigned int cp1gpio2b_pins[] = { 125 };
+static const unsigned int cp1gpio3b_pins[] = { 124 };
+static const unsigned int cp1gpio4b_pins[] = { 99 };
+static const unsigned int cp1gpio5b_pins[] = { 98 };
+static const unsigned int cp1gpio6b_pins[] = { 97 };
+static const unsigned int cp1gpio7b_pins[] = { 96 };
+
+static const unsigned int cp1gpio0_pins[] = { };
+static const unsigned int cp1gpio1_pins[] = { };
+static const unsigned int cp1gpio2_pins[] = { };
+static const unsigned int cp1gpio3_pins[] = { };
+static const unsigned int cp1gpio4_pins[] = { };
+static const unsigned int cp1gpio5_pins[] = { 17 };
+static const unsigned int cp1gpio6_pins[] = { 91 };
+static const unsigned int cp1gpio7_pins[] = { 92 };
+
+static const unsigned int cp1utxd_pins[] = { 42 };
+
+static const unsigned int j2j3_pins[] = { 44, 62, 45, 46 };
+
+static const unsigned int r3oen_pins[] = { 58 };
+static const unsigned int r2oen_pins[] = { 90, 249 };
+static const unsigned int r1oen_pins[] = { 56 };
+static const unsigned int bu4b_pins[] = { 98, 99 };
+static const unsigned int bu4_pins[] = { 54, 55 };
+static const unsigned int bu5b_pins[] = { 100, 101 };
+static const unsigned int bu5_pins[] = { 52, 53 };
+static const unsigned int bu6_pins[] = { 50, 51 };
+static const unsigned int rmii3_pins[] = { 110, 111, 209, 212, 211, 210, 214, 215 };
+
+static const unsigned int jm1_pins[] = { 136, 137, 138, 139, 140 };
+static const unsigned int jm2_pins[] = { 0, 1, 2, 3 };
+
+static const unsigned int tpgpio5b_pins[] = { 58 };
+static const unsigned int tpgpio4b_pins[] = { 57 };
+
+static const unsigned int clkrun_pins[] = { 162 };
+
+static const unsigned int i3c5_pins[] = { 106, 107 };
+static const unsigned int i3c4_pins[] = { 33, 34 };
+static const unsigned int i3c3_pins[] = { 246, 247 };
+static const unsigned int i3c2_pins[] = { 244, 245 };
+static const unsigned int i3c1_pins[] = { 242, 243 };
+static const unsigned int i3c0_pins[] = { 240, 241 };
+
+static const unsigned int hsi1a_pins[] = { 43, 63 };
+static const unsigned int hsi2a_pins[] = { 48, 49 };
+
+static const unsigned int hsi1b_pins[] = { 44, 62 };
+static const unsigned int hsi2b_pins[] = { 50, 51 };
+
+static const unsigned int hsi1c_pins[] = { 45, 46, 47, 61 };
+static const unsigned int hsi2c_pins[] = { 45, 46, 47, 61 };
+
+/* pinmux handing in the pinctrl driver*/
+static const unsigned int smb0_pins[] = { 115, 114 };
+static const unsigned int smb0b_pins[] = { 195, 194 };
+static const unsigned int smb0c_pins[] = { 202, 196 };
+static const unsigned int smb0d_pins[] = { 198, 199 };
+static const unsigned int smb0den_pins[] = { 197 };
+
+static const unsigned int smb1_pins[] = { 117, 116 };
+static const unsigned int smb1b_pins[] = { 126, 127 };
+static const unsigned int smb1c_pins[] = { 124, 125 };
+static const unsigned int smb1d_pins[] = { 4, 5 };
+
+static const unsigned int smb2_pins[] = { 119, 118 };
+static const unsigned int smb2b_pins[] = { 122, 123 };
+static const unsigned int smb2c_pins[] = { 120, 121 };
+static const unsigned int smb2d_pins[] = { 6, 7 };
+
+static const unsigned int smb3_pins[] = { 30, 31 };
+static const unsigned int smb3b_pins[] = { 39, 40 };
+static const unsigned int smb3c_pins[] = { 37, 38 };
+static const unsigned int smb3d_pins[] = { 59, 60 };
+
+static const unsigned int smb4_pins[] = { 28, 29 };
+static const unsigned int smb4b_pins[] = { 18, 19 };
+static const unsigned int smb4c_pins[] = { 20, 21 };
+static const unsigned int smb4d_pins[] = { 22, 23 };
+static const unsigned int smb4den_pins[] = { 17 };
+
+static const unsigned int smb5_pins[] = { 26, 27 };
+static const unsigned int smb5b_pins[] = { 13, 12 };
+static const unsigned int smb5c_pins[] = { 15, 14 };
+static const unsigned int smb5d_pins[] = { 94, 93 };
+static const unsigned int ga20kbc_pins[] = { 94, 93 };
+
+static const unsigned int smb6_pins[] = { 172, 171 };
+static const unsigned int smb6b_pins[] = { 2, 3 };
+static const unsigned int smb6c_pins[] = { 0, 1 };
+static const unsigned int smb6d_pins[] = { 10, 11 };
+static const unsigned int smb7_pins[] = { 174, 173 };
+static const unsigned int smb7b_pins[] = { 16, 141 };
+static const unsigned int smb7c_pins[] = { 24, 25 };
+static const unsigned int smb7d_pins[] = { 142, 143 };
+static const unsigned int smb8_pins[] = { 129, 128 };
+static const unsigned int smb9_pins[] = { 131, 130 };
+static const unsigned int smb10_pins[] = { 133, 132 };
+static const unsigned int smb11_pins[] = { 135, 134 };
+static const unsigned int smb12_pins[] = { 221, 220 };
+static const unsigned int smb13_pins[] = { 223, 222 };
+static const unsigned int smb14_pins[] = { 22, 23 };
+static const unsigned int smb14b_pins[] = { 32, 187 };
+static const unsigned int smb15_pins[] = { 20, 21 };
+static const unsigned int smb15b_pins[] = { 192, 191 };
+
+static const unsigned int smb16_pins[] = { 10, 11 };
+static const unsigned int smb16b_pins[] = { 218, 219 };
+static const unsigned int smb17_pins[] = { 3, 2 };
+static const unsigned int smb18_pins[] = { 0, 1 };
+static const unsigned int smb19_pins[] = { 60, 59 };
+static const unsigned int smb20_pins[] = { 234, 235 };
+static const unsigned int smb21_pins[] = { 169, 170 };
+static const unsigned int smb22_pins[] = { 40, 39 };
+static const unsigned int smb23_pins[] = { 38, 37 };
+static const unsigned int smb23b_pins[] = { 134, 134 };
+
+static const unsigned int fanin0_pins[] = { 64 };
+static const unsigned int fanin1_pins[] = { 65 };
+static const unsigned int fanin2_pins[] = { 66 };
+static const unsigned int fanin3_pins[] = { 67 };
+static const unsigned int fanin4_pins[] = { 68 };
+static const unsigned int fanin5_pins[] = { 69 };
+static const unsigned int fanin6_pins[] = { 70 };
+static const unsigned int fanin7_pins[] = { 71 };
+static const unsigned int fanin8_pins[] = { 72 };
+static const unsigned int fanin9_pins[] = { 73 };
+static const unsigned int fanin10_pins[] = { 74 };
+static const unsigned int fanin11_pins[] = { 75 };
+static const unsigned int fanin12_pins[] = { 76 };
+static const unsigned int fanin13_pins[] = { 77 };
+static const unsigned int fanin14_pins[] = { 78 };
+static const unsigned int fanin15_pins[] = { 79 };
+static const unsigned int faninx_pins[] = { 175, 176, 177, 203 };
+
+static const unsigned int pwm0_pins[] = { 80 };
+static const unsigned int pwm1_pins[] = { 81 };
+static const unsigned int pwm2_pins[] = { 82 };
+static const unsigned int pwm3_pins[] = { 83 };
+static const unsigned int pwm4_pins[] = { 144 };
+static const unsigned int pwm5_pins[] = { 145 };
+static const unsigned int pwm6_pins[] = { 146 };
+static const unsigned int pwm7_pins[] = { 147 };
+static const unsigned int pwm8_pins[] = { 220 };
+static const unsigned int pwm9_pins[] = { 221 };
+static const unsigned int pwm10_pins[] = { 234 };
+static const unsigned int pwm11_pins[] = { 235 };
+
+static const unsigned int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
+static const unsigned int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
+
+static const unsigned int bu2_pins[] = { 96, 97};
+
+/* RGMII 1 MD interface pin group */
+static const unsigned int sg1mdio_pins[] = { 108, 109 };
+
+/* RGMII 2 pin group */
+static const unsigned int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
+ 213, 214, 215 };
+/* RGMII 2 refck pin group */
+static const unsigned int rg2refck_pins[] = { 250 };
+
+/* RGMII 2 MD interface pin group */
+static const unsigned int rg2mdio_pins[] = { 216, 217 };
+
+static const unsigned int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
+ 213, 214, 215, 216, 217, 250 };
+/* Serial I/O Expander 1 */
+static const unsigned int iox1_pins[] = { 0, 1, 2, 3 };
+/* Serial I/O Expander 2 */
+static const unsigned int iox2_pins[] = { 4, 5, 6, 7 };
+/* Host Serial I/O Expander 2 */
+static const unsigned int ioxh_pins[] = { 10, 11, 24, 25 };
+
+static const unsigned int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
+static const unsigned int mmcwp_pins[] = { 153 };
+static const unsigned int mmccd_pins[] = { 155 };
+static const unsigned int mmcrst_pins[] = { 155 };
+static const unsigned int mmc8_pins[] = { 148, 149, 150, 151 };
+
+/* RMII 1 pin groups */
+static const unsigned int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
+static const unsigned int r1err_pins[] = { 56 };
+static const unsigned int r1md_pins[] = { 57, 58 };
+
+/* RMII 2 pin groups */
+static const unsigned int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
+static const unsigned int r2err_pins[] = { 90 };
+static const unsigned int r2md_pins[] = { 91, 92 };
+
+static const unsigned int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
+static const unsigned int sd1pwr_pins[] = { 143 };
+
+static const unsigned int wdog1_pins[] = { 218 };
+static const unsigned int wdog2_pins[] = { 219 };
+
+/* BMC serial port 0 */
+static const unsigned int bmcuart0a_pins[] = { 41, 42 };
+static const unsigned int bmcuart0b_pins[] = { 48, 49 };
+
+static const unsigned int bmcuart1_pins[] = { 43, 63 };
+
+/* System Control Interrupt and Power Management Event pin group */
+static const unsigned int scipme_pins[] = { 169 };
+/* System Management Interrupt pin group */
+static const unsigned int sci_pins[] = { 170 };
+/* Serial Interrupt Line pin group */
+static const unsigned int serirq_pins[] = { 168 };
+
+static const unsigned int clkout_pins[] = { 160 };
+static const unsigned int clkreq_pins[] = { 231 };
+
+static const unsigned int jtag2_pins[] = { 43, 44, 45, 46, 47 };
+/* Graphics SPI Clock pin group */
+static const unsigned int gspi_pins[] = { 12, 13, 14, 15 };
+
+static const unsigned int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
+static const unsigned int spixcs1_pins[] = { 228 };
+
+static const unsigned int pspi_pins[] = { 17, 18, 19 };
+
+static const unsigned int spi0cs1_pins[] = { 32 };
+
+static const unsigned int spi1_pins[] = { 175, 176, 177, 203 };
+static const unsigned int spi1cs1_pins[] = { 233 };
+static const unsigned int spi1d23_pins[] = { 191, 192 };
+static const unsigned int spi1cs2_pins[] = { 191 };
+static const unsigned int spi1cs3_pins[] = { 192 };
+
+static const unsigned int spi3_pins[] = { 183, 184, 185, 186 };
+static const unsigned int spi3cs1_pins[] = { 187 };
+static const unsigned int spi3quad_pins[] = { 188, 189 };
+static const unsigned int spi3cs2_pins[] = { 188 };
+static const unsigned int spi3cs3_pins[] = { 189 };
+
+static const unsigned int ddc_pins[] = { 204, 205, 206, 207 };
+
+static const unsigned int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
+static const unsigned int lpcclk_pins[] = { 168 };
+static const unsigned int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
+
+static const unsigned int lkgpo0_pins[] = { 16 };
+static const unsigned int lkgpo1_pins[] = { 8 };
+static const unsigned int lkgpo2_pins[] = { 9 };
+
+static const unsigned int nprd_smi_pins[] = { 190 };
+
+static const unsigned int hgpio0_pins[] = { 20 };
+static const unsigned int hgpio1_pins[] = { 21 };
+static const unsigned int hgpio2_pins[] = { 22 };
+static const unsigned int hgpio3_pins[] = { 23 };
+static const unsigned int hgpio4_pins[] = { 24 };
+static const unsigned int hgpio5_pins[] = { 25 };
+static const unsigned int hgpio6_pins[] = { 59 };
+static const unsigned int hgpio7_pins[] = { 60 };
+
+/*
+ * pin: name, number
+ * group: name, npins, pins
+ * function: name, ngroups, groups
+ */
+struct npcm8xx_group {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int npins;
+};
+
+#define NPCM8XX_GRPS \
+ NPCM8XX_GRP(gpi35), \
+ NPCM8XX_GRP(gpi36), \
+ NPCM8XX_GRP(tp_jtag3), \
+ NPCM8XX_GRP(tp_uart), \
+ NPCM8XX_GRP(tp_smb2), \
+ NPCM8XX_GRP(tp_smb1), \
+ NPCM8XX_GRP(tp_gpio7), \
+ NPCM8XX_GRP(tp_gpio6), \
+ NPCM8XX_GRP(tp_gpio5), \
+ NPCM8XX_GRP(tp_gpio4), \
+ NPCM8XX_GRP(tp_gpio3), \
+ NPCM8XX_GRP(tp_gpio2), \
+ NPCM8XX_GRP(tp_gpio1), \
+ NPCM8XX_GRP(tp_gpio0), \
+ NPCM8XX_GRP(tp_gpio2b), \
+ NPCM8XX_GRP(tp_gpio1b), \
+ NPCM8XX_GRP(tp_gpio0b), \
+ NPCM8XX_GRP(vgadig), \
+ NPCM8XX_GRP(nbu1crts), \
+ NPCM8XX_GRP(fm2), \
+ NPCM8XX_GRP(fm1), \
+ NPCM8XX_GRP(fm0), \
+ NPCM8XX_GRP(gpio1836), \
+ NPCM8XX_GRP(gpio1889), \
+ NPCM8XX_GRP(gpio187), \
+ NPCM8XX_GRP(cp1urxd), \
+ NPCM8XX_GRP(r3rxer), \
+ NPCM8XX_GRP(cp1gpio2c), \
+ NPCM8XX_GRP(cp1gpio3c), \
+ NPCM8XX_GRP(cp1gpio0b), \
+ NPCM8XX_GRP(cp1gpio1b), \
+ NPCM8XX_GRP(cp1gpio2b), \
+ NPCM8XX_GRP(cp1gpio3b), \
+ NPCM8XX_GRP(cp1gpio4b), \
+ NPCM8XX_GRP(cp1gpio5b), \
+ NPCM8XX_GRP(cp1gpio6b), \
+ NPCM8XX_GRP(cp1gpio7b), \
+ NPCM8XX_GRP(cp1gpio0), \
+ NPCM8XX_GRP(cp1gpio1), \
+ NPCM8XX_GRP(cp1gpio2), \
+ NPCM8XX_GRP(cp1gpio3), \
+ NPCM8XX_GRP(cp1gpio4), \
+ NPCM8XX_GRP(cp1gpio5), \
+ NPCM8XX_GRP(cp1gpio6), \
+ NPCM8XX_GRP(cp1gpio7), \
+ NPCM8XX_GRP(cp1utxd), \
+ NPCM8XX_GRP(spi1cs3), \
+ NPCM8XX_GRP(spi1cs2), \
+ NPCM8XX_GRP(spi1cs1), \
+ NPCM8XX_GRP(spi1), \
+ NPCM8XX_GRP(spi1d23), \
+ NPCM8XX_GRP(j2j3), \
+ NPCM8XX_GRP(r3oen), \
+ NPCM8XX_GRP(r2oen), \
+ NPCM8XX_GRP(r1oen), \
+ NPCM8XX_GRP(bu4b), \
+ NPCM8XX_GRP(bu4), \
+ NPCM8XX_GRP(bu5b), \
+ NPCM8XX_GRP(bu5), \
+ NPCM8XX_GRP(bu6), \
+ NPCM8XX_GRP(rmii3), \
+ NPCM8XX_GRP(jm1), \
+ NPCM8XX_GRP(jm2), \
+ NPCM8XX_GRP(tpgpio5b), \
+ NPCM8XX_GRP(tpgpio4b), \
+ NPCM8XX_GRP(clkrun), \
+ NPCM8XX_GRP(i3c5), \
+ NPCM8XX_GRP(i3c4), \
+ NPCM8XX_GRP(i3c3), \
+ NPCM8XX_GRP(i3c2), \
+ NPCM8XX_GRP(i3c1), \
+ NPCM8XX_GRP(i3c0), \
+ NPCM8XX_GRP(hsi1a), \
+ NPCM8XX_GRP(hsi2a), \
+ NPCM8XX_GRP(hsi1b), \
+ NPCM8XX_GRP(hsi2b), \
+ NPCM8XX_GRP(hsi1c), \
+ NPCM8XX_GRP(hsi2c), \
+ NPCM8XX_GRP(smb0), \
+ NPCM8XX_GRP(smb0b), \
+ NPCM8XX_GRP(smb0c), \
+ NPCM8XX_GRP(smb0d), \
+ NPCM8XX_GRP(smb0den), \
+ NPCM8XX_GRP(smb1), \
+ NPCM8XX_GRP(smb1b), \
+ NPCM8XX_GRP(smb1c), \
+ NPCM8XX_GRP(smb1d), \
+ NPCM8XX_GRP(smb2), \
+ NPCM8XX_GRP(smb2b), \
+ NPCM8XX_GRP(smb2c), \
+ NPCM8XX_GRP(smb2d), \
+ NPCM8XX_GRP(smb3), \
+ NPCM8XX_GRP(smb3b), \
+ NPCM8XX_GRP(smb3c), \
+ NPCM8XX_GRP(smb3d), \
+ NPCM8XX_GRP(smb4), \
+ NPCM8XX_GRP(smb4b), \
+ NPCM8XX_GRP(smb4c), \
+ NPCM8XX_GRP(smb4d), \
+ NPCM8XX_GRP(smb4den), \
+ NPCM8XX_GRP(smb5), \
+ NPCM8XX_GRP(smb5b), \
+ NPCM8XX_GRP(smb5c), \
+ NPCM8XX_GRP(smb5d), \
+ NPCM8XX_GRP(ga20kbc), \
+ NPCM8XX_GRP(smb6), \
+ NPCM8XX_GRP(smb6b), \
+ NPCM8XX_GRP(smb6c), \
+ NPCM8XX_GRP(smb6d), \
+ NPCM8XX_GRP(smb7), \
+ NPCM8XX_GRP(smb7b), \
+ NPCM8XX_GRP(smb7c), \
+ NPCM8XX_GRP(smb7d), \
+ NPCM8XX_GRP(smb8), \
+ NPCM8XX_GRP(smb9), \
+ NPCM8XX_GRP(smb10), \
+ NPCM8XX_GRP(smb11), \
+ NPCM8XX_GRP(smb12), \
+ NPCM8XX_GRP(smb13), \
+ NPCM8XX_GRP(smb14), \
+ NPCM8XX_GRP(smb14b), \
+ NPCM8XX_GRP(smb15), \
+ NPCM8XX_GRP(smb15b), \
+ NPCM8XX_GRP(smb16), \
+ NPCM8XX_GRP(smb16b), \
+ NPCM8XX_GRP(smb17), \
+ NPCM8XX_GRP(smb18), \
+ NPCM8XX_GRP(smb19), \
+ NPCM8XX_GRP(smb20), \
+ NPCM8XX_GRP(smb21), \
+ NPCM8XX_GRP(smb22), \
+ NPCM8XX_GRP(smb23), \
+ NPCM8XX_GRP(smb23b), \
+ NPCM8XX_GRP(fanin0), \
+ NPCM8XX_GRP(fanin1), \
+ NPCM8XX_GRP(fanin2), \
+ NPCM8XX_GRP(fanin3), \
+ NPCM8XX_GRP(fanin4), \
+ NPCM8XX_GRP(fanin5), \
+ NPCM8XX_GRP(fanin6), \
+ NPCM8XX_GRP(fanin7), \
+ NPCM8XX_GRP(fanin8), \
+ NPCM8XX_GRP(fanin9), \
+ NPCM8XX_GRP(fanin10), \
+ NPCM8XX_GRP(fanin11), \
+ NPCM8XX_GRP(fanin12), \
+ NPCM8XX_GRP(fanin13), \
+ NPCM8XX_GRP(fanin14), \
+ NPCM8XX_GRP(fanin15), \
+ NPCM8XX_GRP(faninx), \
+ NPCM8XX_GRP(pwm0), \
+ NPCM8XX_GRP(pwm1), \
+ NPCM8XX_GRP(pwm2), \
+ NPCM8XX_GRP(pwm3), \
+ NPCM8XX_GRP(pwm4), \
+ NPCM8XX_GRP(pwm5), \
+ NPCM8XX_GRP(pwm6), \
+ NPCM8XX_GRP(pwm7), \
+ NPCM8XX_GRP(pwm8), \
+ NPCM8XX_GRP(pwm9), \
+ NPCM8XX_GRP(pwm10), \
+ NPCM8XX_GRP(pwm11), \
+ NPCM8XX_GRP(bu2), \
+ NPCM8XX_GRP(sg1mdio), \
+ NPCM8XX_GRP(rg2), \
+ NPCM8XX_GRP(rg2refck), \
+ NPCM8XX_GRP(rg2mdio), \
+ NPCM8XX_GRP(ddr), \
+ NPCM8XX_GRP(uart1), \
+ NPCM8XX_GRP(uart2), \
+ NPCM8XX_GRP(bmcuart0a), \
+ NPCM8XX_GRP(bmcuart0b), \
+ NPCM8XX_GRP(bmcuart1), \
+ NPCM8XX_GRP(iox1), \
+ NPCM8XX_GRP(iox2), \
+ NPCM8XX_GRP(ioxh), \
+ NPCM8XX_GRP(gspi), \
+ NPCM8XX_GRP(mmc), \
+ NPCM8XX_GRP(mmcwp), \
+ NPCM8XX_GRP(mmccd), \
+ NPCM8XX_GRP(mmcrst), \
+ NPCM8XX_GRP(mmc8), \
+ NPCM8XX_GRP(r1), \
+ NPCM8XX_GRP(r1err), \
+ NPCM8XX_GRP(r1md), \
+ NPCM8XX_GRP(r2), \
+ NPCM8XX_GRP(r2err), \
+ NPCM8XX_GRP(r2md), \
+ NPCM8XX_GRP(sd1), \
+ NPCM8XX_GRP(sd1pwr), \
+ NPCM8XX_GRP(wdog1), \
+ NPCM8XX_GRP(wdog2), \
+ NPCM8XX_GRP(scipme), \
+ NPCM8XX_GRP(sci), \
+ NPCM8XX_GRP(serirq), \
+ NPCM8XX_GRP(jtag2), \
+ NPCM8XX_GRP(spix), \
+ NPCM8XX_GRP(spixcs1), \
+ NPCM8XX_GRP(pspi), \
+ NPCM8XX_GRP(ddc), \
+ NPCM8XX_GRP(clkreq), \
+ NPCM8XX_GRP(clkout), \
+ NPCM8XX_GRP(spi3), \
+ NPCM8XX_GRP(spi3cs1), \
+ NPCM8XX_GRP(spi3quad), \
+ NPCM8XX_GRP(spi3cs2), \
+ NPCM8XX_GRP(spi3cs3), \
+ NPCM8XX_GRP(spi0cs1), \
+ NPCM8XX_GRP(lpc), \
+ NPCM8XX_GRP(lpcclk), \
+ NPCM8XX_GRP(espi), \
+ NPCM8XX_GRP(lkgpo0), \
+ NPCM8XX_GRP(lkgpo1), \
+ NPCM8XX_GRP(lkgpo2), \
+ NPCM8XX_GRP(nprd_smi), \
+ NPCM8XX_GRP(hgpio0), \
+ NPCM8XX_GRP(hgpio1), \
+ NPCM8XX_GRP(hgpio2), \
+ NPCM8XX_GRP(hgpio3), \
+ NPCM8XX_GRP(hgpio4), \
+ NPCM8XX_GRP(hgpio5), \
+ NPCM8XX_GRP(hgpio6), \
+ NPCM8XX_GRP(hgpio7), \
+ \
+
+enum {
+#define NPCM8XX_GRP(x) fn_ ## x
+ NPCM8XX_GRPS
+ /* add placeholder for none/gpio */
+ NPCM8XX_GRP(none),
+ NPCM8XX_GRP(gpio),
+#undef NPCM8XX_GRP
+};
+
+static struct npcm8xx_group npcm8xx_groups[] = {
+#define NPCM8XX_GRP(x) { .name = #x, .pins = x ## _pins, \
+ .npins = ARRAY_SIZE(x ## _pins) }
+ NPCM8XX_GRPS
+#undef NPCM8XX_GRP
+};
+
+#define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a)
+#define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
+#define NPCM8XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
+ .groups = nm ## _grp }
+struct npcm8xx_func {
+ const char *name;
+ const unsigned int ngroups;
+ const char *const *groups;
+};
+
+NPCM8XX_SFUNC(gpi35);
+NPCM8XX_SFUNC(gpi36);
+NPCM8XX_SFUNC(tp_jtag3);
+NPCM8XX_SFUNC(tp_uart);
+NPCM8XX_SFUNC(tp_smb2);
+NPCM8XX_SFUNC(tp_smb1);
+NPCM8XX_SFUNC(tp_gpio7);
+NPCM8XX_SFUNC(tp_gpio6);
+NPCM8XX_SFUNC(tp_gpio5);
+NPCM8XX_SFUNC(tp_gpio4);
+NPCM8XX_SFUNC(tp_gpio3);
+NPCM8XX_SFUNC(tp_gpio2);
+NPCM8XX_SFUNC(tp_gpio1);
+NPCM8XX_SFUNC(tp_gpio0);
+NPCM8XX_SFUNC(tp_gpio2b);
+NPCM8XX_SFUNC(tp_gpio1b);
+NPCM8XX_SFUNC(tp_gpio0b);
+NPCM8XX_SFUNC(vgadig);
+NPCM8XX_SFUNC(nbu1crts);
+NPCM8XX_SFUNC(fm2);
+NPCM8XX_SFUNC(fm1);
+NPCM8XX_SFUNC(fm0);
+NPCM8XX_SFUNC(gpio1836);
+NPCM8XX_SFUNC(gpio1889);
+NPCM8XX_SFUNC(gpio187);
+NPCM8XX_SFUNC(cp1urxd);
+NPCM8XX_SFUNC(r3rxer);
+NPCM8XX_SFUNC(cp1gpio2c);
+NPCM8XX_SFUNC(cp1gpio3c);
+NPCM8XX_SFUNC(cp1gpio0b);
+NPCM8XX_SFUNC(cp1gpio1b);
+NPCM8XX_SFUNC(cp1gpio2b);
+NPCM8XX_SFUNC(cp1gpio3b);
+NPCM8XX_SFUNC(cp1gpio4b);
+NPCM8XX_SFUNC(cp1gpio5b);
+NPCM8XX_SFUNC(cp1gpio6b);
+NPCM8XX_SFUNC(cp1gpio7b);
+NPCM8XX_SFUNC(cp1gpio0);
+NPCM8XX_SFUNC(cp1gpio1);
+NPCM8XX_SFUNC(cp1gpio2);
+NPCM8XX_SFUNC(cp1gpio3);
+NPCM8XX_SFUNC(cp1gpio4);
+NPCM8XX_SFUNC(cp1gpio5);
+NPCM8XX_SFUNC(cp1gpio6);
+NPCM8XX_SFUNC(cp1gpio7);
+NPCM8XX_SFUNC(cp1utxd);
+NPCM8XX_SFUNC(spi1cs3);
+NPCM8XX_SFUNC(spi1cs2);
+NPCM8XX_SFUNC(spi1cs1);
+NPCM8XX_SFUNC(spi1);
+NPCM8XX_SFUNC(spi1d23);
+NPCM8XX_SFUNC(j2j3);
+NPCM8XX_SFUNC(r3oen);
+NPCM8XX_SFUNC(r2oen);
+NPCM8XX_SFUNC(r1oen);
+NPCM8XX_SFUNC(bu4b);
+NPCM8XX_SFUNC(bu4);
+NPCM8XX_SFUNC(bu5b);
+NPCM8XX_SFUNC(bu5);
+NPCM8XX_SFUNC(bu6);
+NPCM8XX_SFUNC(rmii3);
+NPCM8XX_SFUNC(jm1);
+NPCM8XX_SFUNC(jm2);
+NPCM8XX_SFUNC(tpgpio5b);
+NPCM8XX_SFUNC(tpgpio4b);
+NPCM8XX_SFUNC(clkrun);
+NPCM8XX_SFUNC(i3c5);
+NPCM8XX_SFUNC(i3c4);
+NPCM8XX_SFUNC(i3c3);
+NPCM8XX_SFUNC(i3c2);
+NPCM8XX_SFUNC(i3c1);
+NPCM8XX_SFUNC(i3c0);
+NPCM8XX_SFUNC(hsi1a);
+NPCM8XX_SFUNC(hsi2a);
+NPCM8XX_SFUNC(hsi1b);
+NPCM8XX_SFUNC(hsi2b);
+NPCM8XX_SFUNC(hsi1c);
+NPCM8XX_SFUNC(hsi2c);
+NPCM8XX_SFUNC(smb0);
+NPCM8XX_SFUNC(smb0b);
+NPCM8XX_SFUNC(smb0c);
+NPCM8XX_SFUNC(smb0d);
+NPCM8XX_SFUNC(smb0den);
+NPCM8XX_SFUNC(smb1);
+NPCM8XX_SFUNC(smb1b);
+NPCM8XX_SFUNC(smb1c);
+NPCM8XX_SFUNC(smb1d);
+NPCM8XX_SFUNC(smb2);
+NPCM8XX_SFUNC(smb2b);
+NPCM8XX_SFUNC(smb2c);
+NPCM8XX_SFUNC(smb2d);
+NPCM8XX_SFUNC(smb3);
+NPCM8XX_SFUNC(smb3b);
+NPCM8XX_SFUNC(smb3c);
+NPCM8XX_SFUNC(smb3d);
+NPCM8XX_SFUNC(smb4);
+NPCM8XX_SFUNC(smb4b);
+NPCM8XX_SFUNC(smb4c);
+NPCM8XX_SFUNC(smb4d);
+NPCM8XX_SFUNC(smb4den);
+NPCM8XX_SFUNC(smb5);
+NPCM8XX_SFUNC(smb5b);
+NPCM8XX_SFUNC(smb5c);
+NPCM8XX_SFUNC(smb5d);
+NPCM8XX_SFUNC(ga20kbc);
+NPCM8XX_SFUNC(smb6);
+NPCM8XX_SFUNC(smb6b);
+NPCM8XX_SFUNC(smb6c);
+NPCM8XX_SFUNC(smb6d);
+NPCM8XX_SFUNC(smb7);
+NPCM8XX_SFUNC(smb7b);
+NPCM8XX_SFUNC(smb7c);
+NPCM8XX_SFUNC(smb7d);
+NPCM8XX_SFUNC(smb8);
+NPCM8XX_SFUNC(smb9);
+NPCM8XX_SFUNC(smb10);
+NPCM8XX_SFUNC(smb11);
+NPCM8XX_SFUNC(smb12);
+NPCM8XX_SFUNC(smb13);
+NPCM8XX_SFUNC(smb14);
+NPCM8XX_SFUNC(smb14b);
+NPCM8XX_SFUNC(smb15);
+NPCM8XX_SFUNC(smb16);
+NPCM8XX_SFUNC(smb16b);
+NPCM8XX_SFUNC(smb17);
+NPCM8XX_SFUNC(smb18);
+NPCM8XX_SFUNC(smb19);
+NPCM8XX_SFUNC(smb20);
+NPCM8XX_SFUNC(smb21);
+NPCM8XX_SFUNC(smb22);
+NPCM8XX_SFUNC(smb23);
+NPCM8XX_SFUNC(smb23b);
+NPCM8XX_SFUNC(fanin0);
+NPCM8XX_SFUNC(fanin1);
+NPCM8XX_SFUNC(fanin2);
+NPCM8XX_SFUNC(fanin3);
+NPCM8XX_SFUNC(fanin4);
+NPCM8XX_SFUNC(fanin5);
+NPCM8XX_SFUNC(fanin6);
+NPCM8XX_SFUNC(fanin7);
+NPCM8XX_SFUNC(fanin8);
+NPCM8XX_SFUNC(fanin9);
+NPCM8XX_SFUNC(fanin10);
+NPCM8XX_SFUNC(fanin11);
+NPCM8XX_SFUNC(fanin12);
+NPCM8XX_SFUNC(fanin13);
+NPCM8XX_SFUNC(fanin14);
+NPCM8XX_SFUNC(fanin15);
+NPCM8XX_SFUNC(faninx);
+NPCM8XX_SFUNC(pwm0);
+NPCM8XX_SFUNC(pwm1);
+NPCM8XX_SFUNC(pwm2);
+NPCM8XX_SFUNC(pwm3);
+NPCM8XX_SFUNC(pwm4);
+NPCM8XX_SFUNC(pwm5);
+NPCM8XX_SFUNC(pwm6);
+NPCM8XX_SFUNC(pwm7);
+NPCM8XX_SFUNC(pwm8);
+NPCM8XX_SFUNC(pwm9);
+NPCM8XX_SFUNC(pwm10);
+NPCM8XX_SFUNC(pwm11);
+NPCM8XX_SFUNC(bu2);
+NPCM8XX_SFUNC(sg1mdio);
+NPCM8XX_SFUNC(rg2);
+NPCM8XX_SFUNC(rg2refck);
+NPCM8XX_SFUNC(rg2mdio);
+NPCM8XX_SFUNC(ddr);
+NPCM8XX_SFUNC(uart1);
+NPCM8XX_SFUNC(uart2);
+NPCM8XX_SFUNC(bmcuart0a);
+NPCM8XX_SFUNC(bmcuart0b);
+NPCM8XX_SFUNC(bmcuart1);
+NPCM8XX_SFUNC(iox1);
+NPCM8XX_SFUNC(iox2);
+NPCM8XX_SFUNC(ioxh);
+NPCM8XX_SFUNC(gspi);
+NPCM8XX_SFUNC(mmc);
+NPCM8XX_SFUNC(mmcwp);
+NPCM8XX_SFUNC(mmccd);
+NPCM8XX_SFUNC(mmcrst);
+NPCM8XX_SFUNC(mmc8);
+NPCM8XX_SFUNC(r1);
+NPCM8XX_SFUNC(r1err);
+NPCM8XX_SFUNC(r1md);
+NPCM8XX_SFUNC(r2);
+NPCM8XX_SFUNC(r2err);
+NPCM8XX_SFUNC(r2md);
+NPCM8XX_SFUNC(sd1);
+NPCM8XX_SFUNC(sd1pwr);
+NPCM8XX_SFUNC(wdog1);
+NPCM8XX_SFUNC(wdog2);
+NPCM8XX_SFUNC(scipme);
+NPCM8XX_SFUNC(sci);
+NPCM8XX_SFUNC(serirq);
+NPCM8XX_SFUNC(jtag2);
+NPCM8XX_SFUNC(spix);
+NPCM8XX_SFUNC(spixcs1);
+NPCM8XX_SFUNC(pspi);
+NPCM8XX_SFUNC(ddc);
+NPCM8XX_SFUNC(clkreq);
+NPCM8XX_SFUNC(clkout);
+NPCM8XX_SFUNC(spi3);
+NPCM8XX_SFUNC(spi3cs1);
+NPCM8XX_SFUNC(spi3quad);
+NPCM8XX_SFUNC(spi3cs2);
+NPCM8XX_SFUNC(spi3cs3);
+NPCM8XX_SFUNC(spi0cs1);
+NPCM8XX_SFUNC(lpc);
+NPCM8XX_SFUNC(lpcclk);
+NPCM8XX_SFUNC(espi);
+NPCM8XX_SFUNC(lkgpo0);
+NPCM8XX_SFUNC(lkgpo1);
+NPCM8XX_SFUNC(lkgpo2);
+NPCM8XX_SFUNC(nprd_smi);
+NPCM8XX_SFUNC(hgpio0);
+NPCM8XX_SFUNC(hgpio1);
+NPCM8XX_SFUNC(hgpio2);
+NPCM8XX_SFUNC(hgpio3);
+NPCM8XX_SFUNC(hgpio4);
+NPCM8XX_SFUNC(hgpio5);
+NPCM8XX_SFUNC(hgpio6);
+NPCM8XX_SFUNC(hgpio7);
+
+/* Function names */
+static struct npcm8xx_func npcm8xx_funcs[] = {
+ NPCM8XX_MKFUNC(gpi35),
+ NPCM8XX_MKFUNC(gpi36),
+ NPCM8XX_MKFUNC(tp_jtag3),
+ NPCM8XX_MKFUNC(tp_uart),
+ NPCM8XX_MKFUNC(tp_smb2),
+ NPCM8XX_MKFUNC(tp_smb1),
+ NPCM8XX_MKFUNC(tp_gpio7),
+ NPCM8XX_MKFUNC(tp_gpio6),
+ NPCM8XX_MKFUNC(tp_gpio5),
+ NPCM8XX_MKFUNC(tp_gpio4),
+ NPCM8XX_MKFUNC(tp_gpio3),
+ NPCM8XX_MKFUNC(tp_gpio2),
+ NPCM8XX_MKFUNC(tp_gpio1),
+ NPCM8XX_MKFUNC(tp_gpio0),
+ NPCM8XX_MKFUNC(tp_gpio2b),
+ NPCM8XX_MKFUNC(tp_gpio1b),
+ NPCM8XX_MKFUNC(tp_gpio0b),
+ NPCM8XX_MKFUNC(vgadig),
+ NPCM8XX_MKFUNC(nbu1crts),
+ NPCM8XX_MKFUNC(fm2),
+ NPCM8XX_MKFUNC(fm1),
+ NPCM8XX_MKFUNC(fm0),
+ NPCM8XX_MKFUNC(gpio1836),
+ NPCM8XX_MKFUNC(gpio1889),
+ NPCM8XX_MKFUNC(gpio187),
+ NPCM8XX_MKFUNC(cp1urxd),
+ NPCM8XX_MKFUNC(r3rxer),
+ NPCM8XX_MKFUNC(cp1gpio2c),
+ NPCM8XX_MKFUNC(cp1gpio3c),
+ NPCM8XX_MKFUNC(cp1gpio0b),
+ NPCM8XX_MKFUNC(cp1gpio1b),
+ NPCM8XX_MKFUNC(cp1gpio2b),
+ NPCM8XX_MKFUNC(cp1gpio3b),
+ NPCM8XX_MKFUNC(cp1gpio4b),
+ NPCM8XX_MKFUNC(cp1gpio5b),
+ NPCM8XX_MKFUNC(cp1gpio6b),
+ NPCM8XX_MKFUNC(cp1gpio7b),
+ NPCM8XX_MKFUNC(cp1gpio0),
+ NPCM8XX_MKFUNC(cp1gpio1),
+ NPCM8XX_MKFUNC(cp1gpio2),
+ NPCM8XX_MKFUNC(cp1gpio3),
+ NPCM8XX_MKFUNC(cp1gpio4),
+ NPCM8XX_MKFUNC(cp1gpio5),
+ NPCM8XX_MKFUNC(cp1gpio6),
+ NPCM8XX_MKFUNC(cp1gpio7),
+ NPCM8XX_MKFUNC(cp1utxd),
+ NPCM8XX_MKFUNC(spi1cs3),
+ NPCM8XX_MKFUNC(spi1cs2),
+ NPCM8XX_MKFUNC(spi1cs1),
+ NPCM8XX_MKFUNC(spi1),
+ NPCM8XX_MKFUNC(spi1d23),
+ NPCM8XX_MKFUNC(j2j3),
+ NPCM8XX_MKFUNC(r3oen),
+ NPCM8XX_MKFUNC(r2oen),
+ NPCM8XX_MKFUNC(r1oen),
+ NPCM8XX_MKFUNC(bu4b),
+ NPCM8XX_MKFUNC(bu4),
+ NPCM8XX_MKFUNC(bu5b),
+ NPCM8XX_MKFUNC(bu5),
+ NPCM8XX_MKFUNC(bu6),
+ NPCM8XX_MKFUNC(rmii3),
+ NPCM8XX_MKFUNC(jm1),
+ NPCM8XX_MKFUNC(jm2),
+ NPCM8XX_MKFUNC(tpgpio5b),
+ NPCM8XX_MKFUNC(tpgpio4b),
+ NPCM8XX_MKFUNC(clkrun),
+ NPCM8XX_MKFUNC(i3c5),
+ NPCM8XX_MKFUNC(i3c4),
+ NPCM8XX_MKFUNC(i3c3),
+ NPCM8XX_MKFUNC(i3c2),
+ NPCM8XX_MKFUNC(i3c1),
+ NPCM8XX_MKFUNC(i3c0),
+ NPCM8XX_MKFUNC(hsi1a),
+ NPCM8XX_MKFUNC(hsi2a),
+ NPCM8XX_MKFUNC(hsi1b),
+ NPCM8XX_MKFUNC(hsi2b),
+ NPCM8XX_MKFUNC(hsi1c),
+ NPCM8XX_MKFUNC(hsi2c),
+ NPCM8XX_MKFUNC(smb0),
+ NPCM8XX_MKFUNC(smb0b),
+ NPCM8XX_MKFUNC(smb0c),
+ NPCM8XX_MKFUNC(smb0d),
+ NPCM8XX_MKFUNC(smb0den),
+ NPCM8XX_MKFUNC(smb1),
+ NPCM8XX_MKFUNC(smb1b),
+ NPCM8XX_MKFUNC(smb1c),
+ NPCM8XX_MKFUNC(smb1d),
+ NPCM8XX_MKFUNC(smb2),
+ NPCM8XX_MKFUNC(smb2b),
+ NPCM8XX_MKFUNC(smb2c),
+ NPCM8XX_MKFUNC(smb2d),
+ NPCM8XX_MKFUNC(smb3),
+ NPCM8XX_MKFUNC(smb3b),
+ NPCM8XX_MKFUNC(smb3c),
+ NPCM8XX_MKFUNC(smb3d),
+ NPCM8XX_MKFUNC(smb4),
+ NPCM8XX_MKFUNC(smb4b),
+ NPCM8XX_MKFUNC(smb4c),
+ NPCM8XX_MKFUNC(smb4d),
+ NPCM8XX_MKFUNC(smb4den),
+ NPCM8XX_MKFUNC(smb5),
+ NPCM8XX_MKFUNC(smb5b),
+ NPCM8XX_MKFUNC(smb5c),
+ NPCM8XX_MKFUNC(smb5d),
+ NPCM8XX_MKFUNC(ga20kbc),
+ NPCM8XX_MKFUNC(smb6),
+ NPCM8XX_MKFUNC(smb6b),
+ NPCM8XX_MKFUNC(smb6c),
+ NPCM8XX_MKFUNC(smb6d),
+ NPCM8XX_MKFUNC(smb7),
+ NPCM8XX_MKFUNC(smb7b),
+ NPCM8XX_MKFUNC(smb7c),
+ NPCM8XX_MKFUNC(smb7d),
+ NPCM8XX_MKFUNC(smb8),
+ NPCM8XX_MKFUNC(smb9),
+ NPCM8XX_MKFUNC(smb10),
+ NPCM8XX_MKFUNC(smb11),
+ NPCM8XX_MKFUNC(smb12),
+ NPCM8XX_MKFUNC(smb13),
+ NPCM8XX_MKFUNC(smb14),
+ NPCM8XX_MKFUNC(smb14b),
+ NPCM8XX_MKFUNC(smb15),
+ NPCM8XX_MKFUNC(smb16),
+ NPCM8XX_MKFUNC(smb16b),
+ NPCM8XX_MKFUNC(smb17),
+ NPCM8XX_MKFUNC(smb18),
+ NPCM8XX_MKFUNC(smb19),
+ NPCM8XX_MKFUNC(smb20),
+ NPCM8XX_MKFUNC(smb21),
+ NPCM8XX_MKFUNC(smb22),
+ NPCM8XX_MKFUNC(smb23),
+ NPCM8XX_MKFUNC(smb23b),
+ NPCM8XX_MKFUNC(fanin0),
+ NPCM8XX_MKFUNC(fanin1),
+ NPCM8XX_MKFUNC(fanin2),
+ NPCM8XX_MKFUNC(fanin3),
+ NPCM8XX_MKFUNC(fanin4),
+ NPCM8XX_MKFUNC(fanin5),
+ NPCM8XX_MKFUNC(fanin6),
+ NPCM8XX_MKFUNC(fanin7),
+ NPCM8XX_MKFUNC(fanin8),
+ NPCM8XX_MKFUNC(fanin9),
+ NPCM8XX_MKFUNC(fanin10),
+ NPCM8XX_MKFUNC(fanin11),
+ NPCM8XX_MKFUNC(fanin12),
+ NPCM8XX_MKFUNC(fanin13),
+ NPCM8XX_MKFUNC(fanin14),
+ NPCM8XX_MKFUNC(fanin15),
+ NPCM8XX_MKFUNC(faninx),
+ NPCM8XX_MKFUNC(pwm0),
+ NPCM8XX_MKFUNC(pwm1),
+ NPCM8XX_MKFUNC(pwm2),
+ NPCM8XX_MKFUNC(pwm3),
+ NPCM8XX_MKFUNC(pwm4),
+ NPCM8XX_MKFUNC(pwm5),
+ NPCM8XX_MKFUNC(pwm6),
+ NPCM8XX_MKFUNC(pwm7),
+ NPCM8XX_MKFUNC(pwm8),
+ NPCM8XX_MKFUNC(pwm9),
+ NPCM8XX_MKFUNC(pwm10),
+ NPCM8XX_MKFUNC(pwm11),
+ NPCM8XX_MKFUNC(bu2),
+ NPCM8XX_MKFUNC(sg1mdio),
+ NPCM8XX_MKFUNC(rg2),
+ NPCM8XX_MKFUNC(rg2refck),
+ NPCM8XX_MKFUNC(rg2mdio),
+ NPCM8XX_MKFUNC(ddr),
+ NPCM8XX_MKFUNC(uart1),
+ NPCM8XX_MKFUNC(uart2),
+ NPCM8XX_MKFUNC(bmcuart0a),
+ NPCM8XX_MKFUNC(bmcuart0b),
+ NPCM8XX_MKFUNC(bmcuart1),
+ NPCM8XX_MKFUNC(iox1),
+ NPCM8XX_MKFUNC(iox2),
+ NPCM8XX_MKFUNC(ioxh),
+ NPCM8XX_MKFUNC(gspi),
+ NPCM8XX_MKFUNC(mmc),
+ NPCM8XX_MKFUNC(mmcwp),
+ NPCM8XX_MKFUNC(mmccd),
+ NPCM8XX_MKFUNC(mmcrst),
+ NPCM8XX_MKFUNC(mmc8),
+ NPCM8XX_MKFUNC(r1),
+ NPCM8XX_MKFUNC(r1err),
+ NPCM8XX_MKFUNC(r1md),
+ NPCM8XX_MKFUNC(r2),
+ NPCM8XX_MKFUNC(r2err),
+ NPCM8XX_MKFUNC(r2md),
+ NPCM8XX_MKFUNC(sd1),
+ NPCM8XX_MKFUNC(sd1pwr),
+ NPCM8XX_MKFUNC(wdog1),
+ NPCM8XX_MKFUNC(wdog2),
+ NPCM8XX_MKFUNC(scipme),
+ NPCM8XX_MKFUNC(sci),
+ NPCM8XX_MKFUNC(serirq),
+ NPCM8XX_MKFUNC(jtag2),
+ NPCM8XX_MKFUNC(spix),
+ NPCM8XX_MKFUNC(spixcs1),
+ NPCM8XX_MKFUNC(pspi),
+ NPCM8XX_MKFUNC(ddc),
+ NPCM8XX_MKFUNC(clkreq),
+ NPCM8XX_MKFUNC(clkout),
+ NPCM8XX_MKFUNC(spi3),
+ NPCM8XX_MKFUNC(spi3cs1),
+ NPCM8XX_MKFUNC(spi3quad),
+ NPCM8XX_MKFUNC(spi3cs2),
+ NPCM8XX_MKFUNC(spi3cs3),
+ NPCM8XX_MKFUNC(spi0cs1),
+ NPCM8XX_MKFUNC(lpc),
+ NPCM8XX_MKFUNC(lpcclk),
+ NPCM8XX_MKFUNC(espi),
+ NPCM8XX_MKFUNC(lkgpo0),
+ NPCM8XX_MKFUNC(lkgpo1),
+ NPCM8XX_MKFUNC(lkgpo2),
+ NPCM8XX_MKFUNC(nprd_smi),
+ NPCM8XX_MKFUNC(hgpio0),
+ NPCM8XX_MKFUNC(hgpio1),
+ NPCM8XX_MKFUNC(hgpio2),
+ NPCM8XX_MKFUNC(hgpio3),
+ NPCM8XX_MKFUNC(hgpio4),
+ NPCM8XX_MKFUNC(hgpio5),
+ NPCM8XX_MKFUNC(hgpio6),
+ NPCM8XX_MKFUNC(hgpio7),
+};
+
+#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \
+ [a] { .fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \
+ .fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \
+ .fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \
+ .fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \
+ .fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \
+ .flag = q }
+
+/* Drive strength controlled by NPCM8XX_GP_N_ODSC */
+#define DRIVE_STRENGTH_LO_SHIFT 8
+#define DRIVE_STRENGTH_HI_SHIFT 12
+#define DRIVE_STRENGTH_MASK 0x0000FF00
+
+#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
+ ((hi) << DRIVE_STRENGTH_HI_SHIFT))
+#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
+#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
+
+#define GPI 0x1 /* Not GPO */
+#define GPO 0x2 /* Not GPI */
+#define SLEW 0x4 /* Has Slew Control, NPCM8XX_GP_N_OSRC */
+#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
+
+struct npcm8xx_pincfg {
+ int flag;
+ int fn0, reg0, bit0;
+ int fn1, reg1, bit1;
+ int fn2, reg2, bit2;
+ int fn3, reg3, bit3;
+ int fn4, reg4, bit4;
+};
+
+static const struct npcm8xx_pincfg pincfgs[] = {
+ /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */
+ NPCM8XX_PINCFG(0, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(1, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(2, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(3, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(8, lkgpo1, FLOCKR1, 4, tp_gpio0, MFSEL7, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(9, lkgpo2, FLOCKR1, 8, tp_gpio1, MFSEL7, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(10, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(11, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(32, smb14b, MFSEL7, 26, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(35, gpi35, MFSEL5, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI),
+ NPCM8XX_PINCFG(36, gpi36, MFSEL5, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI),
+ NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(40, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(41, bmcuart0a, MFSEL1, 9, cp1urxd, MFSEL6, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(42, bmcuart0a, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO),
+ NPCM8XX_PINCFG(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(44, hsi1b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO),
+ NPCM8XX_PINCFG(45, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(46, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(47, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(2, 8)),
+ NPCM8XX_PINCFG(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(57, r1md, MFSEL1, 13, tpgpio4b, MFSEL5, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(2, 4)),
+ NPCM8XX_PINCFG(58, r1md, MFSEL1, 13, tpgpio5b, MFSEL5, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(2, 4)),
+ NPCM8XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(62, hsi1b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, GPO),
+ NPCM8XX_PINCFG(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(91, r2md, MFSEL1, 16, cp1gpio6, MFSEL6, 8, tp_gpio0b, MFSEL7, 0, none, NONE, 0, none, NONE, 0, DS(2, 4)),
+ NPCM8XX_PINCFG(92, r2md, MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1b, MFSEL7, 1, none, NONE, 0, none, NONE, 0, DS(2, 4)),
+ NPCM8XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(96, cp1gpio7b, MFSEL6, 24, bu2, MFSEL4, 22, tp_gpio7, MFSEL7, 7, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(97, cp1gpio6b, MFSEL6, 25, bu2, MFSEL4, 22, tp_gpio6, MFSEL7, 6, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(98, bu4b, MFSEL5, 13, cp1gpio5b, MFSEL6, 26, tp_gpio5, MFSEL7, 5, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(99, bu4b, MFSEL5, 13, cp1gpio4b, MFSEL6, 27, tp_gpio4, MFSEL7, 4, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(100, bu5b, MFSEL5, 13, cp1gpio3c, MFSEL6, 28, tp_gpio3, MFSEL7, 3, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(101, bu5b, MFSEL5, 13, cp1gpio2c, MFSEL6, 29, tp_gpio2b, MFSEL7, 2, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(102, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(103, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(104, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(105, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(106, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(124, smb1c, I2CSEGSEL, 6, cp1gpio3b, MFSEL6, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(125, smb1c, I2CSEGSEL, 6, cp1gpio2b, MFSEL6, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(126, smb1b, I2CSEGSEL, 5, cp1gpio1b, MFSEL6, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(127, smb1b, I2CSEGSEL, 5, cp1gpio0b, MFSEL6, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 8)),
+ NPCM8XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
+ NPCM8XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
+ NPCM8XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(168, lpcclk, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(170, sci, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(175, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(176, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(177, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(183, spi3, MFSEL4, 16, gpio1836, MFSEL6, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(184, spi3, MFSEL4, 16, gpio1836, MFSEL6, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(185, spi3, MFSEL4, 16, gpio1836, MFSEL6, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(187, spi3cs1, MFSEL4, 17, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, gpio1889, MFSEL7, 25, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, gpio1889, MFSEL7, 25, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(2, 4)),
+ NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DS(0, 2)), /* XX */
+ NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DS(0, 2)), /* XX */
+ NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
+ NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(0, 1)),
+ NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
+ NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(218, wdog1, MFSEL3, 19, smb16, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(219, wdog2, MFSEL3, 20, smb16, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(220, smb12, MFSEL3, 5, pwm8, MFSEL6, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(221, smb12, MFSEL3, 5, pwm9, MFSEL6, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(224, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(225, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(226, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+ NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(4, 12) | SLEW),
+ NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEWLPC),
+ NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
+ NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(241, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(242, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(243, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(244, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(249, r2oen, INTCR4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
+ NPCM8XX_PINCFG(250, rg2refck, INTCR4, 6, ddr, MFSEL3, 26, rmii3, MFSEL5, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
+};
+
+#define NPCM8XX_PIN(a, b) { .number = a, .name = b }
+struct npcm8xx_pin_desc {
+ unsigned int number;
+ const char *name;
+};
+
+/* number, name, drv_data */
+static const struct npcm8xx_pin_desc npcm8xx_pins[] = {
+ NPCM8XX_PIN(0, "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"),
+ NPCM8XX_PIN(1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"),
+ NPCM8XX_PIN(2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"),
+ NPCM8XX_PIN(3, "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"),
+ NPCM8XX_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"),
+ NPCM8XX_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"),
+ NPCM8XX_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"),
+ NPCM8XX_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"),
+ NPCM8XX_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"),
+ NPCM8XX_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"),
+ NPCM8XX_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"),
+ NPCM8XX_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"),
+ NPCM8XX_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"),
+ NPCM8XX_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"),
+ NPCM8XX_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"),
+ NPCM8XX_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"),
+ NPCM8XX_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"),
+ NPCM8XX_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"),
+ NPCM8XX_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"),
+ NPCM8XX_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"),
+ NPCM8XX_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"),
+ NPCM8XX_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"),
+ NPCM8XX_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"),
+ NPCM8XX_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"),
+ NPCM8XX_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"),
+ NPCM8XX_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"),
+ NPCM8XX_PIN(26, "GPIO26/SMB5_SDA"),
+ NPCM8XX_PIN(27, "GPIO27/SMB5_SCL"),
+ NPCM8XX_PIN(28, "GPIO28/SMB4_SDA"),
+ NPCM8XX_PIN(29, "GPIO29/SMB4_SCL"),
+ NPCM8XX_PIN(30, "GPIO30/SMB3_SDA"),
+ NPCM8XX_PIN(31, "GPIO31/SMB3_SCL"),
+ NPCM8XX_PIN(32, "GPIO32/SMB14_SCL/SPI0_nCS1"),
+ NPCM8XX_PIN(33, "I3C4_SCL"),
+ NPCM8XX_PIN(34, "I3C4_SDA"),
+ NPCM8XX_PIN(35, "NA"),
+ NPCM8XX_PIN(36, "NA"),
+ NPCM8XX_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
+ NPCM8XX_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
+ NPCM8XX_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
+ NPCM8XX_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"),
+ NPCM8XX_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"),
+ NPCM8XX_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"),
+ NPCM8XX_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"),
+ NPCM8XX_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"),
+ NPCM8XX_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"),
+ NPCM8XX_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"),
+ NPCM8XX_PIN(47, "GPIO47/SI1n_RI1"),
+ NPCM8XX_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"),
+ NPCM8XX_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"),
+ NPCM8XX_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"),
+ NPCM8XX_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"),
+ NPCM8XX_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"),
+ NPCM8XX_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"),
+ NPCM8XX_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"),
+ NPCM8XX_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"),
+ NPCM8XX_PIN(56, "GPIO56/R1_RXERR/R1_OEN"),
+ NPCM8XX_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"),
+ NPCM8XX_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"),
+ NPCM8XX_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"),
+ NPCM8XX_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"),
+ NPCM8XX_PIN(61, "GPIO61/SI1_nDTR_BOUT"),
+ NPCM8XX_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"),
+ NPCM8XX_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"),
+ NPCM8XX_PIN(64, "GPIO64/FANIN0"),
+ NPCM8XX_PIN(65, "GPIO65/FANIN1"),
+ NPCM8XX_PIN(66, "GPIO66/FANIN2"),
+ NPCM8XX_PIN(67, "GPIO67/FANIN3"),
+ NPCM8XX_PIN(68, "GPIO68/FANIN4"),
+ NPCM8XX_PIN(69, "GPIO69/FANIN5"),
+ NPCM8XX_PIN(70, "GPIO70/FANIN6"),
+ NPCM8XX_PIN(71, "GPIO71/FANIN7"),
+ NPCM8XX_PIN(72, "GPIO72/FANIN8"),
+ NPCM8XX_PIN(73, "GPIO73/FANIN9"),
+ NPCM8XX_PIN(74, "GPIO74/FANIN10"),
+ NPCM8XX_PIN(75, "GPIO75/FANIN11"),
+ NPCM8XX_PIN(76, "GPIO76/FANIN12"),
+ NPCM8XX_PIN(77, "GPIO77/FANIN13"),
+ NPCM8XX_PIN(78, "GPIO78/FANIN14"),
+ NPCM8XX_PIN(79, "GPIO79/FANIN15"),
+ NPCM8XX_PIN(80, "GPIO80/PWM0"),
+ NPCM8XX_PIN(81, "GPIO81/PWM1"),
+ NPCM8XX_PIN(82, "GPIO82/PWM2"),
+ NPCM8XX_PIN(83, "GPIO83/PWM3"),
+ NPCM8XX_PIN(84, "GPIO84/R2_TXD0"),
+ NPCM8XX_PIN(85, "GPIO85/R2_TXD1"),
+ NPCM8XX_PIN(86, "GPIO86/R2_TXEN"),
+ NPCM8XX_PIN(87, "GPIO87/R2_RXD0"),
+ NPCM8XX_PIN(88, "GPIO88/R2_RXD1"),
+ NPCM8XX_PIN(89, "GPIO89/R2_CRSDV"),
+ NPCM8XX_PIN(90, "GPIO90/R2_RXERR/R2_OEN"),
+ NPCM8XX_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"),
+ NPCM8XX_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"),
+ NPCM8XX_PIN(93, "GPIO93/GA20/SMB5D_SCL"),
+ NPCM8XX_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"),
+ NPCM8XX_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"),
+ NPCM8XX_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"),
+ NPCM8XX_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"),
+ NPCM8XX_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"),
+ NPCM8XX_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"),
+ NPCM8XX_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"),
+ NPCM8XX_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"),
+ NPCM8XX_PIN(102, "GPIO102/HSYNC"),
+ NPCM8XX_PIN(103, "GPIO103/VSYNC"),
+ NPCM8XX_PIN(104, "GPIO104/DDC_SCL"),
+ NPCM8XX_PIN(105, "GPIO105/DDC_SDA"),
+ NPCM8XX_PIN(106, "GPIO106/I3C5_SCL"),
+ NPCM8XX_PIN(107, "GPIO107/I3C5_SDA"),
+ NPCM8XX_PIN(108, "GPIO108/SG1_MDC"),
+ NPCM8XX_PIN(109, "GPIO109/SG1_MDIO"),
+ NPCM8XX_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"),
+ NPCM8XX_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"),
+ NPCM8XX_PIN(112, "GPIO112/RG2_TXD2/DDRV2"),
+ NPCM8XX_PIN(113, "GPIO113/RG2_TXD3/DDRV3"),
+ NPCM8XX_PIN(114, "GPIO114/SMB0_SCL"),
+ NPCM8XX_PIN(115, "GPIO115/SMB0_SDA"),
+ NPCM8XX_PIN(116, "GPIO116/SMB1_SCL"),
+ NPCM8XX_PIN(117, "GPIO117/SMB1_SDA"),
+ NPCM8XX_PIN(118, "GPIO118/SMB2_SCL"),
+ NPCM8XX_PIN(119, "GPIO119/SMB2_SDA"),
+ NPCM8XX_PIN(120, "GPIO120/SMB2C_SDA"),
+ NPCM8XX_PIN(121, "GPIO121/SMB2C_SCL"),
+ NPCM8XX_PIN(122, "GPIO122/SMB2B_SDA"),
+ NPCM8XX_PIN(123, "GPIO123/SMB2B_SCL"),
+ NPCM8XX_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"),
+ NPCM8XX_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"),
+ NPCM8XX_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"),
+ NPCM8XX_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"),
+ NPCM8XX_PIN(128, "GPIO128/SMB824_SCL"),
+ NPCM8XX_PIN(129, "GPIO129/SMB824_SDA"),
+ NPCM8XX_PIN(130, "GPIO130/SMB925_SCL"),
+ NPCM8XX_PIN(131, "GPIO131/SMB925_SDA"),
+ NPCM8XX_PIN(132, "GPIO132/SMB1026_SCL"),
+ NPCM8XX_PIN(133, "GPIO133/SMB1026_SDA"),
+ NPCM8XX_PIN(134, "GPIO134/SMB11_SCL"),
+ NPCM8XX_PIN(135, "GPIO135/SMB11_SDA"),
+ NPCM8XX_PIN(136, "GPIO136/JM1_TCK"),
+ NPCM8XX_PIN(137, "GPIO137/JM1_TDO"),
+ NPCM8XX_PIN(138, "GPIO138/JM1_TMS"),
+ NPCM8XX_PIN(139, "GPIO139/JM1_TDI"),
+ NPCM8XX_PIN(140, "GPIO140/JM1_nTRST"),
+ NPCM8XX_PIN(141, "GPIO141/SMB7B_SCL"),
+ NPCM8XX_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"),
+ NPCM8XX_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"),
+ NPCM8XX_PIN(144, "GPIO144/PWM4"),
+ NPCM8XX_PIN(145, "GPIO145/PWM5"),
+ NPCM8XX_PIN(146, "GPIO146/PWM6"),
+ NPCM8XX_PIN(147, "GPIO147/PWM7"),
+ NPCM8XX_PIN(148, "GPIO148/MMC_DT4"),
+ NPCM8XX_PIN(149, "GPIO149/MMC_DT5"),
+ NPCM8XX_PIN(150, "GPIO150/MMC_DT6"),
+ NPCM8XX_PIN(151, "GPIO151/MMC_DT7"),
+ NPCM8XX_PIN(152, "GPIO152/MMC_CLK"),
+ NPCM8XX_PIN(153, "GPIO153/MMC_WP"),
+ NPCM8XX_PIN(154, "GPIO154/MMC_CMD"),
+ NPCM8XX_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"),
+ NPCM8XX_PIN(156, "GPIO156/MMC_DT0"),
+ NPCM8XX_PIN(157, "GPIO157/MMC_DT1"),
+ NPCM8XX_PIN(158, "GPIO158/MMC_DT2"),
+ NPCM8XX_PIN(159, "GPIO159/MMC_DT3"),
+ NPCM8XX_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"),
+ NPCM8XX_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"),
+ NPCM8XX_PIN(162, "GPIO162/LPC_nCLKRUN"),
+ NPCM8XX_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"),
+ NPCM8XX_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"),
+ NPCM8XX_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"),
+ NPCM8XX_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"),
+ NPCM8XX_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"),
+ NPCM8XX_PIN(168, "GPIO168/ESPI_nALERT/SERIRQ"),
+ NPCM8XX_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"),
+ NPCM8XX_PIN(170, "GPIO170/nSMI/SMB21_SDA"),
+ NPCM8XX_PIN(171, "GPIO171/SMB6_SCL"),
+ NPCM8XX_PIN(172, "GPIO172/SMB6_SDA"),
+ NPCM8XX_PIN(173, "GPIO173/SMB7_SCL"),
+ NPCM8XX_PIN(174, "GPIO174/SMB7_SDA"),
+ NPCM8XX_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"),
+ NPCM8XX_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"),
+ NPCM8XX_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"),
+ NPCM8XX_PIN(178, "GPIO178/R1_TXD0"),
+ NPCM8XX_PIN(179, "GPIO179/R1_TXD1"),
+ NPCM8XX_PIN(180, "GPIO180/R1_TXEN"),
+ NPCM8XX_PIN(181, "GPIO181/R1_RXD0"),
+ NPCM8XX_PIN(182, "GPIO182/R1_RXD1"),
+ NPCM8XX_PIN(183, "GPIO183/SPI3_SEL"),
+ NPCM8XX_PIN(184, "GPIO184/SPI3_D0/STRAP13"),
+ NPCM8XX_PIN(185, "GPIO185/SPI3_D1"),
+ NPCM8XX_PIN(186, "GPIO186/SPI3_nCS0"),
+ NPCM8XX_PIN(187, "GPIO187/SPI3_nCS1_SMB14_SDA"),
+ NPCM8XX_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"),
+ NPCM8XX_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"),
+ NPCM8XX_PIN(190, "GPIO190/nPRD_SMI"),
+ NPCM8XX_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"),
+ NPCM8XX_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"),
+ NPCM8XX_PIN(193, "GPIO193/R1_CRSDV"),
+ NPCM8XX_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"),
+ NPCM8XX_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"),
+ NPCM8XX_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"),
+ NPCM8XX_PIN(197, "GPIO197/SMB0DEN/FM0_D3"),
+ NPCM8XX_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"),
+ NPCM8XX_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"),
+ NPCM8XX_PIN(200, "GPIO200/R2_CK"),
+ NPCM8XX_PIN(201, "GPIO201/R1_CK"),
+ NPCM8XX_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"),
+ NPCM8XX_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"),
+ NPCM8XX_PIN(204, "NA"),
+ NPCM8XX_PIN(205, "NA"),
+ NPCM8XX_PIN(206, "NA"),
+ NPCM8XX_PIN(207, "NA"),
+ NPCM8XX_PIN(208, "GPIO208/RG2_TXC/DVCK"),
+ NPCM8XX_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"),
+ NPCM8XX_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"),
+ NPCM8XX_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"),
+ NPCM8XX_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"),
+ NPCM8XX_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"),
+ NPCM8XX_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"),
+ NPCM8XX_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"),
+ NPCM8XX_PIN(216, "GPIO216/RG2_MDC/DDRV11"),
+ NPCM8XX_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"),
+ NPCM8XX_PIN(218, "GPIO218/nWDO1/SMB16_SCL"),
+ NPCM8XX_PIN(219, "GPIO219/nWDO2/SMB16_SDA"),
+ NPCM8XX_PIN(220, "GPIO220/SMB12_SCL/PWM8"),
+ NPCM8XX_PIN(221, "GPIO221/SMB12_SDA/PWM9"),
+ NPCM8XX_PIN(222, "GPIO222/SMB13_SCL"),
+ NPCM8XX_PIN(223, "GPIO223/SMB13_SDA"),
+ NPCM8XX_PIN(224, "GPIO224/SPIX_CK/FM2_CK"),
+ NPCM8XX_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"),
+ NPCM8XX_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"),
+ NPCM8XX_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"),
+ NPCM8XX_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"),
+ NPCM8XX_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"),
+ NPCM8XX_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"),
+ NPCM8XX_PIN(231, "GPIO231/EP_nCLKREQ"),
+ NPCM8XX_PIN(232, "NA"),
+ NPCM8XX_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"),
+ NPCM8XX_PIN(234, "GPIO234/PWM10/SMB20_SCL"),
+ NPCM8XX_PIN(235, "GPIO235/PWM11/SMB20_SDA"),
+ NPCM8XX_PIN(236, "NA"),
+ NPCM8XX_PIN(237, "NA"),
+ NPCM8XX_PIN(238, "NA"),
+ NPCM8XX_PIN(239, "NA"),
+ NPCM8XX_PIN(240, "GPIO240/I3C0_SCL"),
+ NPCM8XX_PIN(241, "GPIO241/I3C0_SDA"),
+ NPCM8XX_PIN(242, "GPIO242/I3C1_SCL"),
+ NPCM8XX_PIN(243, "GPIO243/I3C1_SDA"),
+ NPCM8XX_PIN(244, "GPIO244/I3C2_SCL"),
+ NPCM8XX_PIN(245, "GPIO245/I3C2_SDA"),
+ NPCM8XX_PIN(246, "GPIO246/I3C3_SCL"),
+ NPCM8XX_PIN(247, "GPIO247/I3C3_SDA"),
+ NPCM8XX_PIN(248, "NA"),
+ NPCM8XX_PIN(249, "R2_OEN"),
+ NPCM8XX_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"),
+};
+
+struct npcm8xx_pinctrl_priv {
+ u32 gcr_base;
+ u32 clk_base;
+ u32 gpio_base;
+};
+
+static int npcm8xx_pinctrl_probe(struct udevice *dev)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->gcr_base = NPCM_GCR_BA;
+ priv->clk_base = NPCM_CLK_BA;
+ priv->gpio_base = NPCM_GPIO_BA;
+
+ return 0;
+}
+
+/* Enable mode in pin group */
+static void npcm8xx_setfunc(struct udevice *dev, const unsigned int *pin,
+ unsigned int pin_number, unsigned int mode)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct npcm8xx_pincfg *cfg;
+ int i;
+ u32 gcr_reg = priv->gcr_base;
+
+ for (i = 0 ; i < pin_number ; i++) {
+ cfg = &pincfgs[pin[i]];
+ if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode ||
+ cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) {
+ if (cfg->reg0) {
+ if (cfg->fn0 == mode)
+ setbits_le32((uintptr_t)(gcr_reg + cfg->reg0),
+ BIT(cfg->bit0));
+ else
+ clrbits_le32((uintptr_t)(gcr_reg + cfg->reg0),
+ BIT(cfg->bit0));
+ }
+ if (cfg->reg1) {
+ if (cfg->fn1 == mode)
+ setbits_le32((uintptr_t)(gcr_reg + cfg->reg1),
+ BIT(cfg->bit1));
+ else
+ clrbits_le32((uintptr_t)(gcr_reg + cfg->reg1),
+ BIT(cfg->bit1));
+ }
+ if (cfg->reg2) {
+ if (cfg->fn2 == mode)
+ setbits_le32((uintptr_t)(gcr_reg + cfg->reg2),
+ BIT(cfg->bit2));
+ else
+ clrbits_le32((uintptr_t)(gcr_reg + cfg->reg2),
+ BIT(cfg->bit2));
+ }
+ if (cfg->reg3) {
+ if (cfg->fn3 == mode)
+ setbits_le32((uintptr_t)(gcr_reg + cfg->reg3),
+ BIT(cfg->bit3));
+ else
+ clrbits_le32((uintptr_t)(gcr_reg + cfg->reg3),
+ BIT(cfg->bit3));
+ }
+ if (cfg->reg4) {
+ if (cfg->fn4 == mode)
+ setbits_le32((uintptr_t)(gcr_reg + cfg->reg4),
+ BIT(cfg->bit4));
+ else
+ clrbits_le32((uintptr_t)(gcr_reg + cfg->reg4),
+ BIT(cfg->bit4));
+ }
+ }
+ }
+}
+
+static int npcm8xx_get_pins_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(npcm8xx_pins);
+}
+
+static const char *npcm8xx_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return npcm8xx_pins[selector].name;
+}
+
+static int npcm8xx_get_groups_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(npcm8xx_groups);
+}
+
+static const char *npcm8xx_get_group_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return npcm8xx_groups[selector].name;
+}
+
+static int npcm8xx_get_functions_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(npcm8xx_funcs);
+}
+
+static const char *npcm8xx_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return npcm8xx_funcs[selector].name;
+}
+
+static int npcm8xx_pinmux_set(struct udevice *dev, unsigned int group,
+ unsigned int function)
+{
+ dev_dbg(dev, "set_mux: %d, %d[%s]\n", function, group,
+ npcm8xx_groups[group].name);
+
+ npcm8xx_setfunc(dev, npcm8xx_groups[group].pins,
+ npcm8xx_groups[group].npins, group);
+
+ return 0;
+}
+
+#define PIN_CONFIG_PERSIST_STATE (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_POLARITY_STATE (PIN_CONFIG_END + 2)
+#define PIN_CONFIG_EVENT_CLEAR (PIN_CONFIG_END + 3)
+
+static const struct pinconf_param npcm8xx_conf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+ { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
+ { "output-high", PIN_CONFIG_OUTPUT, 1, },
+ { "output-low", PIN_CONFIG_OUTPUT, 0, },
+ { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 1 },
+ { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 1 },
+ { "persist-enable", PIN_CONFIG_PERSIST_STATE, 1 },
+ { "persist-disable", PIN_CONFIG_PERSIST_STATE, 0 },
+ { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
+ { "active-high", PIN_CONFIG_POLARITY_STATE, 0 },
+ { "active-low", PIN_CONFIG_POLARITY_STATE, 1 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
+ { "event-clear", PIN_CONFIG_EVENT_CLEAR, 0},
+};
+
+static bool is_gpio_persist(struct udevice *dev, enum reset_type type, unsigned int bank)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+ u32 base = priv->clk_base;
+
+ u8 offset = bank + GPIOX_MODULE_RESET;
+ u32 mask = 1 << offset;
+
+ dev_dbg(dev, "reboot reason: 0x%x\n", type);
+
+ switch (type) {
+ case (PORST_TYPE):
+ return false;
+ case (CORST_TYPE):
+ return !((readl((uintptr_t)(base + NPCM8XX_RST_CORSTC)) & mask) >> offset);
+ case (WD0RST_TYPE):
+ return !((readl((uintptr_t)(base + NPCM8XX_RST_WD0RCR)) & mask) >> offset);
+ case (WD1RST_TYPE):
+ return !((readl((uintptr_t)(base + NPCM8XX_RST_WD1RCR)) & mask) >> offset);
+ case (WD2RST_TYPE):
+ return !((readl((uintptr_t)(base + NPCM8XX_RST_WD2RCR)) & mask) >> offset);
+ default:
+ return false;
+ }
+}
+
+static int npcm8xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum,
+ unsigned int enable)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+ u32 base = priv->clk_base;
+
+ dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable);
+
+ if (enable) {
+ clrbits_le32((uintptr_t)(base + NPCM8XX_RST_WD0RCR),
+ BIT(GPIOX_MODULE_RESET + banknum));
+ clrbits_le32((uintptr_t)(base + NPCM8XX_RST_WD1RCR),
+ BIT(GPIOX_MODULE_RESET + banknum));
+ clrbits_le32((uintptr_t)(base + NPCM8XX_RST_WD2RCR),
+ BIT(GPIOX_MODULE_RESET + banknum));
+ clrbits_le32((uintptr_t)(base + NPCM8XX_RST_CORSTC),
+ BIT(GPIOX_MODULE_RESET + banknum));
+ } else {
+ setbits_le32((uintptr_t)(base + NPCM8XX_RST_WD0RCR),
+ BIT(GPIOX_MODULE_RESET + banknum) | CA9C_MODULE_RESET);
+ setbits_le32((uintptr_t)(base + NPCM8XX_RST_WD1RCR),
+ BIT(GPIOX_MODULE_RESET + banknum) | CA9C_MODULE_RESET);
+ setbits_le32((uintptr_t)(base + NPCM8XX_RST_WD2RCR),
+ BIT(GPIOX_MODULE_RESET + banknum) | CA9C_MODULE_RESET);
+ setbits_le32((uintptr_t)(base + NPCM8XX_RST_CORSTC),
+ BIT(GPIOX_MODULE_RESET + banknum) | CA9C_MODULE_RESET);
+ }
+
+ return 0;
+}
+
+/* Set drive strength for a pin, if supported */
+static int npcm8xx_set_drive_strength(struct udevice *dev,
+ unsigned int pin, unsigned int nval)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned int bank = pin / NPCM8XX_GPIO_PER_BANK;
+ unsigned int gpio = (pin % NPCM8XX_GPIO_PER_BITS);
+ u32 base = priv->gpio_base + (NPCM8XX_GPIO_BANK_OFFSET * bank);
+ unsigned int v;
+
+ v = (pincfgs[pin].flag & DRIVE_STRENGTH_MASK);
+ if (!nval || !v)
+ return -EOPNOTSUPP;
+
+ if (DSLO(v) == nval) {
+ dev_dbg(dev,
+ "setting pin %d to low strength [%d]\n", pin, nval);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_ODSC), BIT(gpio));
+ return 0;
+ } else if (DSHI(v) == nval) {
+ dev_dbg(dev,
+ "setting pin %d to high strength [%d]\n", pin, nval);
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_ODSC), BIT(gpio));
+ return 0;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+/* Set slew rate of pin (high/low) */
+static int npcm8xx_set_slew_rate(struct udevice *dev, unsigned int pin, unsigned int arg)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned int bank = pin / NPCM8XX_GPIO_PER_BANK;
+ unsigned int gpio = (pin % NPCM8XX_GPIO_PER_BITS);
+ u32 base = priv->gpio_base + (NPCM8XX_GPIO_BANK_OFFSET * bank);
+
+ if (pincfgs[pin].flag & SLEW) {
+ switch (arg) {
+ case 0:
+ dev_dbg(dev,
+ "setting pin %d slew rate to low\n", pin);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OSRC), BIT(gpio));
+ return 0;
+ case 1:
+ dev_dbg(dev,
+ "setting pin %d slew rate to high\n", pin);
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OSRC), BIT(gpio));
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+ }
+
+ /* LPC Slew rate in SRCNT register */
+ if (pincfgs[pin].flag & SLEWLPC) {
+ switch (arg) {
+ case 0:
+ dev_dbg(dev,
+ "setting LPC/ESPI(%d) slew rate to low\n", pin);
+ clrbits_le32((uintptr_t)(priv->gcr_base + NPCM8XX_GCR_SRCNT), SRCNT_ESPI);
+ return 0;
+ case 1:
+ dev_dbg(dev,
+ "setting LPC/ESPI(%d) slew rate to high\n", pin);
+ setbits_le32((uintptr_t)(priv->gcr_base + NPCM8XX_GCR_SRCNT), SRCNT_ESPI);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int pin,
+ unsigned int param, unsigned int arg)
+{
+ struct npcm8xx_pinctrl_priv *priv = dev_get_priv(dev);
+ int err = 0;
+ unsigned int bank = pin / NPCM8XX_GPIO_PER_BANK;
+ unsigned int gpio = (pin % NPCM8XX_GPIO_PER_BITS);
+ u32 base = priv->gpio_base + (0x1000 * bank);
+
+ npcm8xx_setfunc(dev, (const unsigned int *)&pin, 1, fn_gpio);
+
+ /* To prevent unexpected IRQ trap at verctor 00 in linux kernel */
+ if (param == PIN_CONFIG_EVENT_CLEAR) {
+ dev_dbg(dev, "set pin %d event clear\n", pin);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_EVEN), BIT(gpio));
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_EVST), BIT(gpio));
+ return err;
+ }
+
+ // allow set persist state disable
+ if (param == PIN_CONFIG_PERSIST_STATE) {
+ npcm8xx_gpio_reset_persist(dev, bank, arg);
+ return err;
+ }
+
+ if (is_gpio_persist(dev, npcm8xx_reset_reason(), bank))
+ return err;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ dev_dbg(dev, "set pin %d bias dsiable\n", pin);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_PU), BIT(gpio));
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_PD), BIT(gpio));
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ dev_dbg(dev, "set pin %d bias pull down\n", pin);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_PU), BIT(gpio));
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_PD), BIT(gpio));
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ dev_dbg(dev, "set pin %d bias pull up\n", pin);
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_PU), BIT(gpio));
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_PD), BIT(gpio));
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ dev_dbg(dev, "set pin %d input enable\n", pin);
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OEC), BIT(gpio));
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_IEM), BIT(gpio));
+ break;
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ dev_dbg(dev, "set pin %d output enable\n", pin);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_IEM), BIT(gpio));
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OES), BIT(gpio));
+ case PIN_CONFIG_OUTPUT:
+ dev_dbg(dev, "set pin %d output %d\n", pin, arg);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_IEM), BIT(gpio));
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OES), BIT(gpio));
+ if (arg)
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_DOUT), BIT(gpio));
+ else
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_DOUT), BIT(gpio));
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ dev_dbg(dev, "set pin %d push pull\n", pin);
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OTYP), BIT(gpio));
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ dev_dbg(dev, "set pin %d open drain\n", pin);
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_OTYP), BIT(gpio));
+ break;
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ dev_dbg(dev, "set pin %d input debounce\n", pin);
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_DBNC), BIT(gpio));
+ break;
+ case PIN_CONFIG_POLARITY_STATE:
+ dev_dbg(dev, "set pin %d active %d\n", pin, arg);
+ if (arg)
+ setbits_le32((uintptr_t)(base + NPCM8XX_GP_N_POL), BIT(gpio));
+ else
+ clrbits_le32((uintptr_t)(base + NPCM8XX_GP_N_POL), BIT(gpio));
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ dev_dbg(dev, "set pin %d driver strength %d\n", pin, arg);
+ err = npcm8xx_set_drive_strength(dev, pin, arg);
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ dev_dbg(dev, "set pin %d slew rate %d\n", pin, arg);
+ err = npcm8xx_set_slew_rate(dev, pin, arg);
+ break;
+ default:
+ err = -EOPNOTSUPP;
+ }
+ return err;
+}
+
+static struct pinctrl_ops npcm8xx_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .get_pins_count = npcm8xx_get_pins_count,
+ .get_pin_name = npcm8xx_get_pin_name,
+ .get_groups_count = npcm8xx_get_groups_count,
+ .get_group_name = npcm8xx_get_group_name,
+ .get_functions_count = npcm8xx_get_functions_count,
+ .get_function_name = npcm8xx_get_function_name,
+ .pinmux_set = npcm8xx_pinmux_set,
+ .pinmux_group_set = npcm8xx_pinmux_set,
+ .pinconf_num_params = ARRAY_SIZE(npcm8xx_conf_params),
+ .pinconf_params = npcm8xx_conf_params,
+ .pinconf_set = npcm8xx_pinconf_set,
+ .pinconf_group_set = npcm8xx_pinconf_set,
+};
+
+static const struct udevice_id npcm8xx_pinctrl_ids[] = {
+ { .compatible = "nuvoton,npcm845-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_npcm8xx) = {
+ .name = "nuvoton_npcm8xx_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = npcm8xx_pinctrl_ids,
+ .priv_auto = sizeof(struct npcm8xx_pinctrl_priv),
+ .ops = &npcm8xx_pinctrl_ops,
+ .probe = npcm8xx_pinctrl_probe,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 7/9] spi: npcm-fiu: add NPCM8xx FIU controller driver
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
` (5 preceding siblings ...)
2021-12-15 2:57 ` [PATCH v1 6/9] pinctrl: nuvoton: Add NPCM8xx pinctrl driver Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 2:57 ` [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree Stanley Chu
2021-12-15 2:58 ` [PATCH v1 9/9] ARM: configs: Add defconfig for Nuvoton NPCM845 Stanley Chu
8 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master
controller driver using SPI-MEM interface.
The FIU supports single, dual or quad communication interface.
The FIU controller driver provides flash access in UMA(User
Mode Access) mode by using an indirect address/data mechanism.
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
arch/arm/include/asm/arch-npcm8xx/fiu.h | 61 +++++
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/npcm_fiu_spi.c | 311 ++++++++++++++++++++++++
4 files changed, 379 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/fiu.h
create mode 100644 drivers/spi/npcm_fiu_spi.c
diff --git a/arch/arm/include/asm/arch-npcm8xx/fiu.h b/arch/arm/include/asm/arch-npcm8xx/fiu.h
new file mode 100644
index 0000000000..22fc66dd9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/fiu.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_FIU_H_
+#define _NPCM_FIU_H_
+
+#define CHUNK_SIZE 16
+
+/* FIU UMA Configuration Register (FIU_UMA_CFG) */
+#define FIU_UMA_CFG_LCK 31
+#define FIU_UMA_CFG_CMMLCK 30
+#define FIU_UMA_CFG_RDATSIZ 24
+#define FIU_UMA_CFG_DBSIZ 21
+#define FIU_UMA_CFG_WDATSIZ 16
+#define FIU_UMA_CFG_ADDSIZ 11
+#define FIU_UMA_CFG_CMDSIZ 10
+#define FIU_UMA_CFG_RDBPCK 8
+#define FIU_UMA_CFG_DBPCK 6
+#define FIU_UMA_CFG_WDBPCK 4
+#define FIU_UMA_CFG_ADBPCK 2
+#define FIU_UMA_CFG_CMBPCK 0
+
+/* FIU UMA Control and Status Register (FIU_UMA_CTS) */
+#define FIU_UMA_CTS_SW_CS 16
+#define FIU_UMA_CTS_DEV_NUM 8
+#define FIU_UMA_CTS_EXEC_DONE 0
+
+struct npcm_fiu_regs {
+ unsigned int drd_cfg;
+ unsigned int dwr_cfg;
+ unsigned int uma_cfg;
+ unsigned int uma_cts;
+ unsigned int uma_cmd;
+ unsigned int uma_addr;
+ unsigned int prt_cfg;
+ unsigned char res1[4];
+ unsigned int uma_dw0;
+ unsigned int uma_dw1;
+ unsigned int uma_dw2;
+ unsigned int uma_dw3;
+ unsigned int uma_dr0;
+ unsigned int uma_dr1;
+ unsigned int uma_dr2;
+ unsigned int uma_dr3;
+ unsigned int prt_cmd0;
+ unsigned int prt_cmd1;
+ unsigned int prt_cmd2;
+ unsigned int prt_cmd3;
+ unsigned int prt_cmd4;
+ unsigned int prt_cmd5;
+ unsigned int prt_cmd6;
+ unsigned int prt_cmd7;
+ unsigned int prt_cmd8;
+ unsigned int prt_cmd9;
+ unsigned int stuff[4];
+ unsigned int fiu_cfg;
+};
+
+#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d07e9a28af..a7b8f2fa1b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -474,6 +474,12 @@ config ZYNQMP_GQSPI
This option is used to enable ZynqMP QSPI controller driver which
is used to communicate with qspi flash devices.
+config NPCM_FIU_SPI
+ bool "FIU driver for Nuvoton NPCM SoC"
+ help
+ This enables support for the Flash Interface Unit SPI controller
+ in master mode.
+
endif # if DM_SPI
config FSL_ESPI
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d2f24bccef..4d1be1bb67 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o
+obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c
new file mode 100644
index 0000000000..38b87cc4ac
--- /dev/null
+++ b/drivers/spi/npcm_fiu_spi.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <linux/iopoll.h>
+#include <linux/log2.h>
+#include <asm/arch/fiu.h>
+
+struct npcm_fiu_priv {
+ struct npcm_fiu_regs *regs;
+};
+
+static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
+{
+ return 0;
+}
+
+static int npcm_fiu_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static inline void activate_cs(struct npcm_fiu_regs *regs, int cs)
+{
+ writel((cs & 0x3) << FIU_UMA_CTS_DEV_NUM, ®s->uma_cts);
+}
+
+static inline void deactivate_cs(struct npcm_fiu_regs *regs)
+{
+ writel((1 << FIU_UMA_CTS_SW_CS), ®s->uma_cts);
+}
+
+static int fiu_uma_read(struct udevice *bus, u8 *buf, u32 data_size)
+{
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+ struct npcm_fiu_regs *regs = priv->regs;
+ u32 data_reg[4];
+ u32 val;
+ int ret;
+
+ /* Set data size */
+ writel((data_size << FIU_UMA_CFG_RDATSIZ), ®s->uma_cfg);
+
+ /* Initiate the read */
+ writel(readl(®s->uma_cts) | (1 << FIU_UMA_CTS_EXEC_DONE), ®s->uma_cts);
+
+ /* Wait for completion */
+ ret = readl_poll_timeout(®s->uma_cts, val,
+ !(val & (1 << FIU_UMA_CTS_EXEC_DONE)), 1000000);
+ if (ret) {
+ printf("npcm_fiu: read timeout\n");
+ return ret;
+ }
+
+ /* Copy data from data registers */
+ if (data_size >= 1)
+ data_reg[0] = readl(®s->uma_dr0);
+ if (data_size >= 5)
+ data_reg[1] = readl(®s->uma_dr1);
+ if (data_size >= 9)
+ data_reg[2] = readl(®s->uma_dr2);
+ if (data_size >= 13)
+ data_reg[3] = readl(®s->uma_dr3);
+
+ memcpy(buf, data_reg, data_size);
+
+ return 0;
+}
+
+static int fiu_uma_write(struct udevice *bus, const u8 *buf, u32 data_size)
+{
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+ struct npcm_fiu_regs *regs = priv->regs;
+ u32 data_reg[4];
+ u32 val;
+ int ret;
+
+ /* Set data size */
+ writel((data_size << FIU_UMA_CFG_WDATSIZ), ®s->uma_cfg);
+
+ /* Write data to data registers */
+ memcpy(data_reg, buf, data_size);
+
+ if (data_size >= 1)
+ writel(data_reg[0], ®s->uma_dw0);
+ if (data_size >= 5)
+ writel(data_reg[1], ®s->uma_dw1);
+ if (data_size >= 9)
+ writel(data_reg[2], ®s->uma_dw2);
+ if (data_size >= 13)
+ writel(data_reg[3], ®s->uma_dw3);
+
+ /* Initiate the transaction */
+ writel(readl(®s->uma_cts) | (1 << FIU_UMA_CTS_EXEC_DONE), ®s->uma_cts);
+
+ /* Wait for completion */
+ ret = readl_poll_timeout(®s->uma_cts, val,
+ !(val & (1 << FIU_UMA_CTS_EXEC_DONE)), 1000000);
+ if (ret)
+ printf("npcm_fiu: write timeout\n");
+
+ return ret;
+}
+
+static int npcm_fiu_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+ struct npcm_fiu_regs *regs = priv->regs;
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+ const u8 *tx = dout;
+ u8 *rx = din;
+ int bytes = bitlen / 8;
+ int ret = 0;
+ int len;
+
+ if (flags & SPI_XFER_BEGIN)
+ activate_cs(regs, slave_plat->cs);
+
+ while (bytes) {
+ len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes;
+ if (tx) {
+ ret = fiu_uma_write(bus, tx, len);
+ if (ret)
+ break;
+ tx += len;
+ } else {
+ ret = fiu_uma_read(bus, rx, len);
+ if (ret)
+ break;
+ rx += len;
+ }
+ bytes -= len;
+ }
+
+ if (flags & SPI_XFER_END)
+ deactivate_cs(regs);
+
+ return ret;
+}
+
+static int npcm_fiu_uma_operation(struct npcm_fiu_priv *priv, const struct spi_mem_op *op,
+ u32 addr, const u8 *tx, u8 *rx, u32 nbytes, bool started)
+{
+ struct npcm_fiu_regs *regs = priv->regs;
+ u32 uma_cfg = 0, val;
+ u32 *data32;
+ int ret;
+
+ debug("fiu_uma: opcode 0x%x, dir %d, addr 0x%x, %d bytes\n",
+ op->cmd.opcode, op->data.dir, addr, nbytes);
+ debug(" buswidth cmd:%d, addr:%d, dummy:%d, data:%d\n",
+ op->cmd.buswidth, op->addr.buswidth, op->dummy.buswidth,
+ op->data.buswidth);
+ debug(" size cmd:%d, addr:%d, dummy:%d, data:%d\n",
+ 1, op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
+ debug(" tx %p, rx %p\n", tx, rx);
+
+ if (!started) {
+ /* Send cmd in the begin of an transaction */
+ writel(op->cmd.opcode, ®s->uma_cmd);
+
+ uma_cfg |= (ilog2(op->cmd.buswidth) << FIU_UMA_CFG_CMBPCK) |
+ (1 << FIU_UMA_CFG_CMDSIZ);
+ if (op->addr.nbytes) {
+ uma_cfg |= ilog2(op->addr.buswidth) << FIU_UMA_CFG_ADBPCK |
+ (op->addr.nbytes & 0x7) << FIU_UMA_CFG_ADDSIZ;
+ writel(addr, ®s->uma_addr);
+ }
+ if (op->dummy.nbytes)
+ uma_cfg |= ilog2(op->dummy.buswidth) << FIU_UMA_CFG_DBPCK |
+ (op->dummy.nbytes & 0x7) << FIU_UMA_CFG_DBSIZ;
+ }
+ if (op->data.dir == SPI_MEM_DATA_IN && nbytes)
+ uma_cfg |= ilog2(op->data.buswidth) << FIU_UMA_CFG_RDBPCK |
+ (nbytes & 0x1f) << FIU_UMA_CFG_RDATSIZ;
+ else if (op->data.dir == SPI_MEM_DATA_OUT && nbytes)
+ uma_cfg |= ilog2(op->data.buswidth) << FIU_UMA_CFG_WDBPCK |
+ (nbytes & 0x1f) << FIU_UMA_CFG_WDATSIZ;
+ writel(uma_cfg, ®s->uma_cfg);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT && nbytes) {
+ data32 = (u32 *)tx;
+ if (nbytes >= 1)
+ writel(*data32++, ®s->uma_dw0);
+ if (nbytes >= 5)
+ writel(*data32++, ®s->uma_dw1);
+ if (nbytes >= 9)
+ writel(*data32++, ®s->uma_dw2);
+ if (nbytes >= 13)
+ writel(*data32++, ®s->uma_dw3);
+ }
+ /* Initiate the transaction */
+ writel(readl(®s->uma_cts) | (1 << FIU_UMA_CTS_EXEC_DONE), ®s->uma_cts);
+
+ /* Wait for completion */
+ ret = readl_poll_timeout(®s->uma_cts, val,
+ !(val & (1 << FIU_UMA_CTS_EXEC_DONE)), 1000000);
+ if (ret) {
+ printf("npcm_fiu: UMA op timeout\n");
+ return ret;
+ }
+
+ if (op->data.dir == SPI_MEM_DATA_IN && nbytes) {
+ data32 = (u32 *)rx;
+ if (nbytes >= 1)
+ *data32++ = readl(®s->uma_dr0);
+ if (nbytes >= 5)
+ *data32++ = readl(®s->uma_dr1);
+ if (nbytes >= 9)
+ *data32++ = readl(®s->uma_dr2);
+ if (nbytes >= 13)
+ *data32++ = readl(®s->uma_dr3);
+ }
+
+ return 0;
+}
+
+static int npcm_fiu_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct udevice *bus = slave->dev->parent;
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+ struct npcm_fiu_regs *regs = priv->regs;
+ struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
+ u32 bytes, len;
+ const u8 *tx;
+ u8 *rx;
+ int ret;
+ bool started = false;
+ u32 addr;
+
+ bytes = op->data.nbytes;
+ addr = (u32)op->addr.val;
+ if (!bytes) {
+ activate_cs(regs, slave_plat->cs);
+ ret = npcm_fiu_uma_operation(priv, op, addr, NULL, NULL, 0, started);
+ started = true;
+ goto end;
+ }
+
+ tx = op->data.buf.out;
+ rx = op->data.buf.in;
+ while (bytes) {
+ if (!started)
+ activate_cs(regs, slave_plat->cs);
+
+ len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes;
+ ret = npcm_fiu_uma_operation(priv, op, addr, tx, rx, len, started);
+ started = true;
+ if (ret)
+ break;
+ bytes -= len;
+ addr += len;
+ if (tx)
+ tx += len;
+ if (rx)
+ rx += len;
+
+ if (started && op->data.dir != SPI_MEM_DATA_OUT) {
+ deactivate_cs(regs);
+ started = false;
+ }
+ }
+end:
+ if (started)
+ deactivate_cs(regs);
+
+ return ret;
+}
+
+static int npcm_fiu_spi_probe(struct udevice *bus)
+{
+ struct npcm_fiu_priv *priv = dev_get_priv(bus);
+
+ priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
+ .exec_op = npcm_fiu_exec_op,
+};
+
+static const struct dm_spi_ops npcm_fiu_spi_ops = {
+ .xfer = npcm_fiu_spi_xfer,
+ .set_speed = npcm_fiu_spi_set_speed,
+ .set_mode = npcm_fiu_spi_set_mode,
+ .mem_ops = &npcm_fiu_mem_ops,
+};
+
+static const struct udevice_id npcm_fiu_spi_ids[] = {
+ { .compatible = "nuvoton,npcm845-fiu" },
+ { .compatible = "nuvoton,npcm750-fiu" },
+ { }
+};
+
+U_BOOT_DRIVER(npcm_fiu_spi) = {
+ .name = "npcm_fiu_spi",
+ .id = UCLASS_SPI,
+ .of_match = npcm_fiu_spi_ids,
+ .ops = &npcm_fiu_spi_ops,
+ .priv_auto = sizeof(struct npcm_fiu_priv),
+ .probe = npcm_fiu_spi_probe,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
` (6 preceding siblings ...)
2021-12-15 2:57 ` [PATCH v1 7/9] spi: npcm-fiu: add NPCM8xx FIU controller driver Stanley Chu
@ 2021-12-15 2:57 ` Stanley Chu
2021-12-15 13:07 ` Tom Rini
2021-12-15 2:58 ` [PATCH v1 9/9] ARM: configs: Add defconfig for Nuvoton NPCM845 Stanley Chu
8 siblings, 1 reply; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:57 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add a common device tree for all Nuvoton NPCM8xx BMCs and a board
specific device tree for the NPCM845(Arbel) evaluation board.
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 598 ++++++
arch/arm/dts/nuvoton-npcm845-evb.dts | 264 +++
arch/arm/dts/nuvoton-npcm845-pincfg.dtsi | 2007 +++++++++++++++++++++
arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi | 623 +++++++
5 files changed, 3494 insertions(+)
create mode 100644 arch/arm/dts/nuvoton-common-npcm8xx.dtsi
create mode 100644 arch/arm/dts/nuvoton-npcm845-evb.dts
create mode 100644 arch/arm/dts/nuvoton-npcm845-pincfg.dtsi
create mode 100644 arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7f622fedbd..b866d488c5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1162,6 +1162,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
+dtb-$(CONFIG_TARGET_ARBEL_EVB) += nuvoton-npcm845-evb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
new file mode 100644
index 0000000000..175c8af878
--- /dev/null
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -0,0 +1,598 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dt-bindings/clock/npcm845-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "nuvoton-npcm8xx-pinctrl.dtsi"
+
+/ {
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clks: clock-control@f0801000 {
+ compatible = "nuvoton,npcm845-clock";
+ #clock-cells = <1>;
+ reg = <0x0 0xf0801000 0x0 0x70>;
+ u-boot,dm-pre-reloc;
+ };
+
+ serial0: serial0@f0000000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0000000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ serial1: serial1@f0001000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0001000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ serial2: serial2@f0002000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0002000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ serial3: serial3@f0003000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0003000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ serial4: serial4@f0004000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0004000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ serial5: serial5@f0005000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0005000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ serial6: serial6@f0006000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0xf0006000 0x0 0x20>;
+ clocks = <&clks CLK_UART>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ timer0: timer@f0008000 {
+ compatible = "nuvoton,npcm845-timer";
+ reg = <0x0 0xF0008000 0x0 0x100>;
+ clock-frequency = <25000000>;
+ };
+
+ fiu0: fiu0@fb000000 {
+ compatible = "nuvoton,npcm845-fiu";
+ reg = <0x0 0xfb000000 0x0 0x1000>;
+ spi-max-frequency = <66000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0cs1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fiu1: fiu1@fb002000 {
+ compatible = "nuvoton,npcm845-fiu";
+ reg = <0x0 0xfb002000 0x0 0x1000>;
+ spi-max-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fiu3: fiu3@c0000000 {
+ compatible = "nuvoton,npcm845-fiu";
+ reg = <0x0 0xc0000000 0x0 0x1000>;
+ spi-max-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fiux: fiux@fb001000 {
+ compatible = "nuvoton,npcm845-fiu";
+ reg = <0x0 0xfb001000 0x0 0x1000>;
+ spi-max-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spix_pins &spixcs1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pspi: pspi@f0201000 {
+ compatible = "nuvoton,npcm845-pspi";
+ reg = <0x0 0xf0201000 0x0 0x1000>;
+ spi-max-frequency = <20000000>;
+ clocks = <&clks CLK_APB5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pspi_pins>;
+ status = "disabled";
+ };
+
+ sdhci: sdhci@f0842000 {
+ compatible = "nuvoton,npcm845-sdhci";
+ reg = <0x0 0xf0842000 0x0 0x2000>;
+ clocks = <&clks CLK_EMMC>;
+ clock-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc_pins
+ &mmc8_pins>;
+ status = "disabled";
+ };
+
+ otp: otp@f0189000 {
+ compatible = "nuvoton,npcm845-otp";
+ reg = <0x0 0xf0189000 0x0 0x1000>;
+ clocks = <&clks CLK_APB4>;
+ status = "disabled";
+ };
+
+ rng: rng@f000b000 {
+ compatible = "nuvoton,npcm845-rng";
+ reg = <0x0 0xf000b000 0x0 0x1000>;
+ clocks = <&clks CLK_APB1>;
+ status = "disabled";
+ };
+
+ aes: aes@f0858000 {
+ compatible = "nuvoton,npcm845-aes";
+ reg = <0x0 0xf0858000 0x0 0x1000>;
+ clocks = <&clks CLK_AHB>;
+ clock-names = "clk_ahb";
+ status = "disabled";
+ };
+
+ sha: sha@f085a000 {
+ compatible = "nuvoton,npcm845-sha";
+ reg = <0x0 0xf085a000 0x0 0x1000>;
+ clocks = <&clks CLK_AHB>;
+ clock-names = "clk_ahb";
+ status = "disabled";
+ };
+
+ gpio0: gpio0@f0010000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0010000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio0";
+ };
+
+ gpio1: gpio1@f0011000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0011000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio1";
+ };
+
+ gpio2: gpio2@f0012000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0012000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio2";
+ };
+
+ gpio3: gpio3@f0013000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0013000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio3";
+ };
+
+ gpio4: gpio4@f0014000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0014000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio4";
+ };
+
+ gpio5: gpio5@f0015000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0015000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio5";
+ };
+
+ gpio6: gpio6@f0016000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0016000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio6";
+ };
+
+ gpio7: gpio7@f0017000 {
+ compatible = "nuvoton,npcm845-gpio";
+ reg = <0x0 0xf0017000 0x0 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio7";
+ };
+
+ gmac1: gmac1 {
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xF0802000 0x0 0x2000>;
+ phy-mode = "sgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sg1mdio_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio5 30 GPIO_ACTIVE_LOW>; /* gpio190 */
+ status = "disabled";
+ };
+
+ gmac2: gmac2 {
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xF0804000 0x0 0x2000>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rg2_pins
+ &rg2mdio_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; /* gpio162 */
+ status = "disabled";
+ };
+
+ gmac3: gmac3 { /* GMAC3-RMII1 */
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xF0806000 0x0 0x2000>;
+ phy-mode = "mii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r1_pins
+ &r1md_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio94 */
+ status = "disabled";
+ };
+
+ gmac4: gmac4 { /* GMAC4-RMII2 */
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xF0808000 0x0 0x2000>;
+ phy-mode = "mii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2md_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio93 */
+ status = "disabled";
+ };
+
+ usb_dev0: usb-dev0@f0830100 {
+ compatible = "nuvoton,npcm845-usbd";
+ reg = <0x0 0xF0830100 0x0 0x200>;
+ /* choose Phy: 1 for device 0-9 / 2 for device 9 / 3 for device 8 */
+ usbphy = <1>;
+ /* choose device : 0-9, note the phy limitation above */
+ usbdev = <0>;
+ status = "disabled";
+ };
+
+ usb_eh1: usb-eh1@f0828100 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xF0828100 0x0 0x100>;
+ status = "disabled";
+ };
+
+ usb_oh1: usb-oh1@f0829000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xF0829000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ usb_eh2: usb-eh2@f082a100 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xF082A100 0x0 0x100>;
+ status = "disabled";
+ };
+
+ usb_oh2: usb-oh2@f082b000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xF082B000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ i2c0: i2c-bus@f0080000 {
+ reg = <0x0 0xf0080000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb0_pins>;
+ status = "disabled";
+ };
+
+ i2c1: i2c-bus@f0081000 {
+ reg = <0x0 0xf0081000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb1_pins>;
+ status = "disabled";
+ };
+
+ i2c2: i2c-bus@f0082000 {
+ reg = <0x0 0xf0082000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb2_pins>;
+ status = "disabled";
+ };
+
+ i2c3: i2c-bus@f0083000 {
+ reg = <0x0 0xf0083000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb3_pins>;
+ status = "disabled";
+ };
+
+ i2c4: i2c-bus@f0084000 {
+ reg = <0x0 0xf0084000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb4_pins>;
+ status = "disabled";
+ };
+
+ i2c5: i2c-bus@f0085000 {
+ reg = <0x0 0xf0085000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb5_pins>;
+ status = "disabled";
+ };
+
+ i2c6: i2c-bus@f0086000 {
+ reg = <0x0 0xf0086000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb6_pins>;
+ status = "disabled";
+ };
+
+ i2c7: i2c-bus@f0087000 {
+ reg = <0x0 0xf0087000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb7_pins>;
+ status = "disabled";
+ };
+
+ i2c8: i2c-bus@f0088000 {
+ reg = <0x0 0xf0088000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb8_pins>;
+ status = "disabled";
+ };
+
+ i2c9: i2c-bus@f0089000 {
+ reg = <0x0 0xf0089000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb9_pins>;
+ status = "disabled";
+ };
+
+ i2c10: i2c-bus@f008a000 {
+ reg = <0x0 0xf008a000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb10_pins>;
+ status = "disabled";
+ };
+
+ i2c11: i2c-bus@f008b000 {
+ reg = <0x0 0xf008b000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb11_pins>;
+ status = "disabled";
+ };
+
+ i2c12: i2c-bus@f008c000 {
+ reg = <0x0 0xf008c000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb12_pins>;
+ status = "disabled";
+ };
+
+ i2c13: i2c-bus@f008d000 {
+ reg = <0x0 0xf008d000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb13_pins>;
+ status = "disabled";
+ };
+
+ i2c14: i2c-bus@f008e000 {
+ reg = <0x0 0xf008e000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb14_pins>;
+ status = "disabled";
+ };
+
+ i2c15: i2c-bus@f008f000 {
+ reg = <0x0 0xf008f000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb15_pins>;
+ status = "disabled";
+ };
+
+ i2c16: i2c-bus@fff00000 {
+ reg = <0x0 0xfff00000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb16_pins>;
+ status = "disabled";
+ };
+
+ i2c17: i2c-bus@fff01000 {
+ reg = <0x0 0xfff01000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb17_pins>;
+ status = "disabled";
+ };
+
+ i2c18: i2c-bus@fff02000 {
+ reg = <0x0 0xfff02000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb18_pins>;
+ status = "disabled";
+ };
+
+ i2c19: i2c-bus@fff03000 {
+ reg = <0x0 0xfff03000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb19_pins>;
+ status = "disabled";
+ };
+
+ i2c20: i2c-bus@fff04000 {
+ reg = <0x0 0xfff04000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb20_pins>;
+ status = "disabled";
+ };
+
+ i2c21: i2c-bus@fff05000 {
+ reg = <0x0 0xfff05000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb21_pins>;
+ status = "disabled";
+ };
+
+ i2c22: i2c-bus@fff06000 {
+ reg = <0x0 0xfff06000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb22_pins>;
+ status = "disabled";
+ };
+
+ i2c23: i2c-bus@fff07000 {
+ reg = <0x0 0xfff07000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb23_pins>;
+ status = "disabled";
+ };
+
+ i2c24: i2c-bus@fff08000 {
+ reg = <0x0 0xfff08000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb8_pins>;
+ status = "disabled";
+ };
+
+ i2c25: i2c-bus@fff09000 {
+ reg = <0x0 0xfff09000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb9_pins>;
+ status = "disabled";
+ };
+
+ i2c26: i2c-bus@fff0a000 {
+ reg = <0x0 0xfff0a000 0x0 0x1000>;
+ compatible = "nuvoton,npcm845-i2c";
+ clocks = <&clks CLK_APB2>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb10_pins>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@f0800000 {
+ compatible = "nuvoton,npcm845-pinctrl";
+ };
+
+};
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
new file mode 100644
index 0000000000..f137320c70
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+#include "nuvoton-common-npcm8xx.dtsi"
+#include "nuvoton-npcm845-pincfg.dtsi"
+
+/ {
+ model = "Nuvoton npcm845 EVB Development Board";
+ compatible = "nuvoton,arbel", "nuvoton,npcm845";
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ aliases {
+ serial0 = &serial0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ i2c16 = &i2c16;
+ i2c17 = &i2c17;
+ i2c18 = &i2c18;
+ i2c19 = &i2c19;
+ i2c20 = &i2c20;
+ i2c21 = &i2c21;
+ i2c22 = &i2c22;
+ i2c23 = &i2c23;
+ i2c24 = &i2c24;
+ i2c25 = &i2c25;
+ i2c26 = &i2c26;
+ spi0 = &fiu0;
+ spi1 = &fiu1;
+ spi3 = &fiu3;
+ spi4 = &fiux;
+ spi5 = &pspi;
+ mmc0 = &sdhci;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ usb0 = &usb_dev0;
+ usb1 = &usb_eh1;
+ usb2 = &usb_eh2;
+ eth0 = &gmac1;
+ eth1 = &gmac2;
+ eth2 = &gmac3;
+ eth3 = &gmac4;
+ };
+
+ serial0: serial0@f0000000 {
+ status = "okay";
+ };
+
+ fiu0: fiu0@fb000000 {
+ status = "okay";
+ spi_flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* CS 0 */
+ };
+
+ spi_flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>; /* CS 1 */
+ };
+ };
+
+ fiu1: fiu1@fb002000 {
+ status = "okay";
+ spi_flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* CS 0 */
+ };
+ };
+
+ fiu3: fiu3@c0000000 {
+ status = "okay";
+ spi_flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* CS 0 */
+ };
+ };
+
+ pspi: pspi@f0201000 {
+ status = "okay";
+ };
+
+ sdhci: sdhci@f0842000 {
+ status = "okay";
+ };
+
+ otp: otp@f0189000 {
+ status = "okay";
+ };
+
+ rng: rng@f000b000 {
+ status = "okay";
+ };
+
+ aes: aes@f0858000 {
+ status = "okay";
+ };
+
+ sha: sha@f085a000 {
+ status = "okay";
+ };
+
+ gmac1: gmac1 { /* GMAC1- SGMII */
+ status = "okay";
+ };
+
+ gmac2: gmac2 { /* GMAC2- RGMII */
+ status = "okay";
+ };
+
+ gmac4: gmac4 { /* GMAC4- RMII2 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2oen_pins
+ &gpio91o_pins
+ &gpio92o_pins>;
+ snps,bitbang-mii;
+ snps,mdc-gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio91 */
+ snps,mdio-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
+ };
+
+ usb_dev0: usb-dev0@f0830100 {
+ status = "okay";
+ };
+
+ usb_eh1: usb-eh1@f0828100 {
+ status = "okay";
+ };
+
+ usb_eh2: usb-eh2@f082a100 {
+ status = "okay";
+ };
+
+ i2c0: i2c-bus@f0080000 {
+ status = "okay";
+ };
+
+ i2c1: i2c-bus@f0081000 {
+ status = "okay";
+ };
+
+ i2c2: i2c-bus@f0082000 {
+ status = "okay";
+ };
+
+ i2c3: i2c-bus@f0083000 {
+ status = "okay";
+ };
+
+ i2c4: i2c-bus@f0084000 {
+ status = "okay";
+ };
+
+ i2c5: i2c-bus@f0085000 {
+ status = "okay";
+ };
+
+ i2c6: i2c-bus@f0086000 {
+ status = "okay";
+ };
+
+ i2c7: i2c-bus@f0087000 {
+ status = "okay";
+ };
+
+ i2c8: i2c-bus@f0088000 {
+ status = "okay";
+ };
+
+ i2c9: i2c-bus@f0089000 {
+ status = "okay";
+ };
+
+ i2c10: i2c-bus@f008a000 {
+ status = "okay";
+ };
+
+ i2c11: i2c-bus@f008b000 {
+ status = "okay";
+ };
+
+ i2c12: i2c-bus@f008c000 {
+ status = "okay";
+ };
+
+ i2c13: i2c-bus@f008d000 {
+ status = "okay";
+ };
+
+ i2c14: i2c-bus@f008e000 {
+ status = "okay";
+ };
+
+ i2c15: i2c-bus@f008f000 {
+ status = "okay";
+ };
+
+ i2c16: i2c-bus@fff00000 {
+ status = "okay";
+ };
+
+ i2c17: i2c-bus@fff01000 {
+ status = "okay";
+ };
+
+ i2c18: i2c-bus@fff02000 {
+ status = "okay";
+ };
+
+ i2c19: i2c-bus@fff03000 {
+ status = "okay";
+ };
+
+ i2c20: i2c-bus@fff04000 {
+ status = "okay";
+ };
+
+ i2c21: i2c-bus@fff05000 {
+ status = "okay";
+ };
+
+ i2c22: i2c-bus@fff06000 {
+ status = "okay";
+ };
+
+ i2c23: i2c-bus@fff07000 {
+ status = "okay";
+ };
+
+ i2c24: i2c-bus@fff08000 {
+ status = "okay";
+ };
+
+ i2c25: i2c-bus@fff09000 {
+ status = "okay";
+ };
+
+ i2c26: i2c-bus@fff0a000 {
+ status = "okay";
+ };
+
+};
diff --git a/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi b/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi
new file mode 100644
index 0000000000..65de96b1f5
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi
@@ -0,0 +1,2007 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+/ {
+ pinctrl: pinctrl@f0800000 {
+ gpio0o_pins: gpio0o-pins {
+ pins = "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio1_pins: gpio1-pins {
+ pins = "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio2_pins: gpio2-pins {
+ pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio2o_pins: gpio2o-pins {
+ pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA";
+ bias-disable;
+ output_high;
+ };
+ gpio3_pins: gpio3-pins {
+ pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio3o_pins: gpio3o-pins {
+ pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio4_pins: gpio4-pins {
+ pins = "GPIO4/IOX2_DI/SMB1D_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio5_pins: gpio5-pins {
+ pins = "GPIO5/IOX2_LD/SMB1D_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio6_pins: gpio6-pins {
+ pins = "GPIO6/IOX2_CK/SMB2D_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio6o_pins: gpio6o-pins {
+ pins = "GPIO6/IOX2_CK/SMB2D_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio6ol_pins: gpio6ol-pins {
+ pins = "GPIO6/IOX2_CK/SMB2D_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio7_pins: gpio7-pins {
+ pins = "GPIO7/IOX2_D0/SMB2D_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio7o_pins: gpio7o-pins {
+ pins = "GPIO7/IOX2_D0/SMB2D_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio7ol_pins: gpio7ol-pins {
+ pins = "GPIO7/IOX2_D0/SMB2D_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio8_pins: gpio8-pins {
+ pins = "GPIO8/LKGPO1/TP_GPIO0";
+ bias-disable;
+ input-enable;
+ };
+ gpio8ol_pins: gpio8ol-pins {
+ pins = "GPIO8/LKGPO1/TP_GPIO0";
+ bias-disable;
+ output-low;
+ };
+ gpio9_pins: gpio9-pins {
+ pins = "GPIO9/LKGPO2/TP_GPIO1";
+ bias-disable;
+ input-enable;
+ };
+ gpio9o_pins: gpio9o-pins {
+ pins = "GPIO9/LKGPO2/TP_GPIO1";
+ bias-disable;
+ output-high;
+ };
+ gpio9ol_pins: gpio9ol-pins {
+ pins = "GPIO9/LKGPO2/TP_GPIO1";
+ bias-disable;
+ output-low;
+ };
+ gpio10_pins: gpio10-pins {
+ pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio10ol_pins: gpio10ol-pins {
+ pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio11_pins: gpio11-pins {
+ pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio11o_pins: gpio11o-pins {
+ pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio11ol_pins: gpio11ol-pins {
+ pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio12_pins: gpio12-pins {
+ pins = "GPIO12/GSPI_CK/SMB5B_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio12o_pins: gpio12o-pins {
+ pins = "GPIO12/GSPI_CK/SMB5B_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio12ol_pins: gpio12ol-pins {
+ pins = "GPIO12/GSPI_CK/SMB5B_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio13_pins: gpio13-pins {
+ pins = "GPIO13/GSPI_DO/SMB5B_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio13ol_pins: gpio13ol-pins {
+ pins = "GPIO13/GSPI_DO/SMB5B_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio14_pins: gpio14-pins {
+ pins = "GPIO14/GSPI_DI/SMB5C_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio14ol_pins: gpio14ol-pins {
+ pins = "GPIO14/GSPI_DI/SMB5C_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio15_pins: gpio15-pins {
+ pins = "GPIO15/GSPI_CS/SMB5C_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio15o_pins: gpio15o-pins {
+ pins = "GPIO15/GSPI_CS/SMB5C_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio16_pins: gpio16-pins {
+ pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2";
+ bias-disable;
+ input-enable;
+ };
+ gpio16o_pins: gpio16o-pins {
+ pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2";
+ bias-disable;
+ output-high;
+ };
+ gpio16ol_pins: gpio16ol-pins {
+ pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2";
+ bias-disable;
+ output-low;
+ };
+ gpio17_pins: gpio17-pins {
+ pins = "GPIO17/PSPI_DI/CP1_GPIO5";
+ bias-disable;
+ input-enable;
+ };
+ gpio17o_pins: gpio17o-pins {
+ pins = "GPIO17/PSPI_DI/CP1_GPIO5";
+ bias-disable;
+ output-high;
+ };
+ gpio17ol_pins: gpio17ol-pins {
+ pins = "GPIO17/PSPI_DI/CP1_GPIO5";
+ bias-disable;
+ output-low;
+ };
+ gpio18_pins: gpio18-pins {
+ pins = "GPIO18/PSPI_D0/SMB4B_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio18ol_pins: gpio18ol-pins {
+ pins = "GPIO18/PSPI_D0/SMB4B_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio19_pins: gpio19-pins {
+ pins = "GPIO19/PSPI_CK/SMB4B_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio19ol_pins: gpio19ol-pins {
+ pins = "GPIO19/PSPI_CK/SMB4B_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio20_pins: gpio20-pins {
+ pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio20o_pins: gpio20o-pins {
+ pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio20ol_pins: gpio20ol-pins {
+ pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio21_pins: gpio21-pins {
+ pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio21ol_pins: gpio21ol-pins {
+ pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio22_pins: gpio22-pins {
+ pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio22ol_pins: gpio22ol-pins {
+ pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio23_pins: gpio23-pins {
+ pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio23ol_pins: gpio23ol-pins {
+ pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio24_pins: gpio24-pins {
+ pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio24o_pins: gpio24o-pins {
+ pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio24ol_pins: gpio24ol-pins {
+ pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio25_pins: gpio25-pins {
+ pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio25o_pins: gpio25o-pins {
+ pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio25ol_pins: gpio25ol-pins {
+ pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio26_pins: gpio26-pins {
+ pins = "GPIO26/SMB5_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio27_pins: gpio27-pins {
+ pins = "GPIO27/SMB5_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio32_pins: gpio32-pins {
+ pins = "GPIO32/SMB14_SCL/SPI0_nCS1";
+ bias-disable;
+ input-enable;
+ };
+ gpio32o_pins: gpio32o-pins {
+ pins = "GPIO32/SMB14_SCL/SPI0_nCS1";
+ bias-disable;
+ output-high;
+ };
+ gpio32ol_pins: gpio32ol-pins {
+ pins = "GPIO32/SMB14_SCL/SPI0_nCS1";
+ bias-disable;
+ output-low;
+ };
+ gpio37_pins: gpio37-pins {
+ pins = "GPIO37/SMB3C_SDA/SMB23_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio37o_pins: gpio37o-pins {
+ pins = "GPIO37/SMB3C_SDA/SMB23_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio37ol_pins: gpio37ol-pins {
+ pins = "GPIO37/SMB3C_SDA/SMB23_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio38_pins: gpio38-pins {
+ pins = "GPIO38/SMB3C_SCL/SMB23_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio38o_pins: gpio38o-pins {
+ pins = "GPIO38/SMB3C_SCL/SMB23_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio38ol_pins: gpio38ol-pins {
+ pins = "GPIO38/SMB3C_SCL/SMB23_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio39_pins: gpio39-pins {
+ pins = "GPIO39/SMB3B_SDA/SMB22_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio39o_pins: gpio39o-pins {
+ pins = "GPIO39/SMB3B_SDA/SMB22_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio39ol_pins: gpio39ol-pins {
+ pins = "GPIO39/SMB3B_SDA/SMB22_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio40_pins: gpio40-pins {
+ pins = "GPIO40/SMB3B_SCL/SMB22_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio40o_pins: gpio40o-pins {
+ pins = "GPIO40/SMB3B_SCL/SMB22_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio40ol_pins: gpio40ol-pins {
+ pins = "GPIO40/SMB3B_SCL/SMB22_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio41_pins: gpio41-pins {
+ pins = "GPIO41/BU0_RXD/CP1U_RXD";
+ input-enable;
+ };
+ gpio42_pins: gpio42-pins {
+ pins = "GPIO42/BU0_TXD/CP1U_TXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio43_pins: gpio43-pins {
+ pins = "GPIO43/SI1_RXD/BU1_RXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio44_pins: gpio44-pins {
+ pins = "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI";
+ bias-disable;
+ input-enable;
+ };
+ gpio45_pins: gpio45-pins {
+ pins = "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO";
+ bias-disable;
+ input-enable;
+ };
+ gpio46_pins: gpio46-pins {
+ pins = "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK";
+ bias-disable;
+ input-enable;
+ };
+ gpio47_pins: gpio47-pins {
+ pins = "GPIO47/SI1n_RI1";
+ bias-disable;
+ input-enable;
+ };
+ gpio48_pins: gpio48-pins {
+ pins = "GPIO48/SI2_TXD/BU0_TXD/STRAP5";
+ bias-disable;
+ input-enable;
+ };
+ gpio49_pins: gpio49-pins {
+ pins = "GPIO49/SI2_RXD/BU0_RXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio50_pins: gpio50-pins {
+ pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio50ol_pins: gpio50ol-pins {
+ pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD";
+ bias-disable;
+ output-low;
+ };
+ gpio51_pins: gpio51-pins {
+ pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio51o_pins: gpio51o-pins {
+ pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD";
+ bias-disable;
+ output-high;
+ };
+ gpio52_pins: gpio52-pins {
+ pins = "GPIO52/SI2_nDCD/BU5_RXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio52ol_pins: gpio52ol-pins {
+ pins = "GPIO52/SI2_nDCD/BU5_RXD";
+ bias-disable;
+ output-low;
+ };
+ gpio53_pins: gpio53-pins {
+ pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio53o_pins: gpio53o-pins {
+ pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD";
+ bias-disable;
+ output-high;
+ };
+ gpio54_pins: gpio54-pins {
+ pins = "GPIO54/SI2_nDSR/BU4_TXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio54ol_pins: gpio54ol-pins {
+ pins = "GPIO54/SI2_nDSR/BU4_TXD";
+ bias-disable;
+ output-low;
+ };
+ gpio55_pins: gpio55-pins {
+ pins = "GPIO55/SI2_RI2/BU4_RXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio55ol_pins: gpio55ol-pins {
+ pins = "GPIO55/SI2_RI2/BU4_RXD";
+ bias-disable;
+ output-low;
+ };
+ gpio56_pins: gpio56-pins {
+ pins = "GPIO56/R1_RXERR/R1_OEN";
+ bias-disable;
+ input-enable;
+ };
+ gpio57_pins: gpio57-pins {
+ pins = "GPIO57/R1_MDC/TP_GPIO4";
+ bias-disable;
+ input-enable;
+ };
+ gpio57ol_pins: gpio57ol-pins {
+ pins = "GPIO57/R1_MDC/TP_GPIO4";
+ bias-disable;
+ output-low;
+ };
+ gpio58_pins: gpio58-pins {
+ pins = "GPIO58/R1_MDIO/TP_GPIO5";
+ bias-disable;
+ input-enable;
+ };
+ gpio58ol_pins: gpio58ol-pins {
+ pins = "GPIO58/R1_MDIO/TP_GPIO5";
+ bias-disable;
+ output-low;
+ };
+ gpio59_pins: gpio59-pins {
+ pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio59o_pins: gpio59o-pins {
+ pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio59ol_pins: gpio59ol-pins {
+ pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio60_pins: gpio60-pins {
+ pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio60o_pins: gpio60o-pins {
+ pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio60ol_pins: gpio60ol-pins {
+ pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio61_pins: gpio61-pins {
+ pins = "GPIO61/SI1_nDTR_BOUT";
+ bias-disable;
+ input-enable;
+ };
+ gpio61o_pins: gpio61o-pins {
+ pins = "GPIO61/SI1_nDTR_BOUT";
+ bias-disable;
+ output-high;
+ };
+ gpio62_pins: gpio62-pins {
+ pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO";
+ bias-disable;
+ input-enable;
+ };
+ gpio62o_pins: gpio62o-pins {
+ pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO";
+ bias-disable;
+ output-high;
+ };
+ gpio63_pins: gpio63-pins {
+ pins = "GPIO63/BU1_TXD1/SI1_TXD";
+ bias-disable;
+ input-enable;
+ };
+ gpio63o_pins: gpio63o-pins {
+ pins = "GPIO63/BU1_TXD1/SI1_TXD";
+ bias-disable;
+ output-high;
+ };
+ gpio64_pins: gpio64-pins {
+ pins = "GPIO64/FANIN0";
+ bias-disable;
+ input-enable;
+ };
+ gpio64o_pins: gpio64o-pins {
+ pins = "GPIO64/FANIN0";
+ bias-disable;
+ output-high;
+ };
+ gpio65_pins: gpio65-pins {
+ pins = "GPIO65/FANIN1";
+ bias-disable;
+ input-enable;
+ };
+ gpio66_pins: gpio66-pins {
+ pins = "GPIO66/FANIN2";
+ bias-disable;
+ input-enable;
+ };
+ gpio67_pins: gpio67-pins {
+ pins = "GPIO67/FANIN3";
+ bias-disable;
+ input-enable;
+ };
+ gpio68_pins: gpio68-pins {
+ pins = "GPIO68/FANIN4";
+ bias-disable;
+ input-enable;
+ };
+ gpio68o_pins: gpio68o-pins {
+ pins = "GPIO68/FANIN4";
+ bias-disable;
+ output-high;
+ };
+ gpio69_pins: gpio69-pins {
+ pins = "GPIO69/FANIN5";
+ bias-disable;
+ input-enable;
+ };
+ gpio69o_pins: gpio69o-pins {
+ pins = "GPIO69/FANIN5";
+ bias-disable;
+ output-high;
+ };
+ gpio69ol_pins: gpio69ol-pins {
+ pins = "GPIO69/FANIN5";
+ bias-disable;
+ output-low;
+ };
+ gpio70_pins: gpio70-pins {
+ pins = "GPIO70/FANIN6";
+ bias-disable;
+ input-enable;
+ };
+ gpio70o_pins: gpio70o-pins {
+ pins = "GPIO70/FANIN6";
+ bias-disable;
+ output-high;
+ };
+ gpio71_pins: gpio71-pins {
+ pins = "GPIO71/FANIN7";
+ bias-disable;
+ input-enable;
+ };
+ gpio72_pins: gpio72-pins {
+ pins = "GPIO72/FANIN8";
+ bias-disable;
+ input-enable;
+ };
+ gpio72ol_pins: gpio72ol-pins {
+ pins = "GPIO72/FANIN8";
+ bias-disable;
+ output-low;
+ };
+ gpio73_pins: gpio73-pins {
+ pins = "GPIO73/FANIN9";
+ bias-disable;
+ input-enable;
+ };
+ gpio73ol_pins: gpio73ol-pins {
+ pins = "GPIO73/FANIN9";
+ bias-disable;
+ output-low;
+ };
+ gpio74_pins: gpio74-pins {
+ pins = "GPIO74/FANIN10";
+ bias-disable;
+ input-enable;
+ };
+ gpio74ol_pins: gpio74ol-pins {
+ pins = "GPIO74/FANIN10";
+ bias-disable;
+ output-low;
+ };
+ gpio75_pins: gpio75-pins {
+ pins = "GPIO75/FANIN11";
+ bias-disable;
+ input-enable;
+ };
+ gpio75ol_pins: gpio75ol-pins {
+ pins = "GPIO75/FANIN11";
+ bias-disable;
+ output-low;
+ };
+ gpio76_pins: gpio76-pins {
+ pins = "GPIO76/FANIN12";
+ bias-disable;
+ input-enable;
+ };
+ gpio76ol_pins: gpio76ol-pins {
+ pins = "GPIO76/FANIN12";
+ bias-disable;
+ output-low;
+ };
+ gpio77_pins: gpio77-pins {
+ pins = "GPIO77/FANIN13";
+ bias-disable;
+ input-enable;
+ };
+ gpio77ol_pins: gpio77ol-pins {
+ pins = "GPIO77/FANIN13";
+ bias-disable;
+ output-low;
+ };
+ gpio78_pins: gpio78-pins {
+ pins = "GPIO78/FANIN14";
+ bias-disable;
+ input-enable;
+ };
+ gpio78ol_pins: gpio78ol-pins {
+ pins = "GPIO78/FANIN14";
+ bias-disable;
+ output-low;
+ };
+ gpio79_pins: gpio79-pins {
+ pins = "GPIO79/FANIN15";
+ bias-disable;
+ input-enable;
+ };
+ gpio79ol_pins: gpio79ol-pins {
+ pins = "GPIO79/FANIN15";
+ bias-disable;
+ output-low;
+ };
+ gpio80_pins: gpio80-pins {
+ pins = "GPIO80/PWM0";
+ bias-disable;
+ input-enable;
+ };
+ gpio81_pins: gpio81-pins {
+ pins = "GPIO81/PWM1";
+ bias-disable;
+ input-enable;
+ };
+ gpio82_pins: gpio82-pins {
+ pins = "GPIO82/PWM2";
+ bias-disable;
+ input-enable;
+ };
+ gpio83_pins: gpio83-pins {
+ pins = "GPIO83/PWM3";
+ bias-disable;
+ input-enable;
+ };
+ gpio84_pins: gpio84-pins {
+ pins = "GPIO84/R2_TXD0";
+ bias-disable;
+ input-enable;
+ };
+ gpio84o_pins: gpio84ol-pins {
+ pins = "GPIO84/R2_TXD0";
+ bias-disable;
+ output-high;
+ };
+ gpio85_pins: gpio85-pins {
+ pins = "GPIO85/R2_TXD1";
+ bias-disable;
+ input-enable;
+ };
+ gpio85o_pins: gpio85o-pins {
+ pins = "GPIO85/R2_TXD1";
+ bias-disable;
+ output-high;
+ };
+ gpio86_pins: gpio86-pins {
+ pins = "GPIO86/R2_TXEN";
+ bias-disable;
+ input-enable;
+ };
+ gpio86o_pins: gpio86o-pins {
+ pins = "GPIO86/R2_TXEN";
+ bias-disable;
+ output-high;
+ };
+ gpio87_pins: gpio87-pins {
+ pins = "GPIO87/R2_RXD0";
+ bias-disable;
+ input-enable;
+ };
+ gpio87o_pins: gpio87o-pins {
+ pins = "GPIO87/R2_RXD0";
+ bias-disable;
+ output-high;
+ };
+ gpio88_pins: gpio88-pins {
+ pins = "GPIO88/R2_RXD1";
+ bias-disable;
+ input-enable;
+ };
+ gpio88ol_pins: gpio88ol-pins {
+ pins = "GPIO88/R2_RXD1";
+ bias-disable;
+ output-low;
+ };
+ gpio89_pins: gpio89-pins {
+ pins = "GPIO89/R2_CRSDV";
+ bias-disable;
+ input-enable;
+ };
+ gpio89ol_pins: gpio89ol-pins {
+ pins = "GPIO89/R2_CRSDV";
+ bias-disable;
+ output-low;
+ };
+ gpio90_pins: gpio90-pins {
+ pins = "GPIO90/R2_RXERR/R2_OEN";
+ bias-disable;
+ input-enable;
+ };
+ gpio90o_pins: gpio90o0-pins {
+ pins = "GPIO90/R2_RXERR/R2_OEN";
+ bias-disable;
+ output-high;
+ };
+ gpio90ol_pins: gpio90ol-pins {
+ pins = "GPIO90/R2_RXERR/R2_OEN";
+ bias-disable;
+ output-low;
+ };
+ gpio91_pins: gpio91-pins {
+ pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0";
+ bias-disable;
+ input-enable;
+ };
+ gpio91o_pins: gpio91o-pins {
+ pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0";
+ bias-disable;
+ output-high;
+ };
+ gpio91ol_pins: gpio91ol-pins {
+ pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0";
+ bias-disable;
+ output-low;
+ };
+ gpio92_pins: gpio92-pins {
+ pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+ bias-disable;
+ input-enable;
+ };
+ gpio92o_pins: gpio92o-pins {
+ pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+ bias-disable;
+ output-high;
+ };
+ gpio92ol_pins: gpio92ol-pins {
+ pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+ bias-disable;
+ output-low;
+ };
+ gpio93_pins: gpio93-pins {
+ pins = "GPIO93/GA20/SMB5D_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio93o_pins: gpio93o-pins {
+ pins = "GPIO93/GA20/SMB5D_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio93ol_pins: gpio93ol-pins {
+ pins = "GPIO93/GA20/SMB5D_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio94_pins: gpio94-pins {
+ pins = "GPIO94/nKBRST/SMB5D_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio94o_pins: gpio94o-pins {
+ pins = "GPIO94/nKBRST/SMB5D_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio95_pins: gpio95-pins {
+ pins = "GPIO95/nESPIRST/LPC_nLRESET";
+ bias-disable;
+ input-enable;
+ };
+ gpio96_pins: gpio96-pins {
+ pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7";
+ bias-disable;
+ input-enable;
+ };
+ gpio96ol_pins: gpio96ol-pins {
+ pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7";
+ bias-disable;
+ output-low;
+ };
+ gpio97_pins: gpio97-pins {
+ pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6";
+ bias-disable;
+ input-enable;
+ };
+ gpio97ol_pins: gpio97ol-pins {
+ pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6";
+ bias-disable;
+ output-low;
+ };
+ gpio98_pins: gpio98-pins {
+ pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5";
+ bias-disable;
+ input-enable;
+ };
+ gpio98o_pins: gpio98o-pins {
+ pins = "GPIO98/RG1TXD2";
+ bias-disable;
+ output-high;
+ };
+ gpio98ol_pins: gpio98ol-pins {
+ pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5";
+ bias-disable;
+ output-low;
+ };
+ gpio99_pins: gpio99-pins {
+ pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4";
+ bias-disable;
+ input-enable;
+ };
+ gpio99o_pins: gpio99o-pins {
+ pins = "GPIO99/RG1TXD3";
+ bias-disable;
+ output-high;
+ };
+ gpio99ol_pins: gpio99ol-pins {
+ pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4";
+ bias-disable;
+ output-low;
+ };
+ gpio100_pins: gpio100-pins {
+ pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3";
+ bias-disable;
+ input-enable;
+ };
+ gpio100ol_pins: gpio100ol-pins {
+ pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3";
+ bias-disable;
+ output-low;
+ };
+ gpio101_pins: gpio101-pins {
+ pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2";
+ bias-disable;
+ input-enable;
+ };
+ gpio101ol_pins: gpio101ol-pins {
+ pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2";
+ bias-disable;
+ output-low;
+ };
+ gpio102_pins: gpio102-pins {
+ pins = "GPIO102/HSYNC";
+ bias-disable;
+ input-enable;
+ };
+ gpio102ol_pins: gpio102ol-pins {
+ pins = "GPIO102/HSYNC";
+ bias-disable;
+ output-low;
+ };
+ gpio103_pins: gpio103-pins {
+ pins = "GPIO103/VSYNC";
+ bias-disable;
+ input-enable;
+ };
+ gpio103ol_pins: gpio103ol-pins {
+ pins = "GPIO103/VSYNC";
+ bias-disable;
+ output-low;
+ };
+ gpio104_pins: gpio104-pins {
+ pins = "GPIO104/DDC_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio104ol_pins: gpio104ol-pins {
+ pins = "GPIO104/DDC_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio105_pins: gpio105-pins {
+ pins = "GPIO105/DDC_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio105ol_pins: gpio105ol-pins {
+ pins = "GPIO105/DDC_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio106_pins: gpio106-pins {
+ pins = "GPIO106/I3C5_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio106ol_pins: gpio106ol-pins {
+ pins = "GPIO106/I3C5_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio107_pins: gpio107-pins {
+ pins = "GPIO107/I3C5_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio107ol_pins: gpio107ol-pins {
+ pins = "GPIO107/I3C5_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio108_pins: gpio108-pins {
+ pins = "GPIO108/SG1_MDC";
+ bias-disable;
+ input-enable;
+ };
+ gpio108ol_pins: gpio108ol-pins {
+ pins = "GPIO108/SG1_MDC";
+ bias-disable;
+ output-low;
+ };
+ gpio109_pins: gpio109-pins {
+ pins = "GPIO109/SG1_MDIO";
+ bias-disable;
+ input-enable;
+ };
+ gpio109ol_pins: gpio109ol-pins {
+ pins = "GPIO109/SG1_MDIO";
+ bias-disable;
+ output-low;
+ };
+ gpio110_pins: gpio110-pins {
+ pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0";
+ bias-disable;
+ input-enable;
+ };
+ gpio110ol_pins: gpio110ol-pins {
+ pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0";
+ bias-disable;
+ output-low;
+ };
+ gpio111_pins: gpio111-pins {
+ pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1";
+ bias-disable;
+ input-enable;
+ };
+ gpio111ol_pins: gpio111ol-pins {
+ pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1";
+ bias-disable;
+ output-low;
+ };
+ gpio112_pins: gpio112-pins {
+ pins = "GPIO112/RG2_TXD2/DDRV2";
+ bias-disable;
+ input-enable;
+ };
+ gpio112ol_pins: gpio112ol-pins {
+ pins = "GPIO112/RG2_TXD2/DDRV2";
+ bias-disable;
+ output-low;
+ };
+ gpio113_pins: gpio113-pins {
+ pins = "GPIO113/RG2_TXD3/DDRV3";
+ bias-disable;
+ input-enable;
+ };
+ gpio113ol_pins: gpio113ol-pins {
+ pins = "GPIO113/RG2_TXD3/DDRV3";
+ bias-disable;
+ output-low;
+ };
+ gpio118_pins: gpio118-pins {
+ pins = "GPIO118/SMB2_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio119_pins: gpio119-pins {
+ pins = "GPIO119/SMB2_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio120_pins: gpio120-pins {
+ pins = "GPIO120/SMB2C_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio120ol_pins: gpio120ol-pins {
+ pins = "GPIO120/SMB2C_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio121_pins: gpio121-pins {
+ pins = "GPIO121/SMB2C_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio122_pins: gpio122-pins {
+ pins = "GPIO122/SMB2B_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio123_pins: gpio123-pins {
+ pins = "GPIO123/SMB2B_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio123_pins: gpio123-pins {
+ pins = "GPIO123/SMB2B_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio124_pins: gpio124-pins {
+ pins = "GPIO124/SMB1C_SDA/CP1_GPIO3";
+ bias-disable;
+ input-enable;
+ };
+ gpio125_pins: gpio125-pins {
+ pins = "GPIO125/SMB1C_SCL/CP1_GPIO2";
+ bias-disable;
+ input-enable;
+ };
+ gpio126_pins: gpio126-pins {
+ pins = "GPIO126/SMB1B_SDA/CP1_GPIO1";
+ bias-disable;
+ input-enable;
+ };
+ gpio127_pins: gpio127-pins {
+ pins = "GPIO127/SMB1B_SCL/CP1_GPIO0";
+ bias-disable;
+ input-enable;
+ };
+ gpio128o_pins: gpio128o-pins {
+ pins = "GPIO128/SMB824_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio130_pins: gpio130-pins {
+ pins = "GPIO130/SMB925_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio131_pins: gpio131-pins {
+ pins = "GPIO131/SMB925_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio132_pins: gpio132-pins {
+ pins = "GPIO132/SMB1026_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio133_pins: gpio133-pins {
+ pins = "GPIO133/SMB1026_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio134_pins: gpio134-pins {
+ pins = "GPIO134/SMB11_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio135_pins: gpio135-pins {
+ pins = "GPIO135/SMB11_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio136_pins: gpio136-pins {
+ pins = "GPIO136/JM1_TCK";
+ bias-disable;
+ input-enable;
+ };
+ gpio136o_pins: gpio136o-pins {
+ pins = "GPIO136/JM1_TCK";
+ bias-disable;
+ output-high;
+ };
+ gpio137_pins: gpio137-pins {
+ pins = "GPIO137/JM1_TDO";
+ bias-disable;
+ input-enable;
+ };
+ gpio137o_pins: gpio137o-pins {
+ pins = "GPIO137/JM1_TDO";
+ bias-disable;
+ output-high;
+ };
+ gpio138_pins: gpio138-pins {
+ pins = "GPIO138/JM1_TMS";
+ bias-disable;
+ input-enable;
+ };
+ gpio138o_pins: gpio138o-pins {
+ pins = "GPIO138/JM1_TMS";
+ bias-disable;
+ output-high;
+ };
+ gpio139_pins: gpio139-pins {
+ pins = "GPIO139/JM1_TDI";
+ bias-disable;
+ input-enable;
+ };
+ gpio139o_pins: gpio139o-pins {
+ pins = "GPIO139/JM1_TDI";
+ bias-disable;
+ output-high;
+ };
+ gpio140_pins: gpio140-pins {
+ pins = "GPIO140/JM1_nTRST";
+ bias-disable;
+ input-enable;
+ };
+ gpio140o_pins: gpio140o-pins {
+ pins = "GPIO140/JM1_nTRST";
+ bias-disable;
+ output-high;
+ };
+ gpio141_pins: gpio141-pins {
+ pins = "GPIO141/SMB7B_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio141o_pins: gpio141o-pins {
+ pins = "GPIO141/SMB7B_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio141ol_pins: gpio141ol-pins {
+ pins = "GPIO141/SMB7B_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio142_pins: gpio142-pins {
+ pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio142o_pins: gpio142o-pins {
+ pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio143_pins: gpio143-pins {
+ pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio143o_pins: gpio143o-pins {
+ pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio143ol_pins: gpio143ol-pins {
+ pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio144_pins: gpio144-pins {
+ pins = "GPIO144/PWM4";
+ bias-disable;
+ input-enable;
+ };
+ gpio145_pins: gpio145-pins {
+ pins = "GPIO145/PWM5";
+ bias-disable;
+ input-enable;
+ };
+ gpio146_pins: gpio146-pins {
+ pins = "GPIO146/PWM6";
+ bias-disable;
+ input-enable;
+ };
+ gpio147_pins: gpio147-pins {
+ pins = "GPIO147/PWM7";
+ bias-disable;
+ input-enable;
+ };
+ gpio148_pins: gpio148-pins {
+ pins = "GPIO148/MMC_DT4";
+ bias-disable;
+ input-enable;
+ };
+ gpio148o_pins: gpio148o-pins {
+ pins = "GPIO148/MMC_DT4";
+ bias-disable;
+ output-high;
+ };
+ gpio148ol_pins: gpio148ol_pins {
+ pins = "GPIO148/MMC_DT4";
+ bias-disable;
+ output-low;
+ };
+ gpio149_pins: gpio149-pins {
+ pins = "GPIO149/MMC_DT5";
+ bias-disable;
+ input-enable;
+ };
+ gpio149o_pins: gpio149o-pins {
+ pins = "GPIO149/MMC_DT5";
+ bias-disable;
+ output-high;
+ };
+ gpio149ol_pins: gpio149ol-pins {
+ pins = "GPIO149/MMC_DT5";
+ bias-disable;
+ output-low;
+ };
+ gpio150_pins: gpio150-pins {
+ pins = "GPIO150/MMC_DT6";
+ bias-disable;
+ input-enable;
+ };
+ gpio150o_pins: gpio150o-pins {
+ pins = "GPIO150/MMC_DT6";
+ bias-disable;
+ output-high;
+ };
+ gpio150ol_pins: gpio150ol-pins {
+ pins = "GPIO150/MMC_DT6";
+ bias-disable;
+ output-low;
+ };
+ gpio151_pins: gpio151-pins {
+ pins = "GPIO151/MMC_DT7";
+ bias-disable;
+ input-enable;
+ };
+ gpio151o_pins: gpio151o-pins {
+ pins = "GPIO151/MMC_DT7";
+ bias-disable;
+ output-high;
+ };
+ gpio151ol_pins: gpio151ol-pins {
+ pins = "GPIO151/MMC_DT7";
+ bias-disable;
+ output-low;
+ };
+ gpio152_pins: gpio152-pins {
+ pins = "GPIO152/MMC_CLK";
+ bias-disable;
+ input-enable;
+ };
+ gpio152o_pins: gpio152o-pins {
+ pins = "GPIO152/MMC_CLK";
+ bias-disable;
+ output-high;
+ };
+ gpio152ol_pins: gpio152ol-pins {
+ pins = "GPIO152/MMC_CLK";
+ bias-disable;
+ output-low;
+ };
+ gpio153_pins: gpio153-pins {
+ pins = "GPIO153/MMC_WP";
+ bias-disable;
+ input-enable;
+ };
+ gpio153ol_pins: gpio153ol-pins {
+ pins = "GPIO153/MMC_WP";
+ bias-disable;
+ output-low;
+ };
+ gpio154_pins: gpio154-pins {
+ pins = "GPIO154/MMC_CMD";
+ bias-disable;
+ input-enable;
+ };
+ gpio154ol_pins: gpio154ol-pins {
+ pins = "GPIO154/MMC_CMD";
+ bias-disable;
+ output-low;
+ };
+ gpio155_pins: gpio155-pins {
+ pins = "GPIO155/MMC_nCD/MMC_nRSTLK";
+ bias-disable;
+ input-enable;
+ };
+ gpio155ol_pins: gpio155ol-pins {
+ pins = "GPIO155/MMC_nCD/MMC_nRSTLK";
+ bias-disable;
+ output-low;
+ };
+ gpio156_pins: gpio156-pins {
+ pins = "GPIO156/MMC_DT0";
+ bias-disable;
+ input-enable;
+ };
+ gpio156ol_pins: gpio156ol-pins {
+ pins = "GPIO156/MMC_DT0";
+ bias-disable;
+ output-low;
+ };
+ gpio157_pins: gpio157-pins {
+ pins = "GPIO157/MMC_DT1";
+ bias-disable;
+ input-enable;
+ };
+ gpio157o_pins: gpio157o-pins {
+ pins = "GPIO157/MMC_DT1";
+ bias-disable;
+ output-high;
+ };
+ gpio157ol_pins: gpio157ol-pins {
+ pins = "GPIO157/MMC_DT1";
+ bias-disable;
+ output-low;
+ };
+ gpio158_pins: gpio158-pins {
+ pins = "GPIO158/MMC_DT2";
+ bias-disable;
+ input-enable;
+ };
+ gpio158o_pins: gpio158o-pins {
+ pins = "GPIO158/MMC_DT2";
+ bias-disable;
+ output-high;
+ };
+ gpio158ol_pins: gpio158ol-pins {
+ pins = "GPIO158/MMC_DT2";
+ bias-disable;
+ output-low;
+ };
+ gpio159_pins: gpio159-pins {
+ pins = "GPIO159/MMC_DT3";
+ bias-disable;
+ input-enable;
+ };
+ gpio159o_pins: gpio159o-pins {
+ pins = "GPIO159/MMC_DT3";
+ bias-disable;
+ output-high;
+ };
+ gpio159ol_pins: gpio159ol-pins {
+ pins = "GPIO159/MMC_DT3";
+ bias-disable;
+ output-low;
+ };
+ gpio160_pins: gpio160-pins {
+ pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK";
+ bias-disable;
+ input-enable;
+ };
+ gpio160o_pins: gpio160o-pins {
+ pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK";
+ bias-disable;
+ output-high;
+ };
+ gpio160ol_pins: gpio160ol-pins {
+ pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK";
+ bias-disable;
+ output-low;
+ };
+ gpio161_pins: gpio161-pins {
+ pins = "GPIO161/ESPI_nCS/LPC_nLFRAME";
+ bias-disable;
+ input-enable;
+ };
+ gpio162_pins: gpio162-pins {
+ pins = "GPIO162/LPC_nCLKRUN";
+ bias-disable;
+ input-enable;
+ };
+ gpio162o_pins: gpio162o-pins {
+ pins = "GPIO162/LPC_nCLKRUN";
+ bias-disable;
+ output-high;
+ };
+ gpio163_pins: gpio163-pins {
+ pins = "GPIO163/ESPI_CK/LPC_LCLK";
+ bias-disable;
+ input-enable;
+ };
+ gpio164_pins: gpio164-pins {
+ pins = "GPIO164/ESPI_IO0/LPC_LAD0";
+ bias-disable;
+ input-enable;
+ };
+ gpio165_pins: gpio165-pins {
+ pins = "GPIO165/ESPI_IO1/LPC_LAD1";
+ bias-disable;
+ input-enable;
+ };
+ gpio166_pins: gpio166-pins {
+ pins = "GPIO166/ESPI_IO2/LPC_LAD2";
+ bias-disable;
+ input-enable;
+ };
+ gpio167_pins: gpio167-pins {
+ pins = "GPIO167/ESPI_IO3/LPC_LAD3";
+ bias-disable;
+ input-enable;
+ };
+ gpio168_pins: gpio168-pins {
+ pins = "GPIO168/ESPI_nALERT/SERIRQ";
+ bias-disable;
+ input-enable;
+ drive-open-drain;
+ };
+ gpio168ol_pins: gpio168ol-pins {
+ pins = "GPIO168/ESPI_nALERT/SERIRQ";
+ bias-disable;
+ output-low;
+ };
+ gpio169_pins: gpio169-pins {
+ pins = "GPIO169/nSCIPME/SMB21_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio169o_pins: gpio169o-pins {
+ pins = "GPIO169/nSCIPME/SMB21_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio169ol_pins: gpio169ol-pins {
+ pins = "GPIO169/nSCIPME/SMB21_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio170_pins: gpio170-pins {
+ pins = "GPIO170/nSMI/SMB21_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio170ol_pins: gpio170ol-pins {
+ pins = "GPIO170/nSMI/SMB21_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio173o_pins: gpio173o-pins {
+ pins = "GPIO173/SMB7_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio173ol_pins: gpio173ol-pins {
+ pins = "GPIO173/SMB7_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio174_pins: gpio174-pins {
+ pins = "GPIO174/SMB7_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio175_pins: gpio175-pins {
+ pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK";
+ bias-disable;
+ input-enable;
+ };
+ gpio175o_pins: gpio175o-pins {
+ pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK";
+ bias-disable;
+ output-high;
+ };
+ gpio175ol_pins: gpio175ol-pins {
+ pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK";
+ bias-disable;
+ output-low;
+ };
+ gpio176_pins: gpio176-pins {
+ pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9";
+ bias-disable;
+ input-enable;
+ };
+ gpio176o_pins: gpio176o-pins {
+ pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9";
+ bias-disable;
+ output-high;
+ };
+ gpio176ol_pins: gpio176ol-pins {
+ pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9";
+ bias-disable;
+ output-low;
+ };
+ gpio177_pins: gpio177-pins {
+ pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10";
+ bias-disable;
+ input-enable;
+ };
+ gpio177o_pins: gpio177o-pins {
+ pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10";
+ bias-disable;
+ output-high;
+ };
+ gpio177ol_pins: gpio177ol-pins {
+ pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10";
+ bias-disable;
+ output-low;
+ };
+ gpio187_pins: gpio187-pins {
+ pins = "GPIO187/SPI3_nCS1_SMB14_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio187o_pins: gpio187o-pins {
+ pins = "GPIO187/SPI3_nCS1_SMB14_SDA";
+ bias-disable;
+ output-high;
+ };
+ gpio187ol_pins: gpio187ol-pins {
+ pins = "GPIO187/SPI3_nCS1_SMB14_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio188_pins: gpio188-pins {
+ pins = "GPIO188/SPI3_D2/SPI3_nCS2";
+ bias-disable;
+ input-enable;
+ };
+ gpio188o_pins: gpio188o-pins {
+ pins = "GPIO188/SPI3_D2/SPI3_nCS2";
+ bias-disable;
+ output-high;
+ };
+ gpio189o_pins: gpio189o-pins {
+ pins = "GPIO189/SPI3_D3/SPI3_nCS3";
+ bias-disable;
+ output-high;
+ };
+ gpio190_pins: gpio190-pins {
+ pins = "GPIO190/nPRD_SMI";
+ bias-disable;
+ input-enable;
+ };
+ gpio190o_pins: gpio190o-pins {
+ pins = "GPIO190/nPRD_SMI";
+ bias-disable;
+ output-high;
+ };
+ gpio190ol_pins: gpio190ol-pins {
+ pins = "GPIO190/nPRD_SMI";
+ bias-disable;
+ output-low;
+ };
+ gpio191o_pins: gpio191o-pins {
+ pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10";
+ bias-disable;
+ output-high;
+ };
+ gpio191ol_pins: gpio191ol-pins {
+ pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10";
+ bias-disable;
+ output-low;
+ };
+ gpio192_pins: gpio192-pins {
+ pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio192o_pins: gpio192o-pins {
+ pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio192ol_pins: gpio192ol-pins {
+ pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio194_pins: gpio194-pins {
+ pins = "GPIO194/SMB0B_SCL/FM0_CK";
+ bias-disable;
+ input-enable;
+ };
+ gpio194o_pins: gpio194o-pins {
+ pins = "GPIO194/SMB0B_SCL/FM0_CK";
+ bias-disable;
+ output-high;
+ };
+ gpio195_pins: gpio195-pins {
+ pins = "GPIO195/SMB0B_SDA/FM0_D0";
+ bias-disable;
+ input-enable;
+ };
+ gpio196_pins: gpio196-pins {
+ pins = "GPIO196/SMB0C_SCL/FM0_D1";
+ bias-disable;
+ input-enable;
+ };
+ gpio196o_pins: gpio196o-pins {
+ pins = "GPIO196/SMB0C_SCL/FM0_D1";
+ bias-disable;
+ output-high;
+ };
+ gpio197_pins: gpio197-pins {
+ pins = "GPIO197/SMB0DEN/FM0_D3";
+ bias-disable;
+ input-enable;
+ };
+ gpio197o_pins: gpio197o-pins {
+ pins = "GPIO197/SMB0DEN/FM0_D3";
+ bias-disable;
+ output-high;
+ };
+ gpio197ol_pins: gpio197ol-pins {
+ pins = "GPIO197/SMB0DEN/FM0_D3";
+ bias-disable;
+ output-low;
+ };
+ gpio198o_pins: gpio198o-pins {
+ pins = "GPIO198/SMB0D_SDA/FM0_D2";
+ bias-disable;
+ output-high;
+ };
+ gpio198ol_pins: gpio198ol-pins {
+ pins = "GPIO198/SMB0D_SDA/FM0_D2";
+ bias-disable;
+ output-low;
+ };
+ gpio199_pins: gpio199-pins {
+ pins = "GPIO199/SMB0D_SCL/FM0_CSO";
+ bias-disable;
+ input-enable;
+ };
+ gpio200_pins: gpio200-pins {
+ pins = "GPIO200/R2_CK";
+ input-enable;
+ bias-disable;
+ };
+ gpio200ol_pins: gpio200ol-pins {
+ pins = "GPIO200/R2_CK";
+ bias-disable;
+ output-low;
+ };
+ gpio201ol_pins: gpio201ol-pins {
+ pins = "GPIO201/R1_CK";
+ bias-disable;
+ output-low;
+ };
+ gpio202_pins: gpio202-pins {
+ pins = "GPIO202/SMB0C_SDA/FM0_CSI";
+ bias-disable;
+ input-enable;
+ };
+ gpio203_pins: gpio203-pins {
+ pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI";
+ bias-disable;
+ input-enable;
+ };
+ gpio203o_pins: gpio203o-pins {
+ pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI";
+ bias-disable;
+ output-high;
+ };
+ gpio203ol_pins: gpio203ol-pins {
+ pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI";
+ bias-disable;
+ output-low;
+ };
+ gpio208_pins: gpio208-pins {
+ pins = "GPIO208/RG2_TXC/DVCK";
+ bias-disable;
+ input-enable;
+ };
+ gpio208o_pins: gpio208o-pins {
+ pins = "GPIO208/RG2_TXC/DVCK";
+ bias-disable;
+ output-high;
+ };
+ gpio208ol_pins: gpio208ol-pins {
+ pins = "GPIO208/RG2_TXC/DVCK";
+ bias-disable;
+ output-low;
+ };
+ gpio209_pins: gpio209-pins {
+ pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN";
+ bias-disable;
+ input-enable;
+ };
+ gpio209ol_pins: gpio209ol-pins {
+ pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN";
+ bias-disable;
+ output-low;
+ };
+ gpio210_pins: gpio210-pins {
+ pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0";
+ bias-disable;
+ input-enable;
+ };
+ gpio210o_pins: gpio210o-pins {
+ pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0";
+ bias-disable;
+ output-high;
+ };
+ gpio210ol_pins: gpio210ol-pins {
+ pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0";
+ bias-disable;
+ output-low;
+ };
+ gpio211_pins: gpio211-pins {
+ pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1";
+ bias-disable;
+ input-enable;
+ };
+ gpio211o_pins: gpio211o-pins {
+ pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1";
+ bias-disable;
+ output-high;
+ };
+ gpio211ol_pins: gpio211ol-pins {
+ pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1";
+ bias-disable;
+ output-low;
+ };
+ gpio212_pins: gpio212-pins {
+ pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2";
+ bias-disable;
+ input-enable;
+ };
+ gpio212o_pins: gpio212o-pins {
+ pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2";
+ bias-disable;
+ output-high;
+ };
+ gpio212ol_pins: gpio212ol-pins {
+ pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2";
+ bias-disable;
+ output-low;
+ };
+ gpio213_pins: gpio213-pins {
+ pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN";
+ bias-disable;
+ input-enable;
+ };
+ gpio213o_pins: gpio213o-pins {
+ pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN";
+ bias-disable;
+ output-high;
+ };
+ gpio213ol_pins: gpio213ol-pins {
+ pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN";
+ bias-disable;
+ output-low;
+ };
+ gpio214_pins: gpio214-pins {
+ pins = "GPIO214/RG2_RXC/DDRV9/R3_CK";
+ bias-disable;
+ input-enable;
+ };
+ gpio214ol_pins: gpio214ol-pins {
+ pins = "GPIO214/RG2_RXC/DDRV9/R3_CK";
+ bias-disable;
+ output-low;
+ };
+ gpio215_pins: gpio215-pins {
+ pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV";
+ bias-disable;
+ input-enable;
+ };
+ gpio215ol_pins: gpio215ol-pins {
+ pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV";
+ bias-disable;
+ output-low;
+ };
+ gpio216_pins: gpio216-pins {
+ pins = "GPIO216/RG2_MDC/DDRV11";
+ bias-disable;
+ input-enable;
+ };
+ gpio216ol_pins: gpio216ol-pins {
+ pins = "GPIO216/RG2_MDC/DDRV11";
+ bias-disable;
+ output-low;
+ };
+ gpio217_pins: gpio217-pins {
+ pins = "GPIO217/RG2_MDIO/DVHSYNC";
+ bias-disable;
+ input-enable;
+ };
+ gpio217ol_pins: gpio217ol-pins {
+ pins = "GPIO217/RG2_MDIO/DVHSYNC";
+ bias-disable;
+ output-low;
+ };
+ gpio218_pins: gpio218-pins {
+ pins = "GPIO218/nWDO1/SMB16_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio218ol_pins: gpio218ol-pins {
+ pins = "GPIO218/nWDO1/SMB16_SCL";
+ bias-disable;
+ output-low;
+ };
+ gpio219_pins: gpio219-pins {
+ pins = "GPIO219/nWDO2/SMB16_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio219ol_pins: gpio219ol-pins {
+ pins = "GPIO219/nWDO2/SMB16_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio220ol_pins: gpio220ol-pins {
+ pins = "GPIO220/SMB12_SCL/PWM8";
+ bias-disable;
+ output-low;
+ };
+ gpio221o_pins: gpio221o-pins {
+ pins = "GPIO221/SMB12_SDA/PWM9";
+ bias-disable;
+ output-high;
+ };
+ gpio222_pins: gpio222-pins {
+ pins = "GPIO222/SMB13_SCL";
+ bias-disable;
+ input-enable;
+ };
+ gpio222o_pins: gpio222o-pins {
+ pins = "GPIO222/SMB13_SCL";
+ bias-disable;
+ output-high;
+ };
+ gpio223_pins: gpio223-pins {
+ pins = "GPIO223/SMB13_SDA";
+ bias-disable;
+ input-enable;
+ };
+ gpio223ol_pins: gpio223ol-pins {
+ pins = "GPIO223/SMB13_SDA";
+ bias-disable;
+ output-low;
+ };
+ gpio224_pins: gpio224-pins {
+ pins = "GPIO224/SPIX_CK/FM2_CK";
+ bias-disable;
+ input-enable;
+ };
+ gpio224o_pins: gpio224o-pins {
+ pins = "GPIO224/SPIX_CK/FM2_CK";
+ bias-disable;
+ output-high;
+ };
+ gpio224ol_pins: gpio224ol-pins {
+ pins = "GPIO224/SPIX_CK/FM2_CK";
+ bias-disable;
+ output-low;
+ };
+ gpio225_pins: gpio225-pins {
+ pins = "GPO225/SPIX_D0/FM2_D0/STRAP1";
+ bias-disable;
+ input-enable;
+ };
+ gpio225o_pins: gpio225o-pins {
+ pins = "GPO225/SPIX_D0/FM2_D0/STRAP1";
+ bias-disable;
+ output-high;
+ };
+ gpio226_pins: gpio226-pins {
+ pins = "GPO226/SPIX_D1/FM2_D1/STRAP2";
+ bias-disable;
+ input-enable;
+ };
+ gpio226o_pins: gpio226o-pins {
+ pins = "GPO226/SPIX_D1/FM2_D1/STRAP2";
+ bias-disable;
+ output-high;
+ };
+ gpio227_pins: gpio227-pins {
+ pins = "GPIO227/SPIX_nCS0/FM2_CSI";
+ bias-disable;
+ input-enable;
+ };
+ gpio227o_pins: gpio227o-pins {
+ pins = "GPIO227/SPIX_nCS0/FM2_CSI";
+ bias-disable;
+ output-high;
+ };
+ gpio227ol_pins: gpio227ol-pins {
+ pins = "GPIO227/SPIX_nCS0/FM2_CSI";
+ bias-disable;
+ output-low;
+ };
+ gpio228_pins: gpio228-pins {
+ pins = "GPIO228/SPIX_nCS1/FM2_CSO";
+ bias-disable;
+ input-enable;
+ };
+ gpio228ol_pins: gpio228ol-pins {
+ pins = "GPIO228/SPIX_nCS1/FM2_CSO";
+ bias-disable;
+ output-low;
+ };
+ gpio229_pins: gpio229-pins {
+ pins = "GPO229/SPIX_D2/FM2_D2/STRAP3";
+ bias-disable;
+ input-enable;
+ };
+ gpio229o_pins: gpio229o-pins {
+ pins = "GPO229/SPIX_D2/FM2_D2/STRAP3";
+ bias-disable;
+ output-high;
+ };
+ gpio230_pins: gpio230-pins {
+ pins = "GPO230/SPIX_D3/FM2_D3/STRAP6";
+ bias-disable;
+ input-enable;
+ };
+ gpio230o_pins: gpio230o-pins {
+ pins = "GPO230/SPIX_D3/FM2_D3/STRAP6";
+ bias-disable;
+ output-high;
+ };
+ gpio230ol_pins: gpio230ol-pins {
+ pins = "GPO230/SPIX_D3/FM2_D3/STRAP6";
+ bias-disable;
+ output-low;
+ };
+ gpio231_pins: gpio231-pins {
+ pins = "GPIO231/EP_nCLKREQ";
+ bias-disable;
+ input-enable;
+ };
+ gpio231o_pins: gpio231o-pins {
+ pins = "GPIO231/EP_nCLKREQ";
+ bias-disable;
+ output-high;
+ };
+ };
+};
diff --git a/arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi b/arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi
new file mode 100644
index 0000000000..5ce6e2f2a7
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm8xx-pinctrl.dtsi
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Nuvoton Technology Crop.
+
+/ {
+ pinctrl: pinctrl@f0800000 {
+ iox1_pins: iox1-pins {
+ groups = "iox1";
+ function = "iox1";
+ };
+ iox2_pins: iox2-pins {
+ groups = "iox2";
+ function = "iox2";
+ };
+ smb1d_pins: smb1d-pins {
+ groups = "smb1d";
+ function = "smb1d";
+ };
+ smb2d_pins: smb2d-pins {
+ groups = "smb2d";
+ function = "smb2d";
+ };
+ lkgpo1_pins: lkgpo1-pins {
+ groups = "lkgpo1";
+ function = "lkgpo1";
+ };
+ lkgpo2_pins: lkgpo2-pins {
+ groups = "lkgpo2";
+ function = "lkgpo2";
+ };
+ tp_gpio0_pins: tp_gpio0-pins {
+ groups = "tp_gpio0";
+ function = "tp_gpio0";
+ };
+ tp_gpio1_pins: tp_gpio1-pins {
+ groups = "tp_gpio1";
+ function = "tp_gpio1";
+ };
+ tp_gpio2_pins: tp_gpio2-pins {
+ groups = "tp_gpio2";
+ function = "tp_gpio2";
+ };
+ ioxh_pins: ioxh-pins {
+ groups = "ioxh";
+ function = "ioxh";
+ };
+ gspi_pins: gspi-pins {
+ groups = "gspi";
+ function = "gspi";
+ };
+ smb5b_pins: smb5b-pins {
+ groups = "smb5b";
+ function = "smb5b";
+ };
+ smb5c_pins: smb5c-pins {
+ groups = "smb5c";
+ function = "smb5c";
+ };
+ lkgpo0_pins: lkgpo0-pins {
+ groups = "lkgpo0";
+ function = "lkgpo0";
+ };
+ pspi_pins: pspi-pins {
+ groups = "pspi";
+ function = "pspi";
+ };
+ smb4den_pins: smb4den-pins {
+ groups = "smb4den";
+ function = "smb4den";
+ };
+ smb4b_pins: smb4b-pins {
+ groups = "smb4b";
+ function = "smb4b";
+ };
+ smb4c_pins: smb4c-pins {
+ groups = "smb4c";
+ function = "smb4c";
+ };
+ smb15_pins: smb15-pins {
+ groups = "smb15";
+ function = "smb15";
+ };
+ smb16_pins: smb16-pins {
+ groups = "smb16";
+ function = "smb16";
+ };
+ smb17_pins: smb17-pins {
+ groups = "smb17";
+ function = "smb17";
+ };
+ smb18_pins: smb18-pins {
+ groups = "smb18";
+ function = "smb18";
+ };
+ smb19_pins: smb19-pins {
+ groups = "smb19";
+ function = "smb19";
+ };
+ smb20_pins: smb20-pins {
+ groups = "smb20";
+ function = "smb20";
+ };
+ smb21_pins: smb21-pins {
+ groups = "smb21";
+ function = "smb21";
+ };
+ smb22_pins: smb22-pins {
+ groups = "smb22";
+ function = "smb22";
+ };
+ smb23_pins: smb23-pins {
+ groups = "smb23";
+ function = "smb23";
+ };
+ smb4d_pins: smb4d-pins {
+ groups = "smb4d";
+ function = "smb4d";
+ };
+ smb14_pins: smb14-pins {
+ groups = "smb14";
+ function = "smb14";
+ };
+ smb14b_pins: smb14b-pins {
+ groups = "smb14b";
+ function = "smb14b";
+ };
+ smb5_pins: smb5-pins {
+ groups = "smb5";
+ function = "smb5";
+ };
+ smb4_pins: smb4-pins {
+ groups = "smb4";
+ function = "smb4";
+ };
+ smb3_pins: smb3-pins {
+ groups = "smb3";
+ function = "smb3";
+ };
+ spi0cs1_pins: spi0cs1-pins {
+ groups = "spi0cs1";
+ function = "spi0cs1";
+ };
+ spi0cs2_pins: spi0cs2-pins {
+ groups = "spi0cs2";
+ function = "spi0cs2";
+ };
+ spi0cs3_pins: spi0cs3-pins {
+ groups = "spi0cs3";
+ function = "spi0cs3";
+ };
+ gpi35_pins: gpi35-pins {
+ groups = "gpi35";
+ function = "gpi35";
+ };
+ gpi36_pins: gpi36-pins {
+ groups = "gpi36";
+ function = "gpi36";
+ };
+ smb3c_pins: smb3c-pins {
+ groups = "smb3c";
+ function = "smb3c";
+ };
+ smb3b_pins: smb3b-pins {
+ groups = "smb3b";
+ function = "smb3b";
+ };
+ bmcuart0a_pins: bmcuart0a-pins {
+ groups = "bmcuart0a";
+ function = "bmcuart0a";
+ };
+ uart1_pins: uart1-pins {
+ groups = "uart1";
+ function = "uart1";
+ };
+ jtag2_pins: jtag2-pins {
+ groups = "jtag2";
+ function = "jtag2";
+ };
+ j2j3_pins: j2j3-pins {
+ groups = "j2j3";
+ function = "j2j3";
+ };
+ jm1_pins: jm1-pins {
+ groups = "jm1";
+ function = "jm1";
+ };
+ bmcuart1_pins: bmcuart1-pins {
+ groups = "bmcuart1";
+ function = "bmcuart1";
+ };
+ hsi2a_pins: hsi2a-pins {
+ groups = "hsi2a";
+ function = "hsi2a";
+ };
+ tp_uart_pins: tp_uart-pins {
+ groups = "tp_uart";
+ function = "tp_uart";
+ };
+ bu5_pins: bu5-pins {
+ groups = "bu5";
+ function = "bu5";
+ };
+ bu4_pins: bu4-pins {
+ groups = "bu4";
+ function = "bu4";
+ };
+ uart2_pins: uart2-pins {
+ groups = "uart2";
+ function = "uart2";
+ };
+ bmcuart0b_pins: bmcuart0b-pins {
+ groups = "bmcuart0b";
+ function = "bmcuart0b";
+ };
+ bu2_pins: bu2-pins {
+ groups = "bu2";
+ function = "bu2";
+ };
+ r1err_pins: r1err-pins {
+ groups = "r1err";
+ function = "r1err";
+ };
+ r1md_pins: r1md-pins {
+ groups = "r1md";
+ function = "r1md";
+ };
+ smb3d_pins: smb3d-pins {
+ groups = "smb3d";
+ function = "smb3d";
+ };
+ fanin0_pins: fanin0-pins {
+ groups = "fanin0";
+ function = "fanin0";
+ };
+ fanin1_pins: fanin1-pins {
+ groups = "fanin1";
+ function = "fanin1";
+ };
+ fanin2_pins: fanin2-pins {
+ groups = "fanin2";
+ function = "fanin2";
+ };
+ fanin3_pins: fanin3-pins {
+ groups = "fanin3";
+ function = "fanin3";
+ };
+ fanin4_pins: fanin4-pins {
+ groups = "fanin4";
+ function = "fanin4";
+ };
+ fanin5_pins: fanin5-pins {
+ groups = "fanin5";
+ function = "fanin5";
+ };
+ fanin6_pins: fanin6-pins {
+ groups = "fanin6";
+ function = "fanin6";
+ };
+ fanin7_pins: fanin7-pins {
+ groups = "fanin7";
+ function = "fanin7";
+ };
+ fanin8_pins: fanin8-pins {
+ groups = "fanin8";
+ function = "fanin8";
+ };
+ fanin9_pins: fanin9-pins {
+ groups = "fanin9";
+ function = "fanin9";
+ };
+ fanin10_pins: fanin10-pins {
+ groups = "fanin10";
+ function = "fanin10";
+ };
+ fanin11_pins: fanin11-pins {
+ groups = "fanin11";
+ function = "fanin11";
+ };
+ fanin12_pins: fanin12-pins {
+ groups = "fanin12";
+ function = "fanin12";
+ };
+ fanin13_pins: fanin13-pins {
+ groups = "fanin13";
+ function = "fanin13";
+ };
+ fanin14_pins: fanin14-pins {
+ groups = "fanin14";
+ function = "fanin14";
+ };
+ fanin15_pins: fanin15-pins {
+ groups = "fanin15";
+ function = "fanin15";
+ };
+ pwm0_pins: pwm0-pins {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+ pwm1_pins: pwm1-pins {
+ groups = "pwm1";
+ function = "pwm1";
+ };
+ pwm2_pins: pwm2-pins {
+ groups = "pwm2";
+ function = "pwm2";
+ };
+ pwm3_pins: pwm3-pins {
+ groups = "pwm3";
+ function = "pwm3";
+ };
+ r2_pins: r2-pins {
+ groups = "r2";
+ function = "r2";
+ };
+ r2err_pins: r2err-pins {
+ groups = "r2err";
+ function = "r2err";
+ };
+ r2oen_pins: r2oen-pins {
+ groups = "r2oen";
+ function = "r2oen";
+ };
+ r2md_pins: r2md-pins {
+ groups = "r2md";
+ function = "r2md";
+ };
+ rmii3_pins: rmii3-pins {
+ groups = "rmii3";
+ function = "rmii3";
+ };
+ r3rxer_pins: r3rxer-pins {
+ groups = "r3rxer";
+ function = "r3rxer";
+ };
+ ga20kbc_pins: ga20kbc-pins {
+ groups = "ga20kbc";
+ function = "ga20kbc";
+ };
+ smb5d_pins: smb5d-pins {
+ groups = "smb5d";
+ function = "smb5d";
+ };
+ lpc_pins: lpc-pins {
+ groups = "lpc";
+ function = "lpc";
+ };
+ espi_pins: espi-pins {
+ groups = "espi";
+ function = "espi";
+ };
+ rg1_pins: rg1-pins {
+ groups = "rg1";
+ function = "rg1";
+ };
+ sg1mdio_pins: sg1mdio-pins {
+ groups = "sg1mdio";
+ function = "sg1mdio";
+ };
+ rg2_pins: rg2-pins {
+ groups = "rg2";
+ function = "rg2";
+ };
+ ddr_pins: ddr-pins {
+ groups = "ddr";
+ function = "ddr";
+ };
+ smb0_pins: smb0-pins {
+ groups = "smb0";
+ function = "smb0";
+ };
+ smb1_pins: smb1-pins {
+ groups = "smb1";
+ function = "smb1";
+ };
+ smb2_pins: smb2-pins {
+ groups = "smb2";
+ function = "smb2";
+ };
+ smb2c_pins: smb2c-pins {
+ groups = "smb2c";
+ function = "smb2c";
+ };
+ smb2b_pins: smb2b-pins {
+ groups = "smb2b";
+ function = "smb2b";
+ };
+ smb1c_pins: smb1c-pins {
+ groups = "smb1c";
+ function = "smb1c";
+ };
+ smb1b_pins: smb1b-pins {
+ groups = "smb1b";
+ function = "smb1b";
+ };
+ smb8_pins: smb8-pins {
+ groups = "smb8";
+ function = "smb8";
+ };
+ smb9_pins: smb9-pins {
+ groups = "smb9";
+ function = "smb9";
+ };
+ smb10_pins: smb10-pins {
+ groups = "smb10";
+ function = "smb10";
+ };
+ smb11_pins: smb11-pins {
+ groups = "smb11";
+ function = "smb11";
+ };
+ sd1_pins: sd1-pins {
+ groups = "sd1";
+ function = "sd1";
+ };
+ sd1pwr_pins: sd1pwr-pins {
+ groups = "sd1pwr";
+ function = "sd1pwr";
+ };
+ pwm4_pins: pwm4-pins {
+ groups = "pwm4";
+ function = "pwm4";
+ };
+ pwm5_pins: pwm5-pins {
+ groups = "pwm5";
+ function = "pwm5";
+ };
+ pwm6_pins: pwm6-pins {
+ groups = "pwm6";
+ function = "pwm6";
+ };
+ pwm7_pins: pwm7-pins {
+ groups = "pwm7";
+ function = "pwm7";
+ };
+ mmc8_pins: mmc8-pins {
+ groups = "mmc8";
+ function = "mmc8";
+ };
+ mmc_pins: mmc-pins {
+ groups = "mmc";
+ function = "mmc";
+ };
+ mmcwp_pins: mmcwp-pins {
+ groups = "mmcwp";
+ function = "mmcwp";
+ };
+ mmccd_pins: mmccd-pins {
+ groups = "mmccd";
+ function = "mmccd";
+ };
+ mmcrst_pins: mmcrst-pins {
+ groups = "mmcrst";
+ function = "mmcrst";
+ };
+ clkout_pins: clkout-pins {
+ groups = "clkout";
+ function = "clkout";
+ };
+ serirq_pins: serirq-pins {
+ groups = "serirq";
+ function = "serirq";
+ };
+ lpcclk_pins: lpcclk-pins {
+ groups = "lpcclk";
+ function = "lpcclk";
+ };
+ scipme_pins: scipme-pins {
+ groups = "scipme";
+ function = "scipme";
+ };
+ sci_pins: sci-pins {
+ groups = "sci";
+ function = "sci";
+ };
+ smb6_pins: smb6-pins {
+ groups = "smb6";
+ function = "smb6";
+ };
+ smb7_pins: smb7-pins {
+ groups = "smb7";
+ function = "smb7";
+ };
+ faninx_pins: faninx-pins {
+ groups = "faninx";
+ function = "faninx";
+ };
+ r1_pins: r1-pins {
+ groups = "r1";
+ function = "r1";
+ };
+ spi1_pins: spi1-pins {
+ groups = "spi1";
+ function = "spi1";
+ };
+ spi1cs1_pins: spi1cs1-pins {
+ groups = "spi1cs1";
+ function = "spi1cs1";
+ };
+ spi1d23_pins: spi1d23-pins {
+ groups = "spi1d23";
+ function = "spi1d23";
+ };
+ spi1cs2_pins: spi1cs2-pins {
+ groups = "spi1cs2";
+ function = "spi1cs2";
+ };
+ spi1cs3_pins: spi1cs3-pins {
+ groups = "spi1cs3";
+ function = "spi1cs3";
+ };
+ spi3_pins: spi3-pins {
+ groups = "spi3";
+ function = "spi3";
+ };
+ spi3cs1_pins: spi3cs1-pins {
+ groups = "spi3cs1";
+ function = "spi3cs1";
+ };
+ spi3quad_pins: spi3quad-pins {
+ groups = "spi3quad";
+ function = "spi3quad";
+ };
+ spi3cs2_pins: spi3cs2-pins {
+ groups = "spi3cs2";
+ function = "spi3cs2";
+ };
+ spi3cs3_pins: spi3cs3-pins {
+ groups = "spi3cs3";
+ function = "spi3cs3";
+ };
+ nprd_smi_pins: nprd-smi-pins {
+ groups = "nprd_smi";
+ function = "nprd_smi";
+ };
+ smb0b_pins: smb0b-pins {
+ groups = "smb0b";
+ function = "smb0b";
+ };
+ smb0c_pins: smb0c-pins {
+ groups = "smb0c";
+ function = "smb0c";
+ };
+ smb0den_pins: smb0den-pins {
+ groups = "smb0den";
+ function = "smb0den";
+ };
+ smb0d_pins: smb0d-pins {
+ groups = "smb0d";
+ function = "smb0d";
+ };
+ ddc_pins: ddc-pins {
+ groups = "ddc";
+ function = "ddc";
+ };
+ rg2mdio_pins: rg2mdio-pins {
+ groups = "rg2mdio";
+ function = "rg2mdio";
+ };
+ rg2refck_pins: rg2refck-pins {
+ groups = "rg2refck";
+ function = "rg2refck";
+ };
+ wdog1_pins: wdog1-pins {
+ groups = "wdog1";
+ function = "wdog1";
+ };
+ wdog2_pins: wdog2-pins {
+ groups = "wdog2";
+ function = "wdog2";
+ };
+ smb12_pins: smb12-pins {
+ groups = "smb12";
+ function = "smb12";
+ };
+ smb13_pins: smb13-pins {
+ groups = "smb13";
+ function = "smb13";
+ };
+ spix_pins: spix-pins {
+ groups = "spix";
+ function = "spix";
+ };
+ spixcs1_pins: spixcs1-pins {
+ groups = "spixcs1";
+ function = "spixcs1";
+ };
+ clkreq_pins: clkreq-pins {
+ groups = "clkreq";
+ function = "clkreq";
+ };
+ hgpio0_pins: hgpio0-pins {
+ groups = "hgpio0";
+ function = "hgpio0";
+ };
+ hgpio1_pins: hgpio1-pins {
+ groups = "hgpio1";
+ function = "hgpio1";
+ };
+ hgpio2_pins: hgpio2-pins {
+ groups = "hgpio2";
+ function = "hgpio2";
+ };
+ hgpio3_pins: hgpio3-pins {
+ groups = "hgpio3";
+ function = "hgpio3";
+ };
+ hgpio4_pins: hgpio4-pins {
+ groups = "hgpio4";
+ function = "hgpio4";
+ };
+ hgpio5_pins: hgpio5-pins {
+ groups = "hgpio5";
+ function = "hgpio5";
+ };
+ hgpio6_pins: hgpio6-pins {
+ groups = "hgpio6";
+ function = "hgpio6";
+ };
+ hgpio7_pins: hgpio7-pins {
+ groups = "hgpio7";
+ function = "hgpio7";
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v1 9/9] ARM: configs: Add defconfig for Nuvoton NPCM845
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
` (7 preceding siblings ...)
2021-12-15 2:57 ` [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree Stanley Chu
@ 2021-12-15 2:58 ` Stanley Chu
8 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2021-12-15 2:58 UTC (permalink / raw)
To: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77
Cc: u-boot, openbmc
Add defconfig for NPCM845 EVB (Arbel).
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
---
board/nuvoton/arbel/MAINTAINERS | 7 +++
configs/arbel_evb_defconfig | 77 +++++++++++++++++++++++++++++++++
2 files changed, 84 insertions(+)
create mode 100644 board/nuvoton/arbel/MAINTAINERS
create mode 100644 configs/arbel_evb_defconfig
diff --git a/board/nuvoton/arbel/MAINTAINERS b/board/nuvoton/arbel/MAINTAINERS
new file mode 100644
index 0000000000..1086401f7d
--- /dev/null
+++ b/board/nuvoton/arbel/MAINTAINERS
@@ -0,0 +1,7 @@
+Arbel EVB
+M: Stanley Chu <yschu@nuvoton.com>
+M: Medad Cchien <ctcchien@nuvoton.com>
+S: Maintained
+F: board/nuvoton/arbel/
+F: include/configs/arbel.h
+F: configs/arbel_evb_defconfig
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
new file mode 100644
index 0000000000..6efb72391a
--- /dev/null
+++ b/configs/arbel_evb_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_NPCM=y
+CONFIG_ARCH_NPCM8XX=y
+CONFIG_TARGET_ARBEL_EVB=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_SYS_LOAD_ADDR=0x10000000
+CONFIG_SYS_PROMPT="U-Boot>"
+CONFIG_SYS_MALLOC_LEN=0x240000
+CONFIG_SYS_MEMTEST_END=0x08000000
+CONFIG_SYS_MEMTEST_START=0
+CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_ENV_ADDR=0x80100000
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_NPCM_SERIAL=y
+CONFIG_TIMER=y
+CONFIG_NPCM_TIMER=y
+CONFIG_CLK=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_NPCM8XX=y
+CONFIG_PINCONF=y
+CONFIG_DM_GPIO=y
+CONFIG_NPCM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CMD_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_NEW=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_CMD_FAT=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NPCM_FIU_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_DHCP=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+# CONFIG_EFI is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_ENV_IS_IN_FLASH is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_PSCI_RESET is not set
+# CONFIG_INPUT is not set
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
@ 2021-12-15 12:12 ` Giulio Benetti
2022-03-11 0:50 ` Stanley Chu
2021-12-15 18:32 ` Sean Anderson
2022-03-10 18:49 ` Tom Rini
2 siblings, 1 reply; 31+ messages in thread
From: Giulio Benetti @ 2021-12-15 12:12 UTC (permalink / raw)
To: Stanley Chu, lukma, jagan, andre.przywara, festevam, narmstrong,
pbrobinson, tharvey, christianshewitt, lokeshvutla, sjg, sr,
michal.simek, hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
mr.bossman075, yschu, kwliu, ctcchien, avifishman70, tmaimon77
Cc: u-boot, openbmc
Hi Stanley,
On 15/12/21 03:57, Stanley Chu wrote:
> Add basic support for the Nuvoton NPCM845 BMC.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> arch/arm/Kconfig | 9 +
> arch/arm/Makefile | 1 +
> arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
> arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
> arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
> arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
> arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
> arch/arm/mach-nuvoton/Kconfig | 24 ++
> arch/arm/mach-nuvoton/Makefile | 1 +
> arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
> arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
> arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
Here ^^^ you setup timer, but it should be a separate driver IMHO. At
least this is what I've done for imxrt.
Same goes for clock, there is no clock driver and you setup spi clock
directly inside the same file with npcm_sysintf_init() while that should
be part of the clock driver.
Also all defines regarding to clocks and peripherals should go into
their driver.
> arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
Here you've mixed up the architecture(above) and the board(below) in a
single patch.
> board/nuvoton/arbel/Kconfig | 18 ++
> board/nuvoton/arbel/Makefile | 1 +
> board/nuvoton/arbel/arbel.c | 33 +++
> include/configs/arbel.h | 54 ++++
arbel should be arbel-evk
I stop here, because there could be big changes if others agree.
Best regards
--
Giulio Benetti
Benetti Engineering sas
> 17 files changed, 924 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
> create mode 100644 arch/arm/mach-nuvoton/Kconfig
> create mode 100644 arch/arm/mach-nuvoton/Makefile
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
> create mode 100644 board/nuvoton/arbel/Kconfig
> create mode 100644 board/nuvoton/arbel/Makefile
> create mode 100644 board/nuvoton/arbel/arbel.c
> create mode 100644 include/configs/arbel.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f7f03837fe..80ec42f6be 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
> select LINUX_KERNEL_IMAGE_HEADER
> select XEN_SERIAL
> select SSCANF
> +
> +config ARCH_NPCM
> + bool "Support Nuvoton SoCs"
> + select DM
> + select OF_CONTROL
> + imply CMD_DM
> +
> endchoice
>
> config SUPPORT_PASSING_ATAGS
> @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
>
> source "arch/arm/mach-nexell/Kconfig"
>
> +source "arch/arm/mach-nuvoton/Kconfig"
> +
> source "board/armltd/total_compute/Kconfig"
>
> source "board/bosch/shc/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index ad757e982e..29a0250ab6 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
> machine-$(CONFIG_ARCH_ZYNQ) += zynq
> machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
> machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
> +machine-$(CONFIG_ARCH_NPCM) += nuvoton
>
> machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>
> diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
> new file mode 100644
> index 0000000000..088b536b7b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef _NPCM_CLOCK_H_
> +#define _NPCM_CLOCK_H_
> +
> +#define NPCM_CLK_BA 0xF0801000
> +enum {
> + APB1 = 1,
> + APB2 = 2,
> + APB3 = 3,
> + APB4 = 4,
> + APB5 = 5,
> + SPI0 = 10,
> + SPI1 = 11,
> + SPI3 = 13,
> + SPIX = 14,
> +};
> +
> +/* Clock Select Register (CLKSEL) */
> +#define CLKSEL_RCPCKSEL 27
> +#define CLKSEL_RGSEL 25
> +#define CLKSEL_GFXMSEL 21
> +#define CLKSEL_CLKOUTSEL 18
> +#define CLKSEL_PCICKSEL 16
> +#define CLKSEL_ADCCKSEL 14
> +#define CLKSEL_MCCKSEL 12
> +#define CLKSEL_SUCKSEL 10
> +#define CLKSEL_UARTCKSEL 8
> +#define CLKSEL_SDCKSEL 6
> +#define CLKSEL_PIXCKSEL 4
> +#define CLKSEL_CPUCKSEL 0
> +
> +/* Clock Divider Control Register 1 (CLKDIV1) */
> +#define CLKDIV1_ADCCKDIV 28
> +#define CLKDIV1_CLK4DIV 26
> +#define CLKDIV1_PRE_ADCCKDIV 21
> +#define CLKDIV1_UARTDIV 16
> +#define CLKDIV1_MMCCKDIV 11
> +#define CLKDIV1_SPI3CKDIV 6
> +#define CLKDIV1_PCICKDIV 2
> +
> +/* Clock Divider Control Register 2 (CLKDIV2) */
> +#define CLKDIV2_APB4CKDIV 30
> +#define CLKDIV2_APB3CKDIV 28
> +#define CLKDIV2_APB2CKDIV 26
> +#define CLKDIV2_APB1CKDIV 24
> +#define CLKDIV2_APB5CKDIV 22
> +#define CLKDIV2_CLKOUTDIV 16
> +#define CLKDIV2_GFXCKDIV 13
> +#define CLKDIV2_SUCKDIV 8
> +#define CLKDIV2_SU48CKDIV 4
> +
> +/* PLL Control Register 2 (PLLCON2) */
> +#define PLLCON_LOKI 31
> +#define PLLCON_LOKS 30
> +#define PLLCON_FBDV 16
> +#define PLLCON_OTDV2 13
> +#define PLLCON_PWDEN 12
> +#define PLLCON_OTDV1 8
> +#define PLLCON_INDV 0
> +
> +/* CPUCKSEL (CPU/AMBA/MC Clock Source Select Bit) */
> +#define CLKSEL_CPUCKSEL_PLL0 0x00 /* 0 0: PLL0 clock*/
> +#define CLKSEL_CPUCKSEL_PLL1 0x01 /* 0 1: PLL1 clock */
> +#define CLKSEL_CPUCKSEL_CLKREF 0x02 /* 1 0: CLKREF input (25 MHZ, default) */
> +#define CLKSEL_CPUCKSEL_SYSBPCK 0x03 /* 1 1: Bypass clock from pin SYSBPCK */
> +
> +/* UARTCKSEL (Core and Host UART Clock Source Select Bit). */
> +#define CLKSEL_UARTCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> +#define CLKSEL_UARTCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> +#define CLKSEL_UARTCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> +#define CLKSEL_UARTCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> +
> +/* SDCKSEL (SDHC Clock Source Select Bit). */
> +#define CLKSEL_SDCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> +#define CLKSEL_SDCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> +#define CLKSEL_SDCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> +#define CLKSEL_SDCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> +
> +/* IP Software Reset Register 1 (IPSRST1), offset 0x20 */
> +#define IPSRST1_USBDEV1 5
> +#define IPSRST1_USBDEV2 8
> +#define IPSRST1_USBDEV3 25
> +#define IPSRST1_USBDEV4 22
> +#define IPSRST1_USBDEV5 23
> +#define IPSRST1_USBDEV6 24
> +#define IPSRST1_GMAC4 21
> +#define IPSRST1_GMAC3 6
> +
> +/* IP Software Reset Register 2 (IPSRST2), offset 0x24 */
> +#define IPSRST2_GMAC1 28
> +#define IPSRST2_GMAC2 25
> +#define IPSRST2_USBHOST1 26
> +#define IPSRST2_SDHC 9
> +#define IPSRST2_MMC 8
> +
> +/* IP Software Reset Register 3 (IPSRST3), offset 0x34 */
> +#define IPSRST3_USBPHY1 24
> +#define IPSRST3_USBPHY2 25
> +#define IPSRST3_USBHUB 8
> +#define IPSRST3_USBDEV9 7
> +#define IPSRST3_USBDEV8 6
> +#define IPSRST3_USBDEV7 5
> +#define IPSRST3_USBDEV0 4
> +
> +/* IP Software Reset Register 4 (IPSRST4), offset 0x74 */
> +#define IPSRST4_USBHOST2 31
> +#define IPSRST4_USBPHY3 25
> +
> +#define EXT_CLOCK_FREQUENCY_KHZ 25 * 1000 * 1UL
> +#define EXT_CLOCK_FREQUENCY_MHZ 25
> +
> +struct clk_ctl {
> + unsigned int clken1;
> + unsigned int clksel;
> + unsigned int clkdiv1;
> + unsigned int pllcon0;
> + unsigned int pllcon1;
> + unsigned int swrstr;
> + unsigned char res1[0x8];
> + unsigned int ipsrst1;
> + unsigned int ipsrst2;
> + unsigned int clken2;
> + unsigned int clkdiv2;
> + unsigned int clken3;
> + unsigned int ipsrst3;
> + unsigned int wd0rcr;
> + unsigned int wd1rcr;
> + unsigned int wd2rcr;
> + unsigned int swrstc1;
> + unsigned int swrstc2;
> + unsigned int swrstc3;
> + unsigned int tiprstc;
> + unsigned int pllcon2;
> + unsigned int clkdiv3;
> + unsigned int corstc;
> + unsigned int pllcong;
> + unsigned int ahbckfi;
> + unsigned int seccnt;
> + unsigned int cntr25m;
> + unsigned int clken4;
> + unsigned int ipsrst4;
> + unsigned int busto;
> + unsigned int clkdiv4;
> + unsigned int wd0rcrb;
> + unsigned int wd1rcrb;
> + unsigned int wd2rcrb;
> + unsigned int swrstc1b;
> + unsigned int swrstc2b;
> + unsigned int swrstc3b;
> + unsigned int tiprstcb;
> + unsigned int corstcb;
> + unsigned int ipsrstdis1;
> + unsigned int ipsrstdis2;
> + unsigned int ipsrstdis3;
> + unsigned int ipsrstdis4;
> + unsigned char res2[0x10];
> + unsigned int thrtl_cnt;
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/espi.h b/arch/arm/include/asm/arch-npcm8xx/espi.h
> new file mode 100644
> index 0000000000..d4de012b02
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/espi.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +#ifndef _NPCM_ESPI_H_
> +#define _NPCM_ESPI_H_
> +
> +#define NPCM_ESPI_BA 0xF009F000
> +/* Register offsets */
> +#define ESPICFG 0x04
> +#define ESPIHINDP 0x80
> +
> +/* Channel Supported */
> +#define ESPICFG_CHNSUPP_MASK 0x0F
> +#define ESPICFG_CHNSUPP_SHFT 24
> +
> +/* I/O Mode Supported */
> +#define ESPICFG_IOMODE_SHIFT 8
> +#define ESPI_IO_MODE_SINGLE_DUAL_QUAD 3
> +
> +/* Maximum Frequency Supported */
> +#define ESPICFG_MAXFREQ_SHIFT 10
> +#define ESPI_MAX_33_MHZ 2
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> new file mode 100644
> index 0000000000..14a4b2dbfb
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> @@ -0,0 +1,313 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef _NPCM_GCR_H_
> +#define _NPCM_GCR_H_
> +
> +#define NPCM_GCR_BA 0xF0800000
> +/* On-Chip ARBEL NPCM8XX VERSIONS */
> +
> +#define ARBEL_Z1 0x00A35850
> +#define ARBEL_A1 0x04a35850
> +#define ARBEL_NPCM845 0x00000000
> +#define ARBEL_NPCM830 0x00300395
> +#define ARBEL_NPCM810 0x00000220
> +
> +/* Function Lock Register 2 (FLOCKR2) */
> +#define FLOCKR2_MMCRST 12
> +#define FLOCKR2_MMCRSTLK 13
> +#define FLOCKR2_G35DA2P 18
> +
> +/* Power-On Setting Register (PWRON) */
> +#define PWRON_BSPA 4 /* STRAP5 */
> +#define PWRON_SECEN 7 /* STRAP8 */
> +
> +/* Multiple Function Pin Select Register 1 (MFSEL1) */
> +#define MFSEL1_SIRQSE 31
> +#define MFSEL1_IOX1SEL 30
> +#define MFSEL1_HSI2BSEL 29
> +#define MFSEL1_HSI1BSEL 28
> +#define MFSEL1_DVH1SEL 27
> +#define MFSEL1_LPCSEL 26
> +#define MFSEL1_PECIB 25
> +#define MFSEL1_GSPISEL 24
> +#define MFSEL1_SMISEL 22
> +#define MFSEL1_CLKOSEL 21
> +#define MFSEL1_DVOSEL 18
> +#define MFSEL1_KBCICSEL 17
> +#define MFSEL1_R2MDSEL 16
> +#define MFSEL1_R2ERRSEL 15
> +#define MFSEL1_RMII2SEL 14
> +#define MFSEL1_R1MDSEL 13
> +#define MFSEL1_R1ERRSEL 12
> +#define MFSEL1_HSI2ASEL 11
> +#define MFSEL1_HSI1ASEL 10
> +#define MFSEL1_BSPSEL 9
> +#define MFSEL1_SMB2SEL 8
> +#define MFSEL1_SMB1SEL 7
> +#define MFSEL1_SMB0SEL 6
> +#define MFSEL1_HSI2CSEL 5
> +#define MFSEL1_HSI1CSEL 4
> +#define MFSEL1_S0CS1SEL 3
> +#define MFSEL1_SMB5SEL 2
> +#define MFSEL1_SMB4SEL 1
> +#define MFSEL1_SMB3SEL 0
> +
> +/* Multiple Function Pin Select Register 3 (MFSEL3) */
> +#define MFSEL3_DVODEDLY 27
> +#define MFSEL3_DDRDVOSEL 26
> +#define MFSEL3_MMCCDSEL 25
> +#define MFSEL3_BU1SEL 24
> +#define MFSEL3_I3C5SEL 22
> +#define MFSEL3_WDO2SEL 20
> +#define MFSEL3_WDO1SEL 19
> +#define MFSEL3_IOXHSEL 18
> +#define MFSEL3_PCIEPUSE 17
> +#define MFSEL3_CLKRUNSEL 16
> +#define MFSEL3_IOX2SEL 14
> +#define MFSEL3_PSPISEL 13
> +#define MFSEL3_MMC8SEL 11
> +#define MFSEL3_MMCSEL 10
> +#define MFSEL3_RMII1SEL 9
> +#define MFSEL3_SMB15SEL 8
> +#define MFSEL3_SMB14SEL 7
> +#define MFSEL3_SMB13SEL 6
> +#define MFSEL3_SMB12SEL 5
> +#define MFSEL3_SPI1SEL 4
> +#define MFSEL3_FIN1916SELB 3
> +#define MFSEL3_SMB7SEL 2
> +#define MFSEL3_SMB6SEL 1
> +#define MFSEL3_SCISEL 0
> +
> +/* Multiple Function Pin Select Register 4 (MFSEL4) */
> +#define MFSEL4_SMB11DDC 29
> +#define MFSEL4_SXCS1SEL 28
> +#define MFSEL4_SPXSEL 27
> +#define MFSEL4_RG2SEL 24
> +#define MFSEL4_RG2MSEL 23
> +#define MFSEL4_BU2SELB 22
> +#define MFSEL4_SG1MSEL 21
> +#define MFSEL4_SP3QSEL 20
> +#define MFSEL4_S3CS3SEL 19
> +#define MFSEL4_S3CS2SEL 18
> +#define MFSEL4_S3CS1SEL 17
> +#define MFSEL4_SP3SEL 16
> +#define MFSEL4_SP0QSEL 15
> +#define MFSEL4_SMB11SEL 14
> +#define MFSEL4_SMB10SEL 13
> +#define MFSEL4_SMB9SEL 12
> +#define MFSEL4_SMB8SEL 11
> +#define MFSEL4_DBGTRSEL 10
> +#define MFSEL4_CKRQSEL 9
> +#define MFSEL4_ESPISEL 8
> +#define MFSEL4_MMCRSEL 6
> +#define MFSEL4_SD1PSEL 5
> +#define MFSEL4_ROSEL 4
> +#define MFSEL4_ESPIPMESEL 2
> +#define MFSEL4_BSPASEL 1
> +#define MFSEL4_JTAG2SEL 0
> +
> +/* Multiple Function Pin Select Register 5 (MFSEL5) */
> +#define MFSEL5_R3OENSEL 14
> +#define MFSEL5_RMII3SEL 11
> +#define MFSEL5_R2OENSEL 10
> +#define MFSEL5_R1OENSEL 9
> +#define MFSEL5_NSPI1CS3SEL 5
> +#define MFSEL5_NSPI1CS2SEL 4
> +#define MFSEL5_SPI1D23SEL 3
> +#define MFSEL5_NSPI1CS1SEL 0
> +
> +/* Multiple Function Pin Select Register 6 (MFSEL6) */
> +#define MFSEL6_GPIO1836SEL 19
> +#define MFSEL6_FM1SEL 17
> +
> +/* Multiple Function Pin Select Register 7 (MFSEL7) */
> +#define MFSEL7_SMB15SELB 27
> +#define MFSEL7_GPIO1889SEL 25
> +
> +/* USB PHY1 Control Register (USB1PHYCTL) */
> +#define USB1PHYCTL_RS 28
> +/* USB PHY2 Control Register (USB2PHYCTL) */
> +#define USB2PHYCTL_RS 28
> +/* USB PHY2 Control Register (USB3PHYCTL) */
> +#define USB3PHYCTL_RS 28
> +
> +/* Integration Control Register (INTCR) */
> +#define INTCR_DUDKSMOD 30
> +#define INTCR_DDC3I 29
> +#define INTCR_KVMSI 28
> +#define INTCR_DEHS 27
> +#define INTCR_GGPCT2_0 24
> +#define INTCR_SGC2 23
> +#define INTCR_DSNS_TRIG 21
> +#define INTCR_DAC_SNS 20
> +#define INTCR_SGC1 19
> +#define INTCR_LDDRB 18
> +#define INTCR_GIRST 17
> +#define INTCR_DUDKSEN 16
> +#define INTCR_DACOFF 15
> +#define INTCR_DACSEL 14
> +#define INTCR_GFXINT 12
> +#define INTCR_DACOSOVR 10
> +#define INTCR_GFXIFDIS 8
> +#define INTCR_H2RQDIS 9
> +#define INTCR_H2DISPOFF 8
> +#define INTCR_GFXINT2 7
> +#define INTCR_VGAIOEN 6
> +#define INTCR_PSPIFEN 4
> +#define INTCR_HIFEN 3
> +#define INTCR_SMBFEN 2
> +#define INTCR_MFTFEN 1
> +#define INTCR_KCSRST_MODE 0
> +
> +/* Integration Control Register (INTCR2) */
> +#define INTCR2_WDC 21
> +
> +/* Integration Control Register (INTCR3) */
> +#define INTCR3_USBLPBK2 31 /* USB loop-backed HOST 1/2 */
> +#define INTCR3_USBLPBK 24 /* USB loop-backed mode on/off */
> +#define INTCR3_USBPHY3SW 14 /* 2 bits */
> +#define INTCR3_USBPHY2SW 12 /* 2 bits */
> +#define INTCR3_USBPPS 6
> +#define INTCR3_UHUB_RWUD 5
> +
> +/* Integration Control Register (INTCR4) */
> +#define INTCR4_GMMAP1 24
> +#define INTCR4_GMMAP0 16
> +#define INTCR4_R3EN 14
> +#define INTCR4_R2EN 13
> +#define INTCR4_R1EN 12
> +#define INTCR4_RGMIIREF 6
> +
> +/* I2C Segment Pin Select Register (I2CSEGSEL) */
> +#define I2CSEGSEL_S0DECFG 3
> +#define I2CSEGSEL_S4DECFG 17
> +
> +/* I2C Segment Control Register (I2CSEGCTL) */
> +#define I2CSEGCTL_S0DEN 20
> +#define I2CSEGCTL_S0DWE 21
> +#define I2CSEGCTL_S4DEN 24
> +#define I2CSEGCTL_S4DWE 25
> +#define I2CSEGCTL_INIT_VAL 0x9333F000
> +
> +struct npcm_gcr {
> + unsigned int pdid;
> + unsigned int pwron;
> + unsigned int swstrps;
> + unsigned int rsvd1[2];
> + unsigned int miscpe;
> + unsigned int spldcnt;
> + unsigned int rsvd2[1];
> + unsigned int flockr2;
> + unsigned int flockr3;
> + unsigned int rsvd3[3];
> + unsigned int a35_mode;
> + unsigned int spswc;
> + unsigned int intcr;
> + unsigned int intsr;
> + unsigned int obscr1;
> + unsigned int obsdr1;
> + unsigned int rsvd4[1];
> + unsigned int hifcr;
> + unsigned int rsvd5[3];
> + unsigned int intcr2;
> + unsigned int rsvd6[1];
> + unsigned int srcnt;
> + unsigned int ressr;
> + unsigned int rlockr1;
> + unsigned int flockr1;
> + unsigned int dscnt;
> + unsigned int mdlr;
> + unsigned int scrpad_c;
> + /* scrpad_b: holds the active dram size (value set by bootblock) */
> + unsigned int scrpad_b;
> + unsigned int rsvd7[4];
> + unsigned int daclvlr;
> + unsigned int intcr3;
> + unsigned int pcirctl;
> + unsigned int rsvd8[2];
> + unsigned int vsintr;
> + unsigned int rsvd9[1];
> + unsigned int sd2sur1;
> + unsigned int sd2sur2;
> + unsigned int sd2irv3;
> + unsigned int intcr4;
> + unsigned int obscr2;
> + unsigned int obsdr2;
> + unsigned int rsvd10[5];
> + unsigned int i2csegsel;
> + unsigned int i2csegctl;
> + unsigned int vsrcr;
> + unsigned int mlockr;
> + unsigned int rsvd11[8];
> + unsigned int etsr;
> + unsigned int dft1r;
> + unsigned int dft2r;
> + unsigned int dft3r;
> + unsigned int edffsr;
> + unsigned int rsvd12[1];
> + unsigned int intcrpce3;
> + unsigned int intcrpce2;
> + unsigned int intcrpce0;
> + unsigned int intcrpce1;
> + unsigned int dactest;
> + unsigned int scrpad;
> + unsigned int usb1phyctl;
> + unsigned int usb2phyctl;
> + unsigned int usb3phyctl;
> + unsigned int intsr2;
> + unsigned int intcrpce2b;
> + unsigned int intcrpce0b;
> + unsigned int intcrpce1b;
> + unsigned int intcrpce3b;
> + unsigned int rsvd13[4];
> + unsigned int intcrpce2c;
> + unsigned int intcrpce0c;
> + unsigned int intcrpce1c;
> + unsigned int intcrpce3c;
> + unsigned int rsvd14[40];
> + unsigned int sd2irv4;
> + unsigned int sd2irv5;
> + unsigned int sd2irv6;
> + unsigned int sd2irv7;
> + unsigned int sd2irv8;
> + unsigned int sd2irv9;
> + unsigned int sd2irv10;
> + unsigned int sd2irv11;
> + unsigned int rsvd15[8];
> + unsigned int mfsel1;
> + unsigned int mfsel2;
> + unsigned int mfsel3;
> + unsigned int mfsel4;
> + unsigned int mfsel5;
> + unsigned int mfsel6;
> + unsigned int mfsel7;
> + unsigned int rsvd16[1];
> + unsigned int mfsel_lk1;
> + unsigned int mfsel_lk2;
> + unsigned int mfsel_lk3;
> + unsigned int mfsel_lk4;
> + unsigned int mfsel_lk5;
> + unsigned int mfsel_lk6;
> + unsigned int mfsel_lk7;
> + unsigned int rsvd17[1];
> + unsigned int mfsel_set1;
> + unsigned int mfsel_set2;
> + unsigned int mfsel_set3;
> + unsigned int mfsel_set4;
> + unsigned int mfsel_set5;
> + unsigned int mfsel_set6;
> + unsigned int mfsel_set7;
> + unsigned int rsvd18[1];
> + unsigned int mfsel_clr1;
> + unsigned int mfsel_clr2;
> + unsigned int mfsel_clr3;
> + unsigned int mfsel_clr4;
> + unsigned int mfsel_clr5;
> + unsigned int mfsel_clr6;
> + unsigned int mfsel_clr7;
> + };
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/gpio.h b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> new file mode 100644
> index 0000000000..234a1d3de9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef _NPCM_GPIO_H_
> +#define _NPCM_GPIO_H_
> +
> +#define NPCM_GPIO_BA 0xF0010000
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
> new file mode 100644
> index 0000000000..ffaff50fe2
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +#ifndef _NPCM_RST_H_
> +#define _NPCM_RST_H_
> +
> +enum reset_type {
> + PORST_TYPE = 0x01,
> + CORST_TYPE = 0x02,
> + WD0RST_TYPE = 0x03,
> + SWR1ST_TYPE = 0x04,
> + SWR2ST_TYPE = 0x05,
> + SWR3ST_TYPE = 0x06,
> + SWR4ST_TYPE = 0x07,
> + WD1RST_TYPE = 0x08,
> + WD2RST_TYPE = 0x09,
> + UNKNOWN_TYPE = 0x10,
> +};
> +
> +#define PORST 0x80000000
> +#define CORST 0x40000000
> +#define WD0RST 0x20000000
> +#define SWR1ST 0x10000000
> +#define SWR2ST 0x08000000
> +#define SWR3ST 0x04000000
> +#define SWR4ST 0x02000000
> +#define WD1RST 0x01000000
> +#define WD2RST 0x00800000
> +#define RESSR_MASK 0xff800000
> +
> +enum reset_type npcm8xx_reset_reason(void);
> +
> +#endif
> diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig
> new file mode 100644
> index 0000000000..e014dd4b79
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/Kconfig
> @@ -0,0 +1,24 @@
> +if ARCH_NPCM
> +
> +config SYS_ARCH
> + default "arm"
> +
> +config SYS_TEXT_BASE
> + default 0x8000
> +
> +choice
> + prompt "Nuvoton SoC select"
> + default ARCH_NPCM8XX
> +
> +config ARCH_NPCM8XX
> + bool "Support Nuvoton NPCM8xx SoC"
> + select ARM64
> + help
> + General support for NPCM8xx BMC (Arbel).
> + Nuvoton NPCM8xx BMC is based on the Cortex A35.
> +
> +endchoice
> +
> +source "arch/arm/mach-nuvoton/npcm8xx/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile
> new file mode 100644
> index 0000000000..e75689a1a0
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/Kconfig b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> new file mode 100644
> index 0000000000..478a046ad5
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> @@ -0,0 +1,18 @@
> +if ARCH_NPCM8XX
> +
> +config SYS_CPU
> + default "armv8"
> +
> +config SYS_SOC
> + default "npcm8xx"
> +
> +config TARGET_ARBEL_EVB
> + bool "Arbel-EVB"
> + help
> + ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
> + supports general functions of Basebase Management Controller
> + (BMC).
> +
> +source "board/nuvoton/arbel/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/Makefile b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> new file mode 100644
> index 0000000000..c62a4aa20a
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> @@ -0,0 +1 @@
> +obj-y += reset.o cpu.o
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/cpu.c b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> new file mode 100644
> index 0000000000..8a7315d535
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> @@ -0,0 +1,170 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <cpu_func.h>
> +#include <asm/io.h>
> +#include <asm/arch/gcr.h>
> +#include <asm/arch/espi.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/system.h>
> +#include <asm/global_data.h>
> +
> +/* System Counter */
> +struct sctr_regs {
> + u32 cntcr;
> + u32 cntsr;
> + u32 cntcv1;
> + u32 cntcv2;
> + u32 resv1[4];
> + u32 cntfid0;
> + u32 cntfid1;
> + u32 cntfid2;
> + u32 resv2[1001];
> + u32 counterid[1];
> +};
> +
> +#define SC_CNTCR_ENABLE BIT(0)
> +#define SC_CNTCR_HDBG BIT(1)
> +#define SC_CNTCR_FREQ0 BIT(8)
> +#define SC_CNTCR_FREQ1 BIT(9)
> +
> +#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int print_cpuinfo(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> + unsigned int id = 0;
> + unsigned long mpidr_val = 0;
> + unsigned int mdlr = 0;
> +
> + asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
> +
> + mdlr = readl(&gcr->mdlr);
> +
> + printf("CPU-%d: ", (unsigned int)(mpidr_val & 0x3));
> +
> + switch (mdlr) {
> + case ARBEL_NPCM845:
> + printf("NPCM845 ");
> + break;
> + case ARBEL_NPCM830:
> + printf("NPCM830 ");
> + break;
> + case ARBEL_NPCM810:
> + printf("NPCM810 ");
> + break;
> + default:
> + printf("NPCM8XX ");
> + break;
> + }
> +
> + id = readl(&gcr->pdid);
> + switch (id) {
> + case ARBEL_Z1:
> + printf("Z1 @ ");
> + break;
> + case ARBEL_A1:
> + printf("A1 @ ");
> + break;
> + default:
> + printf("Unknown\n");
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void npcm_sysintf_init(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> + u32 espi_ch_supp, val;
> +
> + espi_ch_supp = ofnode_conf_read_int("espi-channel-support", 0);
> +
> + if (espi_ch_supp) {
> + /* Use eSPI function and initialize ESPICFG */
> + u32 hindp = 0x00011110 | espi_ch_supp;
> +
> + writel((readl(&gcr->mfsel4) | (1 << MFSEL4_ESPISEL)), &gcr->mfsel4);
> + writel(hindp, NPCM_ESPI_BA + ESPIHINDP);
> + val = readl(NPCM_ESPI_BA + ESPICFG);
> + val |= ESPI_IO_MODE_SINGLE_DUAL_QUAD << ESPICFG_IOMODE_SHIFT;
> + val |= ESPI_MAX_33_MHZ << ESPICFG_MAXFREQ_SHIFT;
> + val |= ((espi_ch_supp & ESPICFG_CHNSUPP_MASK) << ESPICFG_CHNSUPP_SHFT);
> + writel(val, NPCM_ESPI_BA + ESPICFG);
> + } else {
> + /* Use LPC function */
> + writel((readl(&gcr->mfsel1) | (1 << MFSEL1_LPCSEL)), &gcr->mfsel1);
> + }
> +}
> +
> +int arch_cpu_init(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> +
> + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
> + /* enable cache to speed up system running */
> + if (get_sctlr() & CR_M)
> + return 0;
> +
> + icache_enable();
> + __asm_invalidate_dcache_all();
> + __asm_invalidate_tlb_all();
> + set_sctlr(get_sctlr() | CR_C);
> + }
> +
> + /* Power voltage select setup */
> + setbits_le32(&gcr->vsrcr, BIT(30));
> +
> + npcm_sysintf_init();
> +
> + return 0;
> +}
> +
> +static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
> + {
> + /* DRAM */
> + .phys = 0x0UL,
> + .virt = 0x0UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + },
> + {
> + .phys = 0x80000000UL,
> + .virt = 0x80000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + },
> + {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = npcm_mem_map;
> +
> +int timer_init(void)
> +{
> + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
> + unsigned int cntfrq_el0;
> +
> + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
> + writel(cntfrq_el0, &sctr->cntfid0);
> +
> + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
> + SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
> +
> + gd->arch.tbl = 0;
> + gd->arch.tbu = 0;
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/reset.c b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> new file mode 100644
> index 0000000000..7fbed7ba76
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/rst.h>
> +#include <asm/arch/gcr.h>
> +
> +void reset_cpu(void)
> +{
> + /* Watcdog reset - WTCR register set WTE-BIT7 WTRE-BIT1 WTR-BIT0 */
> + writel(0x83, 0xf000801c);
> +
> + while (1)
> + ;
> +}
> +
> +void reset_misc(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> +
> + /* clear WDC */
> + writel(readl(&gcr->intcr2) & ~(1 << INTCR2_WDC), &gcr->intcr2);
> +}
> +
> +enum reset_type npcm8xx_reset_reason(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> + enum reset_type type = UNKNOWN_TYPE;
> + u32 value = readl(&gcr->ressr);
> +
> + if (value == 0)
> + value = ~readl(&gcr->intcr2);
> +
> + value &= RESSR_MASK;
> +
> + if (value & CORST)
> + type = CORST;
> + if (value & WD0RST)
> + type = WD0RST;
> + if (value & WD1RST)
> + type = WD1RST;
> + if (value & WD2RST)
> + type = WD2RST;
> + if (value & PORST)
> + type = PORST;
> +
> + return type;
> +}
> diff --git a/board/nuvoton/arbel/Kconfig b/board/nuvoton/arbel/Kconfig
> new file mode 100644
> index 0000000000..4a03ea1abf
> --- /dev/null
> +++ b/board/nuvoton/arbel/Kconfig
> @@ -0,0 +1,18 @@
> +if TARGET_ARBEL_EVB
> +
> +config SYS_BOARD
> + default "arbel"
> +
> +config SYS_VENDOR
> + default "nuvoton"
> +
> +config SYS_CONFIG_NAME
> + default "arbel"
> +
> +config SYS_MEM_TOP_HIDE
> + hex "Reserved TOP memory"
> + default 0xB000000
> + help
> + Reserve memory for ECC/GFX/VCD/ECE.
> +
> +endif
> diff --git a/board/nuvoton/arbel/Makefile b/board/nuvoton/arbel/Makefile
> new file mode 100644
> index 0000000000..f9ad1dea34
> --- /dev/null
> +++ b/board/nuvoton/arbel/Makefile
> @@ -0,0 +1 @@
> +obj-y += arbel.o
> diff --git a/board/nuvoton/arbel/arbel.c b/board/nuvoton/arbel/arbel.c
> new file mode 100644
> index 0000000000..86cef98c5f
> --- /dev/null
> +++ b/board/nuvoton/arbel/arbel.c
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +#include <asm/arch/gcr.h>
> +#include <asm/mach-types.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> + gd->bd->bi_arch_number = MACH_TYPE_NPCMX50;
> + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100UL);
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> +
> + /*
> + * get dram active size value from bootblock.
> + * Value sent using scrpad_02 register.
> + */
> + gd->ram_size = readl(&gcr->scrpad_b);
> +
> + return 0;
> +}
> diff --git a/include/configs/arbel.h b/include/configs/arbel.h
> new file mode 100644
> index 0000000000..2cb658c3e6
> --- /dev/null
> +++ b/include/configs/arbel.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef __CONFIG_ARBEL_H
> +#define __CONFIG_ARBEL_H
> +
> +#define CONFIG_GICV2
> +#define GICD_BASE (0xDFFF9000)
> +#define GICC_BASE (0xDFFFA000)
> +
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_BOOTM_LEN (20 << 20)
> +#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
> +#define CONFIG_SYS_SDRAM_BASE 0x0
> +#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_HZ 1000
> +#define CONFIG_BITBANGMII_MULTI
> +
> +/* Default environemnt variables */
> +#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot"
> +#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
> + "stdin=serial\0" \
> + "stdout=serial\0" \
> + "stderr=serial\0" \
> + "ethact=gmac1\0" \
> + "autostart=no\0" \
> + "ethaddr=00:00:F7:A0:00:FC\0" \
> + "eth1addr=00:00:F7:A0:00:FD\0" \
> + "eth2addr=00:00:F7:A0:00:FE\0" \
> + "eth3addr=00:00:F7:A0:00:FF\0" \
> + "gatewayip=192.168.0.17\0" \
> + "serverip=192.168.0.17\0" \
> + "ipaddr=192.168.0.15\0" \
> + "romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
> + "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
> + "earlycon=uart8250,mmio32,0xf0000000\0" \
> + "console=ttyS0,115200n8\0" \
> + "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
> + "console=${console} ramdisk_size=48000\0" \
> + "\0"
> +
> +#endif
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
2021-12-15 2:57 ` [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree Stanley Chu
@ 2021-12-15 13:07 ` Tom Rini
2021-12-15 13:32 ` 盛
0 siblings, 1 reply; 31+ messages in thread
From: Tom Rini @ 2021-12-15 13:07 UTC (permalink / raw)
To: Stanley Chu
Cc: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77, u-boot, openbmc
[-- Attachment #1: Type: text/plain, Size: 319 bytes --]
On Wed, Dec 15, 2021 at 10:57:59AM +0800, Stanley Chu wrote:
> Add a common device tree for all Nuvoton NPCM8xx BMCs and a board
> specific device tree for the NPCM845(Arbel) evaluation board.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Which Linux kernel release are these from? Thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
2021-12-15 13:07 ` Tom Rini
@ 2021-12-15 13:32 ` 盛
2021-12-15 13:35 ` Tom Rini
0 siblings, 1 reply; 31+ messages in thread
From: 盛 @ 2021-12-15 13:32 UTC (permalink / raw)
To: Tom Rini
Cc: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, Stanley Chu, kwliu, ctcchien,
avifishman70, tmaimon77, u-boot, openbmc
Tom Rini <trini@konsulko.com> 於 2021年12月15日 週三 下午9:07寫道：
>
> On Wed, Dec 15, 2021 at 10:57:59AM +0800, Stanley Chu wrote:
>
> > Add a common device tree for all Nuvoton NPCM8xx BMCs and a board
> > specific device tree for the NPCM845(Arbel) evaluation board.
> >
> > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
>
> Which Linux kernel release are these from? Thanks!
These are new created because NPCM845 is an new generation BMC chip,
not upstream to Linux kernel yet.
>
> --
> Tom
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
2021-12-15 13:32 ` 盛
@ 2021-12-15 13:35 ` Tom Rini
2021-12-15 15:32 ` Jesse Taube
0 siblings, 1 reply; 31+ messages in thread
From: Tom Rini @ 2021-12-15 13:35 UTC (permalink / raw)
To: 盛
Cc: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, Stanley Chu, kwliu, ctcchien,
avifishman70, tmaimon77, u-boot, openbmc
[-- Attachment #1: Type: text/plain, Size: 745 bytes --]
On Wed, Dec 15, 2021 at 09:32:00PM +0800, 盛 wrote:
> Tom Rini <trini@konsulko.com> 於 2021年12月15日 週三 下午9:07寫道：
> >
> > On Wed, Dec 15, 2021 at 10:57:59AM +0800, Stanley Chu wrote:
> >
> > > Add a common device tree for all Nuvoton NPCM8xx BMCs and a board
> > > specific device tree for the NPCM845(Arbel) evaluation board.
> > >
> > > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> >
> > Which Linux kernel release are these from? Thanks!
> These are new created because NPCM845 is an new generation BMC chip,
> not upstream to Linux kernel yet.
OK. The device trees at least need to be in linux-next. That will
cover a lot of baseline review that needs to happen before we take it
in.
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
2021-12-15 13:35 ` Tom Rini
@ 2021-12-15 15:32 ` Jesse Taube
2021-12-15 15:39 ` Tom Rini
0 siblings, 1 reply; 31+ messages in thread
From: Jesse Taube @ 2021-12-15 15:32 UTC (permalink / raw)
To: Tom Rini, 盛
Cc: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, Stanley Chu, kwliu, ctcchien, avifishman70,
tmaimon77, u-boot, openbmc
> OK. The device trees at least need to be in linux-next. That will
> cover a lot of baseline review that needs to happen before we take it
> in.
>
Hi Tom!
If my understanding is correct device tree's should be accepted into
Linux-next before U-Boot, or am I wrong.
Also Stanley, I don't think I apply to this patch set...
When getting maintainers I think you should pass `--nogit --norolestats`.
I may be wrong about this though as I'm new to contributions.
Thanks,
Jesse T
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree
2021-12-15 15:32 ` Jesse Taube
@ 2021-12-15 15:39 ` Tom Rini
0 siblings, 0 replies; 31+ messages in thread
From: Tom Rini @ 2021-12-15 15:39 UTC (permalink / raw)
To: Jesse Taube
Cc: 盛,
lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, Stanley Chu, kwliu, ctcchien, avifishman70,
tmaimon77, u-boot, openbmc
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On Wed, Dec 15, 2021 at 10:32:21AM -0500, Jesse Taube wrote:
> > OK. The device trees at least need to be in linux-next. That will
> > cover a lot of baseline review that needs to happen before we take it
> > in.
> >
> Hi Tom!
> If my understanding is correct device tree's should be accepted into
> Linux-next before U-Boot, or am I wrong.
Yes, they should be in linux-next at least before going in to U-Boot.
--
Tom
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
2021-12-15 12:12 ` Giulio Benetti
@ 2021-12-15 18:32 ` Sean Anderson
2022-03-11 0:55 ` Stanley Chu
[not found] ` <d23d2925-d5ea-e23b-fb99-7856aedfb328@gmail.com>
2022-03-10 18:49 ` Tom Rini
2 siblings, 2 replies; 31+ messages in thread
From: Sean Anderson @ 2021-12-15 18:32 UTC (permalink / raw)
To: Stanley Chu, lukma, jagan, andre.przywara, festevam, narmstrong,
pbrobinson, tharvey, christianshewitt, lokeshvutla, sjg, sr,
michal.simek, hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, dsankouski,
vabhav.sharma, bmeng.cn, patrick, samuel, giulio.benetti,
mr.bossman075, yschu, kwliu, ctcchien, avifishman70, tmaimon77
Cc: u-boot, openbmc
On 12/14/21 9:57 PM, Stanley Chu wrote:
> Add basic support for the Nuvoton NPCM845 BMC.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> arch/arm/Kconfig | 9 +
> arch/arm/Makefile | 1 +
> arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
> arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
> arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
> arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
> arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
> arch/arm/mach-nuvoton/Kconfig | 24 ++
> arch/arm/mach-nuvoton/Makefile | 1 +
> arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
> arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
> arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
> arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
> board/nuvoton/arbel/Kconfig | 18 ++
> board/nuvoton/arbel/Makefile | 1 +
> board/nuvoton/arbel/arbel.c | 33 +++
> include/configs/arbel.h | 54 ++++
> 17 files changed, 924 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
> create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
> create mode 100644 arch/arm/mach-nuvoton/Kconfig
> create mode 100644 arch/arm/mach-nuvoton/Makefile
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
> create mode 100644 board/nuvoton/arbel/Kconfig
> create mode 100644 board/nuvoton/arbel/Makefile
> create mode 100644 board/nuvoton/arbel/arbel.c
> create mode 100644 include/configs/arbel.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f7f03837fe..80ec42f6be 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
> select LINUX_KERNEL_IMAGE_HEADER
> select XEN_SERIAL
> select SSCANF
> +
> +config ARCH_NPCM
> + bool "Support Nuvoton SoCs"
> + select DM
> + select OF_CONTROL
> + imply CMD_DM
> +
> endchoice
>
> config SUPPORT_PASSING_ATAGS
> @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
>
> source "arch/arm/mach-nexell/Kconfig"
>
> +source "arch/arm/mach-nuvoton/Kconfig"
> +
> source "board/armltd/total_compute/Kconfig"
>
> source "board/bosch/shc/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index ad757e982e..29a0250ab6 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
> machine-$(CONFIG_ARCH_ZYNQ) += zynq
> machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
> machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
> +machine-$(CONFIG_ARCH_NPCM) += nuvoton
>
> machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>
> diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
> new file mode 100644
> index 0000000000..088b536b7b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
Please add this (and all the other includes) in the patches adding the
drivers which use them. This makes it much easier to review.
Additionally, if these defines are not used elsewhere, they can be
included at the beginning of the clock driver itself.
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef _NPCM_CLOCK_H_
> +#define _NPCM_CLOCK_H_
> +
> +#define NPCM_CLK_BA 0xF0801000
> +enum {
Don't redefine these. Just use include/dt-bindings/clock/npcm845-clock.h
> + APB1 = 1,
> + APB2 = 2,
> + APB3 = 3,
> + APB4 = 4,
> + APB5 = 5,
> + SPI0 = 10,
> + SPI1 = 11,
> + SPI3 = 13,
> + SPIX = 14,
> +};
> +
> +/* Clock Select Register (CLKSEL) */
> +#define CLKSEL_RCPCKSEL 27
> +#define CLKSEL_RGSEL 25
> +#define CLKSEL_GFXMSEL 21
> +#define CLKSEL_CLKOUTSEL 18
> +#define CLKSEL_PCICKSEL 16
> +#define CLKSEL_ADCCKSEL 14
> +#define CLKSEL_MCCKSEL 12
> +#define CLKSEL_SUCKSEL 10
> +#define CLKSEL_UARTCKSEL 8
> +#define CLKSEL_SDCKSEL 6
> +#define CLKSEL_PIXCKSEL 4
> +#define CLKSEL_CPUCKSEL 0
Please use GENMASK for this. For example,
#define CLKSEL_CPUCKSEL GENMASK(1, 0)
This allows you to do things like
u32 clksel = readl(®s->clksel);
switch (FIELD_GET(CLKSEL_CPUCKSEL, clksel)) {
}
later on, instead of having magic masks everywhere.
> +
> +/* Clock Divider Control Register 1 (CLKDIV1) */
> +#define CLKDIV1_ADCCKDIV 28
> +#define CLKDIV1_CLK4DIV 26
> +#define CLKDIV1_PRE_ADCCKDIV 21
> +#define CLKDIV1_UARTDIV 16
> +#define CLKDIV1_MMCCKDIV 11
> +#define CLKDIV1_SPI3CKDIV 6
> +#define CLKDIV1_PCICKDIV 2
> +
> +/* Clock Divider Control Register 2 (CLKDIV2) */
> +#define CLKDIV2_APB4CKDIV 30
> +#define CLKDIV2_APB3CKDIV 28
> +#define CLKDIV2_APB2CKDIV 26
> +#define CLKDIV2_APB1CKDIV 24
> +#define CLKDIV2_APB5CKDIV 22
> +#define CLKDIV2_CLKOUTDIV 16
> +#define CLKDIV2_GFXCKDIV 13
> +#define CLKDIV2_SUCKDIV 8
> +#define CLKDIV2_SU48CKDIV 4
> +
> +/* PLL Control Register 2 (PLLCON2) */
> +#define PLLCON_LOKI 31
> +#define PLLCON_LOKS 30
> +#define PLLCON_FBDV 16
> +#define PLLCON_OTDV2 13
> +#define PLLCON_PWDEN 12
> +#define PLLCON_OTDV1 8
> +#define PLLCON_INDV 0
> +
> +/* CPUCKSEL (CPU/AMBA/MC Clock Source Select Bit) */
> +#define CLKSEL_CPUCKSEL_PLL0 0x00 /* 0 0: PLL0 clock*/
> +#define CLKSEL_CPUCKSEL_PLL1 0x01 /* 0 1: PLL1 clock */
> +#define CLKSEL_CPUCKSEL_CLKREF 0x02 /* 1 0: CLKREF input (25 MHZ, default) */
> +#define CLKSEL_CPUCKSEL_SYSBPCK 0x03 /* 1 1: Bypass clock from pin SYSBPCK */
> +
> +/* UARTCKSEL (Core and Host UART Clock Source Select Bit). */
> +#define CLKSEL_UARTCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> +#define CLKSEL_UARTCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> +#define CLKSEL_UARTCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> +#define CLKSEL_UARTCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> +
> +/* SDCKSEL (SDHC Clock Source Select Bit). */
> +#define CLKSEL_SDCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> +#define CLKSEL_SDCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> +#define CLKSEL_SDCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> +#define CLKSEL_SDCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> +
> +/* IP Software Reset Register 1 (IPSRST1), offset 0x20 */
If you have multiple logical devices in one group of registers, you
should look into organizing your bindings like
syscon@0xf0801000 {
compatible = "simple-mfd";
reg = <0x0 0xf0801000 0x0 0x70>;
clks: clock-controller {
compatible = "nuvoton,npcm845-clock";
#clock-cells = <1>;
clocks = <&some_oscillator>;
clock-names = "extclk";
u-boot,dm-pre-reloc;
};
rsts: reset-controller {
compatible = "nuvoton,npcm845-reset";
#reset-cells = <1>;
}
}
> +#define IPSRST1_USBDEV1 5
> +#define IPSRST1_USBDEV2 8
> +#define IPSRST1_USBDEV3 25
> +#define IPSRST1_USBDEV4 22
> +#define IPSRST1_USBDEV5 23
> +#define IPSRST1_USBDEV6 24
> +#define IPSRST1_GMAC4 21
> +#define IPSRST1_GMAC3 6
> +
> +/* IP Software Reset Register 2 (IPSRST2), offset 0x24 */
> +#define IPSRST2_GMAC1 28
> +#define IPSRST2_GMAC2 25
> +#define IPSRST2_USBHOST1 26
> +#define IPSRST2_SDHC 9
> +#define IPSRST2_MMC 8
> +
> +/* IP Software Reset Register 3 (IPSRST3), offset 0x34 */
> +#define IPSRST3_USBPHY1 24
> +#define IPSRST3_USBPHY2 25
> +#define IPSRST3_USBHUB 8
> +#define IPSRST3_USBDEV9 7
> +#define IPSRST3_USBDEV8 6
> +#define IPSRST3_USBDEV7 5
> +#define IPSRST3_USBDEV0 4
> +
> +/* IP Software Reset Register 4 (IPSRST4), offset 0x74 */
> +#define IPSRST4_USBHOST2 31
> +#define IPSRST4_USBPHY3 25
> +
> +#define EXT_CLOCK_FREQUENCY_KHZ 25 * 1000 * 1UL
> +#define EXT_CLOCK_FREQUENCY_MHZ 25
Just define it in HZ and divide it as needed. The compiler will optimize
it. But see also my comments on your other patch.
> +
> +struct clk_ctl {
Please name this npcm_clk_ctl or similar.
> + unsigned int clken1;
Please use u32/u64 as the case may be.
--Sean
> + unsigned int clksel;
> + unsigned int clkdiv1;
> + unsigned int pllcon0;
> + unsigned int pllcon1;
> + unsigned int swrstr;
> + unsigned char res1[0x8];
> + unsigned int ipsrst1;
> + unsigned int ipsrst2;
> + unsigned int clken2;
> + unsigned int clkdiv2;
> + unsigned int clken3;
> + unsigned int ipsrst3;
> + unsigned int wd0rcr;
> + unsigned int wd1rcr;
> + unsigned int wd2rcr;
> + unsigned int swrstc1;
> + unsigned int swrstc2;
> + unsigned int swrstc3;
> + unsigned int tiprstc;
> + unsigned int pllcon2;
> + unsigned int clkdiv3;
> + unsigned int corstc;
> + unsigned int pllcong;
> + unsigned int ahbckfi;
> + unsigned int seccnt;
> + unsigned int cntr25m;
> + unsigned int clken4;
> + unsigned int ipsrst4;
> + unsigned int busto;
> + unsigned int clkdiv4;
> + unsigned int wd0rcrb;
> + unsigned int wd1rcrb;
> + unsigned int wd2rcrb;
> + unsigned int swrstc1b;
> + unsigned int swrstc2b;
> + unsigned int swrstc3b;
> + unsigned int tiprstcb;
> + unsigned int corstcb;
> + unsigned int ipsrstdis1;
> + unsigned int ipsrstdis2;
> + unsigned int ipsrstdis3;
> + unsigned int ipsrstdis4;
> + unsigned char res2[0x10];
> + unsigned int thrtl_cnt;
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/espi.h b/arch/arm/include/asm/arch-npcm8xx/espi.h
> new file mode 100644
> index 0000000000..d4de012b02
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/espi.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +#ifndef _NPCM_ESPI_H_
> +#define _NPCM_ESPI_H_
> +
> +#define NPCM_ESPI_BA 0xF009F000
> +/* Register offsets */
> +#define ESPICFG 0x04
> +#define ESPIHINDP 0x80
> +
> +/* Channel Supported */
> +#define ESPICFG_CHNSUPP_MASK 0x0F
> +#define ESPICFG_CHNSUPP_SHFT 24
> +
> +/* I/O Mode Supported */
> +#define ESPICFG_IOMODE_SHIFT 8
> +#define ESPI_IO_MODE_SINGLE_DUAL_QUAD 3
> +
> +/* Maximum Frequency Supported */
> +#define ESPICFG_MAXFREQ_SHIFT 10
> +#define ESPI_MAX_33_MHZ 2
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> new file mode 100644
> index 0000000000..14a4b2dbfb
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> @@ -0,0 +1,313 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef _NPCM_GCR_H_
> +#define _NPCM_GCR_H_
> +
> +#define NPCM_GCR_BA 0xF0800000
> +/* On-Chip ARBEL NPCM8XX VERSIONS */
> +
> +#define ARBEL_Z1 0x00A35850
> +#define ARBEL_A1 0x04a35850
> +#define ARBEL_NPCM845 0x00000000
> +#define ARBEL_NPCM830 0x00300395
> +#define ARBEL_NPCM810 0x00000220
> +
> +/* Function Lock Register 2 (FLOCKR2) */
> +#define FLOCKR2_MMCRST 12
> +#define FLOCKR2_MMCRSTLK 13
> +#define FLOCKR2_G35DA2P 18
> +
> +/* Power-On Setting Register (PWRON) */
> +#define PWRON_BSPA 4 /* STRAP5 */
> +#define PWRON_SECEN 7 /* STRAP8 */
> +
> +/* Multiple Function Pin Select Register 1 (MFSEL1) */
> +#define MFSEL1_SIRQSE 31
> +#define MFSEL1_IOX1SEL 30
> +#define MFSEL1_HSI2BSEL 29
> +#define MFSEL1_HSI1BSEL 28
> +#define MFSEL1_DVH1SEL 27
> +#define MFSEL1_LPCSEL 26
> +#define MFSEL1_PECIB 25
> +#define MFSEL1_GSPISEL 24
> +#define MFSEL1_SMISEL 22
> +#define MFSEL1_CLKOSEL 21
> +#define MFSEL1_DVOSEL 18
> +#define MFSEL1_KBCICSEL 17
> +#define MFSEL1_R2MDSEL 16
> +#define MFSEL1_R2ERRSEL 15
> +#define MFSEL1_RMII2SEL 14
> +#define MFSEL1_R1MDSEL 13
> +#define MFSEL1_R1ERRSEL 12
> +#define MFSEL1_HSI2ASEL 11
> +#define MFSEL1_HSI1ASEL 10
> +#define MFSEL1_BSPSEL 9
> +#define MFSEL1_SMB2SEL 8
> +#define MFSEL1_SMB1SEL 7
> +#define MFSEL1_SMB0SEL 6
> +#define MFSEL1_HSI2CSEL 5
> +#define MFSEL1_HSI1CSEL 4
> +#define MFSEL1_S0CS1SEL 3
> +#define MFSEL1_SMB5SEL 2
> +#define MFSEL1_SMB4SEL 1
> +#define MFSEL1_SMB3SEL 0
> +
> +/* Multiple Function Pin Select Register 3 (MFSEL3) */
> +#define MFSEL3_DVODEDLY 27
> +#define MFSEL3_DDRDVOSEL 26
> +#define MFSEL3_MMCCDSEL 25
> +#define MFSEL3_BU1SEL 24
> +#define MFSEL3_I3C5SEL 22
> +#define MFSEL3_WDO2SEL 20
> +#define MFSEL3_WDO1SEL 19
> +#define MFSEL3_IOXHSEL 18
> +#define MFSEL3_PCIEPUSE 17
> +#define MFSEL3_CLKRUNSEL 16
> +#define MFSEL3_IOX2SEL 14
> +#define MFSEL3_PSPISEL 13
> +#define MFSEL3_MMC8SEL 11
> +#define MFSEL3_MMCSEL 10
> +#define MFSEL3_RMII1SEL 9
> +#define MFSEL3_SMB15SEL 8
> +#define MFSEL3_SMB14SEL 7
> +#define MFSEL3_SMB13SEL 6
> +#define MFSEL3_SMB12SEL 5
> +#define MFSEL3_SPI1SEL 4
> +#define MFSEL3_FIN1916SELB 3
> +#define MFSEL3_SMB7SEL 2
> +#define MFSEL3_SMB6SEL 1
> +#define MFSEL3_SCISEL 0
> +
> +/* Multiple Function Pin Select Register 4 (MFSEL4) */
> +#define MFSEL4_SMB11DDC 29
> +#define MFSEL4_SXCS1SEL 28
> +#define MFSEL4_SPXSEL 27
> +#define MFSEL4_RG2SEL 24
> +#define MFSEL4_RG2MSEL 23
> +#define MFSEL4_BU2SELB 22
> +#define MFSEL4_SG1MSEL 21
> +#define MFSEL4_SP3QSEL 20
> +#define MFSEL4_S3CS3SEL 19
> +#define MFSEL4_S3CS2SEL 18
> +#define MFSEL4_S3CS1SEL 17
> +#define MFSEL4_SP3SEL 16
> +#define MFSEL4_SP0QSEL 15
> +#define MFSEL4_SMB11SEL 14
> +#define MFSEL4_SMB10SEL 13
> +#define MFSEL4_SMB9SEL 12
> +#define MFSEL4_SMB8SEL 11
> +#define MFSEL4_DBGTRSEL 10
> +#define MFSEL4_CKRQSEL 9
> +#define MFSEL4_ESPISEL 8
> +#define MFSEL4_MMCRSEL 6
> +#define MFSEL4_SD1PSEL 5
> +#define MFSEL4_ROSEL 4
> +#define MFSEL4_ESPIPMESEL 2
> +#define MFSEL4_BSPASEL 1
> +#define MFSEL4_JTAG2SEL 0
> +
> +/* Multiple Function Pin Select Register 5 (MFSEL5) */
> +#define MFSEL5_R3OENSEL 14
> +#define MFSEL5_RMII3SEL 11
> +#define MFSEL5_R2OENSEL 10
> +#define MFSEL5_R1OENSEL 9
> +#define MFSEL5_NSPI1CS3SEL 5
> +#define MFSEL5_NSPI1CS2SEL 4
> +#define MFSEL5_SPI1D23SEL 3
> +#define MFSEL5_NSPI1CS1SEL 0
> +
> +/* Multiple Function Pin Select Register 6 (MFSEL6) */
> +#define MFSEL6_GPIO1836SEL 19
> +#define MFSEL6_FM1SEL 17
> +
> +/* Multiple Function Pin Select Register 7 (MFSEL7) */
> +#define MFSEL7_SMB15SELB 27
> +#define MFSEL7_GPIO1889SEL 25
> +
> +/* USB PHY1 Control Register (USB1PHYCTL) */
> +#define USB1PHYCTL_RS 28
> +/* USB PHY2 Control Register (USB2PHYCTL) */
> +#define USB2PHYCTL_RS 28
> +/* USB PHY2 Control Register (USB3PHYCTL) */
> +#define USB3PHYCTL_RS 28
> +
> +/* Integration Control Register (INTCR) */
> +#define INTCR_DUDKSMOD 30
> +#define INTCR_DDC3I 29
> +#define INTCR_KVMSI 28
> +#define INTCR_DEHS 27
> +#define INTCR_GGPCT2_0 24
> +#define INTCR_SGC2 23
> +#define INTCR_DSNS_TRIG 21
> +#define INTCR_DAC_SNS 20
> +#define INTCR_SGC1 19
> +#define INTCR_LDDRB 18
> +#define INTCR_GIRST 17
> +#define INTCR_DUDKSEN 16
> +#define INTCR_DACOFF 15
> +#define INTCR_DACSEL 14
> +#define INTCR_GFXINT 12
> +#define INTCR_DACOSOVR 10
> +#define INTCR_GFXIFDIS 8
> +#define INTCR_H2RQDIS 9
> +#define INTCR_H2DISPOFF 8
> +#define INTCR_GFXINT2 7
> +#define INTCR_VGAIOEN 6
> +#define INTCR_PSPIFEN 4
> +#define INTCR_HIFEN 3
> +#define INTCR_SMBFEN 2
> +#define INTCR_MFTFEN 1
> +#define INTCR_KCSRST_MODE 0
> +
> +/* Integration Control Register (INTCR2) */
> +#define INTCR2_WDC 21
> +
> +/* Integration Control Register (INTCR3) */
> +#define INTCR3_USBLPBK2 31 /* USB loop-backed HOST 1/2 */
> +#define INTCR3_USBLPBK 24 /* USB loop-backed mode on/off */
> +#define INTCR3_USBPHY3SW 14 /* 2 bits */
> +#define INTCR3_USBPHY2SW 12 /* 2 bits */
> +#define INTCR3_USBPPS 6
> +#define INTCR3_UHUB_RWUD 5
> +
> +/* Integration Control Register (INTCR4) */
> +#define INTCR4_GMMAP1 24
> +#define INTCR4_GMMAP0 16
> +#define INTCR4_R3EN 14
> +#define INTCR4_R2EN 13
> +#define INTCR4_R1EN 12
> +#define INTCR4_RGMIIREF 6
> +
> +/* I2C Segment Pin Select Register (I2CSEGSEL) */
> +#define I2CSEGSEL_S0DECFG 3
> +#define I2CSEGSEL_S4DECFG 17
> +
> +/* I2C Segment Control Register (I2CSEGCTL) */
> +#define I2CSEGCTL_S0DEN 20
> +#define I2CSEGCTL_S0DWE 21
> +#define I2CSEGCTL_S4DEN 24
> +#define I2CSEGCTL_S4DWE 25
> +#define I2CSEGCTL_INIT_VAL 0x9333F000
> +
> +struct npcm_gcr {
> + unsigned int pdid;
> + unsigned int pwron;
> + unsigned int swstrps;
> + unsigned int rsvd1[2];
> + unsigned int miscpe;
> + unsigned int spldcnt;
> + unsigned int rsvd2[1];
> + unsigned int flockr2;
> + unsigned int flockr3;
> + unsigned int rsvd3[3];
> + unsigned int a35_mode;
> + unsigned int spswc;
> + unsigned int intcr;
> + unsigned int intsr;
> + unsigned int obscr1;
> + unsigned int obsdr1;
> + unsigned int rsvd4[1];
> + unsigned int hifcr;
> + unsigned int rsvd5[3];
> + unsigned int intcr2;
> + unsigned int rsvd6[1];
> + unsigned int srcnt;
> + unsigned int ressr;
> + unsigned int rlockr1;
> + unsigned int flockr1;
> + unsigned int dscnt;
> + unsigned int mdlr;
> + unsigned int scrpad_c;
> + /* scrpad_b: holds the active dram size (value set by bootblock) */
> + unsigned int scrpad_b;
> + unsigned int rsvd7[4];
> + unsigned int daclvlr;
> + unsigned int intcr3;
> + unsigned int pcirctl;
> + unsigned int rsvd8[2];
> + unsigned int vsintr;
> + unsigned int rsvd9[1];
> + unsigned int sd2sur1;
> + unsigned int sd2sur2;
> + unsigned int sd2irv3;
> + unsigned int intcr4;
> + unsigned int obscr2;
> + unsigned int obsdr2;
> + unsigned int rsvd10[5];
> + unsigned int i2csegsel;
> + unsigned int i2csegctl;
> + unsigned int vsrcr;
> + unsigned int mlockr;
> + unsigned int rsvd11[8];
> + unsigned int etsr;
> + unsigned int dft1r;
> + unsigned int dft2r;
> + unsigned int dft3r;
> + unsigned int edffsr;
> + unsigned int rsvd12[1];
> + unsigned int intcrpce3;
> + unsigned int intcrpce2;
> + unsigned int intcrpce0;
> + unsigned int intcrpce1;
> + unsigned int dactest;
> + unsigned int scrpad;
> + unsigned int usb1phyctl;
> + unsigned int usb2phyctl;
> + unsigned int usb3phyctl;
> + unsigned int intsr2;
> + unsigned int intcrpce2b;
> + unsigned int intcrpce0b;
> + unsigned int intcrpce1b;
> + unsigned int intcrpce3b;
> + unsigned int rsvd13[4];
> + unsigned int intcrpce2c;
> + unsigned int intcrpce0c;
> + unsigned int intcrpce1c;
> + unsigned int intcrpce3c;
> + unsigned int rsvd14[40];
> + unsigned int sd2irv4;
> + unsigned int sd2irv5;
> + unsigned int sd2irv6;
> + unsigned int sd2irv7;
> + unsigned int sd2irv8;
> + unsigned int sd2irv9;
> + unsigned int sd2irv10;
> + unsigned int sd2irv11;
> + unsigned int rsvd15[8];
> + unsigned int mfsel1;
> + unsigned int mfsel2;
> + unsigned int mfsel3;
> + unsigned int mfsel4;
> + unsigned int mfsel5;
> + unsigned int mfsel6;
> + unsigned int mfsel7;
> + unsigned int rsvd16[1];
> + unsigned int mfsel_lk1;
> + unsigned int mfsel_lk2;
> + unsigned int mfsel_lk3;
> + unsigned int mfsel_lk4;
> + unsigned int mfsel_lk5;
> + unsigned int mfsel_lk6;
> + unsigned int mfsel_lk7;
> + unsigned int rsvd17[1];
> + unsigned int mfsel_set1;
> + unsigned int mfsel_set2;
> + unsigned int mfsel_set3;
> + unsigned int mfsel_set4;
> + unsigned int mfsel_set5;
> + unsigned int mfsel_set6;
> + unsigned int mfsel_set7;
> + unsigned int rsvd18[1];
> + unsigned int mfsel_clr1;
> + unsigned int mfsel_clr2;
> + unsigned int mfsel_clr3;
> + unsigned int mfsel_clr4;
> + unsigned int mfsel_clr5;
> + unsigned int mfsel_clr6;
> + unsigned int mfsel_clr7;
> + };
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/gpio.h b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> new file mode 100644
> index 0000000000..234a1d3de9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef _NPCM_GPIO_H_
> +#define _NPCM_GPIO_H_
> +
> +#define NPCM_GPIO_BA 0xF0010000
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
> new file mode 100644
> index 0000000000..ffaff50fe2
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +#ifndef _NPCM_RST_H_
> +#define _NPCM_RST_H_
> +
> +enum reset_type {
> + PORST_TYPE = 0x01,
> + CORST_TYPE = 0x02,
> + WD0RST_TYPE = 0x03,
> + SWR1ST_TYPE = 0x04,
> + SWR2ST_TYPE = 0x05,
> + SWR3ST_TYPE = 0x06,
> + SWR4ST_TYPE = 0x07,
> + WD1RST_TYPE = 0x08,
> + WD2RST_TYPE = 0x09,
> + UNKNOWN_TYPE = 0x10,
> +};
> +
> +#define PORST 0x80000000
> +#define CORST 0x40000000
> +#define WD0RST 0x20000000
> +#define SWR1ST 0x10000000
> +#define SWR2ST 0x08000000
> +#define SWR3ST 0x04000000
> +#define SWR4ST 0x02000000
> +#define WD1RST 0x01000000
> +#define WD2RST 0x00800000
> +#define RESSR_MASK 0xff800000
> +
> +enum reset_type npcm8xx_reset_reason(void);
> +
> +#endif
> diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig
> new file mode 100644
> index 0000000000..e014dd4b79
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/Kconfig
> @@ -0,0 +1,24 @@
> +if ARCH_NPCM
> +
> +config SYS_ARCH
> + default "arm"
> +
> +config SYS_TEXT_BASE
> + default 0x8000
> +
> +choice
> + prompt "Nuvoton SoC select"
> + default ARCH_NPCM8XX
> +
> +config ARCH_NPCM8XX
> + bool "Support Nuvoton NPCM8xx SoC"
> + select ARM64
> + help
> + General support for NPCM8xx BMC (Arbel).
> + Nuvoton NPCM8xx BMC is based on the Cortex A35.
> +
> +endchoice
> +
> +source "arch/arm/mach-nuvoton/npcm8xx/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile
> new file mode 100644
> index 0000000000..e75689a1a0
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/Kconfig b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> new file mode 100644
> index 0000000000..478a046ad5
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> @@ -0,0 +1,18 @@
> +if ARCH_NPCM8XX
> +
> +config SYS_CPU
> + default "armv8"
> +
> +config SYS_SOC
> + default "npcm8xx"
> +
> +config TARGET_ARBEL_EVB
> + bool "Arbel-EVB"
> + help
> + ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
> + supports general functions of Basebase Management Controller
> + (BMC).
> +
> +source "board/nuvoton/arbel/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/Makefile b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> new file mode 100644
> index 0000000000..c62a4aa20a
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> @@ -0,0 +1 @@
> +obj-y += reset.o cpu.o
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/cpu.c b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> new file mode 100644
> index 0000000000..8a7315d535
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> @@ -0,0 +1,170 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <cpu_func.h>
> +#include <asm/io.h>
> +#include <asm/arch/gcr.h>
> +#include <asm/arch/espi.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/system.h>
> +#include <asm/global_data.h>
> +
> +/* System Counter */
> +struct sctr_regs {
> + u32 cntcr;
> + u32 cntsr;
> + u32 cntcv1;
> + u32 cntcv2;
> + u32 resv1[4];
> + u32 cntfid0;
> + u32 cntfid1;
> + u32 cntfid2;
> + u32 resv2[1001];
> + u32 counterid[1];
> +};
> +
> +#define SC_CNTCR_ENABLE BIT(0)
> +#define SC_CNTCR_HDBG BIT(1)
> +#define SC_CNTCR_FREQ0 BIT(8)
> +#define SC_CNTCR_FREQ1 BIT(9)
> +
> +#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int print_cpuinfo(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> + unsigned int id = 0;
> + unsigned long mpidr_val = 0;
> + unsigned int mdlr = 0;
> +
> + asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
> +
> + mdlr = readl(&gcr->mdlr);
> +
> + printf("CPU-%d: ", (unsigned int)(mpidr_val & 0x3));
> +
> + switch (mdlr) {
> + case ARBEL_NPCM845:
> + printf("NPCM845 ");
> + break;
> + case ARBEL_NPCM830:
> + printf("NPCM830 ");
> + break;
> + case ARBEL_NPCM810:
> + printf("NPCM810 ");
> + break;
> + default:
> + printf("NPCM8XX ");
> + break;
> + }
> +
> + id = readl(&gcr->pdid);
> + switch (id) {
> + case ARBEL_Z1:
> + printf("Z1 @ ");
> + break;
> + case ARBEL_A1:
> + printf("A1 @ ");
> + break;
> + default:
> + printf("Unknown\n");
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void npcm_sysintf_init(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> + u32 espi_ch_supp, val;
> +
> + espi_ch_supp = ofnode_conf_read_int("espi-channel-support", 0);
> +
> + if (espi_ch_supp) {
> + /* Use eSPI function and initialize ESPICFG */
> + u32 hindp = 0x00011110 | espi_ch_supp;
> +
> + writel((readl(&gcr->mfsel4) | (1 << MFSEL4_ESPISEL)), &gcr->mfsel4);
> + writel(hindp, NPCM_ESPI_BA + ESPIHINDP);
> + val = readl(NPCM_ESPI_BA + ESPICFG);
> + val |= ESPI_IO_MODE_SINGLE_DUAL_QUAD << ESPICFG_IOMODE_SHIFT;
> + val |= ESPI_MAX_33_MHZ << ESPICFG_MAXFREQ_SHIFT;
> + val |= ((espi_ch_supp & ESPICFG_CHNSUPP_MASK) << ESPICFG_CHNSUPP_SHFT);
> + writel(val, NPCM_ESPI_BA + ESPICFG);
> + } else {
> + /* Use LPC function */
> + writel((readl(&gcr->mfsel1) | (1 << MFSEL1_LPCSEL)), &gcr->mfsel1);
> + }
> +}
> +
> +int arch_cpu_init(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> +
> + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
> + /* enable cache to speed up system running */
> + if (get_sctlr() & CR_M)
> + return 0;
> +
> + icache_enable();
> + __asm_invalidate_dcache_all();
> + __asm_invalidate_tlb_all();
> + set_sctlr(get_sctlr() | CR_C);
> + }
> +
> + /* Power voltage select setup */
> + setbits_le32(&gcr->vsrcr, BIT(30));
> +
> + npcm_sysintf_init();
> +
> + return 0;
> +}
> +
> +static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
> + {
> + /* DRAM */
> + .phys = 0x0UL,
> + .virt = 0x0UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + },
> + {
> + .phys = 0x80000000UL,
> + .virt = 0x80000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + },
> + {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = npcm_mem_map;
> +
> +int timer_init(void)
> +{
> + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
> + unsigned int cntfrq_el0;
> +
> + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
> + writel(cntfrq_el0, &sctr->cntfid0);
> +
> + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
> + SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
> +
> + gd->arch.tbl = 0;
> + gd->arch.tbu = 0;
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-nuvoton/npcm8xx/reset.c b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> new file mode 100644
> index 0000000000..7fbed7ba76
> --- /dev/null
> +++ b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/rst.h>
> +#include <asm/arch/gcr.h>
> +
> +void reset_cpu(void)
> +{
> + /* Watcdog reset - WTCR register set WTE-BIT7 WTRE-BIT1 WTR-BIT0 */
> + writel(0x83, 0xf000801c);
> +
> + while (1)
> + ;
> +}
> +
> +void reset_misc(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> +
> + /* clear WDC */
> + writel(readl(&gcr->intcr2) & ~(1 << INTCR2_WDC), &gcr->intcr2);
> +}
> +
> +enum reset_type npcm8xx_reset_reason(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> + enum reset_type type = UNKNOWN_TYPE;
> + u32 value = readl(&gcr->ressr);
> +
> + if (value == 0)
> + value = ~readl(&gcr->intcr2);
> +
> + value &= RESSR_MASK;
> +
> + if (value & CORST)
> + type = CORST;
> + if (value & WD0RST)
> + type = WD0RST;
> + if (value & WD1RST)
> + type = WD1RST;
> + if (value & WD2RST)
> + type = WD2RST;
> + if (value & PORST)
> + type = PORST;
> +
> + return type;
> +}
> diff --git a/board/nuvoton/arbel/Kconfig b/board/nuvoton/arbel/Kconfig
> new file mode 100644
> index 0000000000..4a03ea1abf
> --- /dev/null
> +++ b/board/nuvoton/arbel/Kconfig
> @@ -0,0 +1,18 @@
> +if TARGET_ARBEL_EVB
> +
> +config SYS_BOARD
> + default "arbel"
> +
> +config SYS_VENDOR
> + default "nuvoton"
> +
> +config SYS_CONFIG_NAME
> + default "arbel"
> +
> +config SYS_MEM_TOP_HIDE
> + hex "Reserved TOP memory"
> + default 0xB000000
> + help
> + Reserve memory for ECC/GFX/VCD/ECE.
> +
> +endif
> diff --git a/board/nuvoton/arbel/Makefile b/board/nuvoton/arbel/Makefile
> new file mode 100644
> index 0000000000..f9ad1dea34
> --- /dev/null
> +++ b/board/nuvoton/arbel/Makefile
> @@ -0,0 +1 @@
> +obj-y += arbel.o
> diff --git a/board/nuvoton/arbel/arbel.c b/board/nuvoton/arbel/arbel.c
> new file mode 100644
> index 0000000000..86cef98c5f
> --- /dev/null
> +++ b/board/nuvoton/arbel/arbel.c
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +#include <asm/arch/gcr.h>
> +#include <asm/mach-types.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_init(void)
> +{
> + gd->bd->bi_arch_number = MACH_TYPE_NPCMX50;
> + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100UL);
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> +
> + /*
> + * get dram active size value from bootblock.
> + * Value sent using scrpad_02 register.
> + */
> + gd->ram_size = readl(&gcr->scrpad_b);
> +
> + return 0;
> +}
> diff --git a/include/configs/arbel.h b/include/configs/arbel.h
> new file mode 100644
> index 0000000000..2cb658c3e6
> --- /dev/null
> +++ b/include/configs/arbel.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2021 Nuvoton Technology Corp.
> + */
> +
> +#ifndef __CONFIG_ARBEL_H
> +#define __CONFIG_ARBEL_H
> +
> +#define CONFIG_GICV2
> +#define GICD_BASE (0xDFFF9000)
> +#define GICC_BASE (0xDFFFA000)
> +
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SYS_MAXARGS 32
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_BOOTM_LEN (20 << 20)
> +#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
> +#define CONFIG_SYS_SDRAM_BASE 0x0
> +#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_HZ 1000
> +#define CONFIG_BITBANGMII_MULTI
> +
> +/* Default environemnt variables */
> +#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot"
> +#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
> + "stdin=serial\0" \
> + "stdout=serial\0" \
> + "stderr=serial\0" \
> + "ethact=gmac1\0" \
> + "autostart=no\0" \
> + "ethaddr=00:00:F7:A0:00:FC\0" \
> + "eth1addr=00:00:F7:A0:00:FD\0" \
> + "eth2addr=00:00:F7:A0:00:FE\0" \
> + "eth3addr=00:00:F7:A0:00:FF\0" \
> + "gatewayip=192.168.0.17\0" \
> + "serverip=192.168.0.17\0" \
> + "ipaddr=192.168.0.15\0" \
> + "romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
> + "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
> + "earlycon=uart8250,mmio32,0xf0000000\0" \
> + "console=ttyS0,115200n8\0" \
> + "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
> + "console=${console} ramdisk_size=48000\0" \
> + "\0"
> +
> +#endif
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845
2021-12-15 2:57 ` [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845 Stanley Chu
@ 2021-12-15 18:32 ` Sean Anderson
2022-02-16 16:25 ` Tom Rini
1 sibling, 0 replies; 31+ messages in thread
From: Sean Anderson @ 2021-12-15 18:32 UTC (permalink / raw)
To: Stanley Chu, lukma, jagan, andre.przywara, festevam, narmstrong,
pbrobinson, tharvey, christianshewitt, lokeshvutla, sjg, sr,
michal.simek, hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, dsankouski,
vabhav.sharma, bmeng.cn, patrick, samuel, giulio.benetti,
mr.bossman075, yschu, kwliu, ctcchien, avifishman70, tmaimon77
Cc: u-boot, openbmc
On 12/14/21 9:57 PM, Stanley Chu wrote:
> Add clock controller driver for NPCM845
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> drivers/clk/Makefile | 1 +
> drivers/clk/nuvoton/Makefile | 1 +
> drivers/clk/nuvoton/clk_npcm8xx.c | 213 ++++++++++++++++++++++
> include/dt-bindings/clock/npcm845-clock.h | 17 ++
> 4 files changed, 232 insertions(+)
> create mode 100644 drivers/clk/nuvoton/Makefile
> create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
> create mode 100644 include/dt-bindings/clock/npcm845-clock.h
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 711ae5bc29..a3b64b73c2 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -53,3 +53,4 @@ obj-$(CONFIG_STM32H7) += clk_stm32h7.o
> obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
> obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
> obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
> +obj-$(CONFIG_ARCH_NPCM) += nuvoton/
Please keep this in alphabetical order (I know the file isn't perfect).
> diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile
> new file mode 100644
> index 0000000000..998e5329bb
> --- /dev/null
> +++ b/drivers/clk/nuvoton/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_ARCH_NPCM8XX) += clk_npcm8xx.o
> diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c
> new file mode 100644
> index 0000000000..c547c47e82
> --- /dev/null
> +++ b/drivers/clk/nuvoton/clk_npcm8xx.c
> @@ -0,0 +1,213 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021 Nuvoton Technology.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <clk-uclass.h>
> +#include <asm/types.h>
> +#include <asm/arch/clock.h>
Please add this include file in this patch.
> +#include <asm/io.h>
> +#include <linux/delay.h>
> +#include <dt-bindings/clock/npcm845-clock.h>
Please order these correctly. See https://www.denx.de/wiki/U-Boot/CodingStyle#Include_files
> +
> +struct npcm_clk_priv {
> + struct clk_ctl *regs;
> +};
> +
> +enum regss {
perhaps "pll_id" or similar?
> + PLL_0,
> + PLL_1,
> + PLL_2,
> + PLL_CLKREF,
> +};
> +
> +static u32 clk_get_pll_freq(struct clk_ctl *regs, enum regss pll)
> +{
> + u32 pllval;
> + u32 fin = EXT_CLOCK_FREQUENCY_KHZ; /* 25KHz */
Please get this from the device tree.
> + u32 fout, nr, nf, no;
> +
> + switch (pll) {
> + case PLL_0:
> + pllval = readl(®s->pllcon0);
> + break;
> + case PLL_1:
> + pllval = readl(®s->pllcon1);
> + break;
> + case PLL_2:
> + pllval = readl(®s->pllcon2);
> + break;
> + case PLL_CLKREF:
This is not used.
> + default:
> + return 0;
> + }
> +
> + /* PLL Input Clock Divider */
> + nr = (pllval >> PLLCON_INDV) & 0x1f;
With
#define PLLCON_INDV GENMASK(6, 0)
you can do
nr = FIELD_GET(PLLCON_INDV, pllval);
This applies to all your other register accesses.
> + /* PLL VCO Output Clock Feedback Divider */
> + nf = (pllval >> PLLCON_FBDV) & 0xfff;
> + /* PLL Output Clock Divider 1 */
> + no = ((pllval >> PLLCON_OTDV1) & 0x7) *
> + ((pllval >> PLLCON_OTDV2) & 0x7);
> +
> + fout = ((10 * fin * nf) / (no * nr));
Can this overflow? Can you add a comment about that?
> +
> + return fout * 100;
Where do these 10 and 100 factors come from? Please combine them.
> +}
> +
> +static u32 npcm_mmc_set_rate(struct clk_ctl *regs, ulong rate)
> +{
> + u32 pll0_freq, div, sdhci_clk;
> +
> + /* To acquire PLL0 frequency. */
> + pll0_freq = clk_get_pll_freq(regs, PLL_0);
> +
> + /* Calculate rounded up div to produce closest to
> + * target output clock
> + */
> + div = (pll0_freq % rate == 0) ? (pll0_freq / rate) :
> + (pll0_freq / rate) + 1;
div = DIV_ROUND_UP(pll0_freq, rate);
> +
> + writel((readl(®s->clkdiv1) & ~(0x1f << CLKDIV1_MMCCKDIV))
> + | (div - 1) << CLKDIV1_MMCCKDIV, ®s->clkdiv1);
example of FIELD_PREP:
clkdiv1 = readl(®s->clkdiv1);
clkdiv1 &= ~CLKDIV1_MMCCKDIV;
clkdiv1 |= FIELD_PREP(CLKDIV1_MMCCKDIV, div - 1);
writel(clkdiv1, ®s->clkdiv1);
You don't have to break out each line, but please apply this to your
register writes.
> +
> + /* Wait to the div to stabilize */
> + udelay(100);
> +
> + /* Select PLL0 as source */
> + writel((readl(®s->clksel) & ~(0x3 << CLKSEL_SDCKSEL))
> + | (CLKSEL_SDCKSEL_PLL0 << CLKSEL_SDCKSEL),
> + ®s->clksel);
> +
> + sdhci_clk = pll0_freq / div;
> +
> + return sdhci_clk;
> +}
> +
> +static u32 npcm_uart_set_rate(struct clk_ctl *regs, ulong rate)
> +{
> + u32 src_freq, div;
> +
> + src_freq = clk_get_pll_freq(regs, PLL_2) / 2;
> + div = (src_freq % rate == 0) ? (src_freq / rate) :
> + (src_freq / rate) + 1;
> + writel((readl(®s->clkdiv1) & ~(0x1f << CLKDIV1_UARTDIV))
> + | (div - 1) << CLKDIV1_UARTDIV, ®s->clkdiv1);
> + writel((readl(®s->clksel) & ~(3 << CLKSEL_UARTCKSEL))
> + | (CLKSEL_UARTCKSEL_PLL2 << CLKSEL_UARTCKSEL),
> + ®s->clksel);
> +
> + return (src_freq / div);
> +}
> +
> +static ulong npcm_get_cpu_freq(struct clk_ctl *regs)
> +{
> + ulong fout = 0;
> + u32 clksel = readl(®s->clksel) & (0x3 << CLKSEL_CPUCKSEL);
> +
> + if (clksel == CLKSEL_CPUCKSEL_PLL0)
Use a switch here.
> + fout = (ulong)clk_get_pll_freq(regs, PLL_0);
> + else if (clksel == CLKSEL_CPUCKSEL_PLL1)
> + fout = (ulong)clk_get_pll_freq(regs, PLL_1);
> + else if (clksel == CLKSEL_CPUCKSEL_CLKREF)
> + fout = EXT_CLOCK_FREQUENCY_MHZ; /* FOUT is specified in MHz */
> + else
> + fout = EXT_CLOCK_FREQUENCY_MHZ; /* FOUT is specified in MHz */
> +
> + return fout;
> +}
> +
> +static u32 npcm_get_apb_divisor(struct clk_ctl *regs, u32 apb)
> +{
> + u32 apb_divisor = 2;
Just inline this. E.g.
return 2 << ...;
> +
> + /* AHBn div */
> + apb_divisor = apb_divisor * (1 << ((readl(®s->clkdiv1)
> + >> CLKDIV1_CLK4DIV) & 0x3));
> +
> + switch (apb) {
> + case APB2: /* APB divisor */
> + apb_divisor = apb_divisor *
> + (1 << ((readl(®s->clkdiv2)
> + >> CLKDIV2_APB2CKDIV) & 0x3));
> + break;
> + case APB5: /* APB divisor */
> + apb_divisor = apb_divisor *
> + (1 << ((readl(®s->clkdiv2)
> + >> CLKDIV2_APB5CKDIV) & 0x3));
> + break;
> + default:
> + apb_divisor = 0xFFFFFFFF;
Isn't getting here a bug?
> + break;
> + }
> +
> + return apb_divisor;
> +}
> +
> +static ulong npcm_clk_get_rate(struct clk *clk)
> +{
> + struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case CLK_APB2:
> + return npcm_get_cpu_freq(priv->regs) /
> + npcm_get_apb_divisor(priv->regs, APB2);
> + case CLK_APB5:
> + return npcm_get_cpu_freq(priv->regs) /
> + npcm_get_apb_divisor(priv->regs, APB5);
I think you can use a more modular approach here:
struct clk parent;
switch (clk->id) {
case CLK_APB2:
parent.id = CLK_AHB;
ret = clk_request(clk->dev, &parent);
if (ret)
return ret;
fin = clk_get_rate(&parent);
if (IS_ERR_VALUE(fin))
return fin;
return fin / FIELD_GET(CLKDIV2_APB2CKDIV, readl(®s->clkdiv2));
}
And of course you can go further and create some arrays to hold those
parameters if you like.
This switch statement should also return -ENOSYS in the default case.
> + }
> +
> + return 0;
> +}
> +
> +static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case CLK_EMMC:
> + return npcm_mmc_set_rate(priv->regs, rate);
> +
> + case CLK_UART:
> + return npcm_uart_set_rate(priv->regs, rate);
> + default:
> + return -ENOENT;
-ENOSYS
> + }
> +
> + return 0;
> +}
> +
> +static int npcm_clk_probe(struct udevice *dev)
> +{
> + struct npcm_clk_priv *priv = dev_get_priv(dev);
> + void *base;
> +
> + base = dev_read_addr_ptr(dev);
> + if (!base)
> + return -ENOENT;
> +
> + priv->regs = (struct clk_ctl *)base;
You can directly assign to regs. And there is no need to cast here,
since base is a void pointer.
> +
> + return 0;
> +}
> +
> +static struct clk_ops npcm_clk_ops = {
> + .get_rate = npcm_clk_get_rate,
> + .set_rate = npcm_clk_set_rate,
Please add a .request callback which enforces the max clock id.
--Sean
> +};
> +
> +static const struct udevice_id npcm_clk_ids[] = {
> + { .compatible = "nuvoton,npcm845-clock" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_npcm) = {
> + .name = "clk_npcm",
> + .id = UCLASS_CLK,
> + .of_match = npcm_clk_ids,
> + .ops = &npcm_clk_ops,
> + .priv_auto = sizeof(struct npcm_clk_priv),
> + .probe = npcm_clk_probe,
> +};
> diff --git a/include/dt-bindings/clock/npcm845-clock.h b/include/dt-bindings/clock/npcm845-clock.h
> new file mode 100644
> index 0000000000..fca10d39c8
> --- /dev/null
> +++ b/include/dt-bindings/clock/npcm845-clock.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +#ifndef _DT_BINDINGS_NPCM845_CLOCK_H_
> +#define _DT_BINDINGS_NPCM845_CLOCK_H_
> +
> +#define CLK_TIMER 0
> +#define CLK_UART 1
> +#define CLK_SD 2
> +#define CLK_EMMC 3
> +#define CLK_APB1 4
> +#define CLK_APB2 5
> +#define CLK_APB3 6
> +#define CLK_APB4 7
> +#define CLK_APB5 8
> +#define CLK_AHB 9
> +
> +#endif
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845
2021-12-15 2:57 ` [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845 Stanley Chu
2021-12-15 18:32 ` Sean Anderson
@ 2022-02-16 16:25 ` Tom Rini
2022-02-17 2:08 ` Stanley
1 sibling, 1 reply; 31+ messages in thread
From: Tom Rini @ 2022-02-16 16:25 UTC (permalink / raw)
To: Stanley Chu
Cc: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77, u-boot, openbmc
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On Wed, Dec 15, 2021 at 10:57:53AM +0800, Stanley Chu wrote:
> Add clock controller driver for NPCM845
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> ---
> drivers/clk/Makefile | 1 +
> drivers/clk/nuvoton/Makefile | 1 +
> drivers/clk/nuvoton/clk_npcm8xx.c | 213 ++++++++++++++++++++++
> include/dt-bindings/clock/npcm845-clock.h | 17 ++
> 4 files changed, 232 insertions(+)
> create mode 100644 drivers/clk/nuvoton/Makefile
> create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
> create mode 100644 include/dt-bindings/clock/npcm845-clock.h
Following up here, Sean had comments and while I've seen follow-up timer
and serial patches, I haven't seen a follow-up clk patch.
--
Tom
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845
2022-02-16 16:25 ` Tom Rini
@ 2022-02-17 2:08 ` Stanley
0 siblings, 0 replies; 31+ messages in thread
From: Stanley @ 2022-02-17 2:08 UTC (permalink / raw)
To: Tom Rini; +Cc: seanga2, u-boot
Hi Tom,
Thanks for the reminder. I made a big change on clk driver and will
submit the new patch later.
--
Stanley
Tom Rini <trini@konsulko.com> 於 2022年2月17日 週四 上午12:25 寫道：
>
> On Wed, Dec 15, 2021 at 10:57:53AM +0800, Stanley Chu wrote:
>
> > Add clock controller driver for NPCM845
> >
> > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > ---
> > drivers/clk/Makefile | 1 +
> > drivers/clk/nuvoton/Makefile | 1 +
> > drivers/clk/nuvoton/clk_npcm8xx.c | 213 ++++++++++++++++++++++
> > include/dt-bindings/clock/npcm845-clock.h | 17 ++
> > 4 files changed, 232 insertions(+)
> > create mode 100644 drivers/clk/nuvoton/Makefile
> > create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c
> > create mode 100644 include/dt-bindings/clock/npcm845-clock.h
>
> Following up here, Sean had comments and while I've seen follow-up timer
> and serial patches, I haven't seen a follow-up clk patch.
>
> --
> Tom
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
2021-12-15 12:12 ` Giulio Benetti
2021-12-15 18:32 ` Sean Anderson
@ 2022-03-10 18:49 ` Tom Rini
2022-03-11 2:13 ` Stanley Chu
2 siblings, 1 reply; 31+ messages in thread
From: Tom Rini @ 2022-03-10 18:49 UTC (permalink / raw)
To: Stanley Chu
Cc: lukma, jagan, andre.przywara, festevam, narmstrong, pbrobinson,
tharvey, christianshewitt, lokeshvutla, sjg, sr, michal.simek,
hs, weijie.gao, hannes.schmelzer, harm.berntsen,
sebastian.reichel, stephan, fangyuanseu, kettenis, seanga2,
dsankouski, vabhav.sharma, bmeng.cn, patrick, samuel,
giulio.benetti, mr.bossman075, yschu, kwliu, ctcchien,
avifishman70, tmaimon77, u-boot, openbmc
[-- Attachment #1: Type: text/plain, Size: 498 bytes --]
On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote:
> Add basic support for the Nuvoton NPCM845 BMC.
>
> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
I see there's a number of outstanding questions to this first part of
the port. Can you please address them? Furthermore, the defconfig and
dts patches should be part of this first patch and the dts needs to be
in linux-next at least, if not a full linux kernel release. Thanks and
sorry for the delay here.
--
Tom
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
[not found] ` <0fee2e28-b3c8-d649-0921-52e6fb098e71@gmail.com>
@ 2022-03-11 0:39 ` Stanley Chu
0 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2022-03-11 0:39 UTC (permalink / raw)
To: Sean Anderson, Tom Rini
Cc: lukma, sjg, sr, hs, Stanley Chu, kwliu, ctcchien, avifishman70,
tmaimon77, u-boot
Hi Sean,
Thanks for the review.
It is addressed in the gpio driver patch as below.
https://patchwork.ozlabs.org/project/uboot/patch/20220225021450.18690-1-yschu@nuvoton.com/
--
Stanley
On Thu, Dec 16, 2021 at 6:30 AM Sean Anderson <seanga2@gmail.com> wrote:
>
> On 12/15/21 5:16 PM, Jesse Taube wrote:
> >
> >
> > On 12/15/21 13:32, Sean Anderson wrote:
> >> On 12/14/21 9:57 PM, Stanley Chu wrote:
> >>> Add basic support for the Nuvoton NPCM845 BMC.
> >>>
> >>> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> >>> ---
> >>> arch/arm/Kconfig | 9 +
> >>> arch/arm/Makefile | 1 +
> >>> arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
> >>> arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
> >>> arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
> >>> arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
> >>> arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
> >>> arch/arm/mach-nuvoton/Kconfig | 24 ++
> >>> arch/arm/mach-nuvoton/Makefile | 1 +
> >>> arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
> >>> arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
> >>> arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
> >>> arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
> >>> board/nuvoton/arbel/Kconfig | 18 ++
> >>> board/nuvoton/arbel/Makefile | 1 +
> >>> board/nuvoton/arbel/arbel.c | 33 +++
> >>> include/configs/arbel.h | 54 ++++
> >>> 17 files changed, 924 insertions(+)
> > Hello World!
> >
> > Because I was CC'ed I guess I will keep myself up-to date.
> > This commit has 17 files changed and almost 1k insertions,
> > That is a relatively large commit. Would it be better to split
> > /arch/arm/include/asm
> > /arch/arm/mach-nuvoton
> > /board
> > /include/configs
> > into different commits.
> > I ask this because I split them for a patch I'm working on
>
> Please submit the relevant headers with their drivers.
>
> For example, arch/arm/include/asm/arch-npcm8xx/gpio.h should go
> in "[PATCH v1 5/9] gpio: npcm: Add support for Nuvoton NPCM SoCs"
>
> --Sean
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2021-12-15 12:12 ` Giulio Benetti
@ 2022-03-11 0:50 ` Stanley Chu
2022-03-11 1:06 ` Giulio Benetti
0 siblings, 1 reply; 31+ messages in thread
From: Stanley Chu @ 2022-03-11 0:50 UTC (permalink / raw)
To: Giulio Benetti, Tom Rini; +Cc: kwliu, ctcchien, avifishman70, tmaimon77, u-boot
Hi Giulio,
Thank you for your comment, I've submitted a clk driver patch to address this.
https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-yschu@nuvoton.com/
--
Stanley
On Wed, Dec 15, 2021 at 8:12 PM Giulio Benetti
<giulio.benetti@benettiengineering.com> wrote:
>
> Hi Stanley,
>
> On 15/12/21 03:57, Stanley Chu wrote:
> > Add basic support for the Nuvoton NPCM845 BMC.
> >
> > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > ---
> > arch/arm/Kconfig | 9 +
> > arch/arm/Makefile | 1 +
> > arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
> > arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
> > arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
> > arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
> > arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
> > arch/arm/mach-nuvoton/Kconfig | 24 ++
> > arch/arm/mach-nuvoton/Makefile | 1 +
> > arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
> > arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
> > arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
>
> Here ^^^ you setup timer, but it should be a separate driver IMHO. At
> least this is what I've done for imxrt.
> Same goes for clock, there is no clock driver and you setup spi clock
> directly inside the same file with npcm_sysintf_init() while that should
> be part of the clock driver.
>
> Also all defines regarding to clocks and peripherals should go into
> their driver.
>
> > arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
>
> Here you've mixed up the architecture(above) and the board(below) in a
> single patch.
>
> > board/nuvoton/arbel/Kconfig | 18 ++
> > board/nuvoton/arbel/Makefile | 1 +
> > board/nuvoton/arbel/arbel.c | 33 +++
> > include/configs/arbel.h | 54 ++++
>
> arbel should be arbel-evk
>
> I stop here, because there could be big changes if others agree.
>
> Best regards
> --
> Giulio Benetti
> Benetti Engineering sas
>
> > 17 files changed, 924 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
> > create mode 100644 arch/arm/mach-nuvoton/Kconfig
> > create mode 100644 arch/arm/mach-nuvoton/Makefile
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
> > create mode 100644 board/nuvoton/arbel/Kconfig
> > create mode 100644 board/nuvoton/arbel/Makefile
> > create mode 100644 board/nuvoton/arbel/arbel.c
> > create mode 100644 include/configs/arbel.h
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index f7f03837fe..80ec42f6be 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
> > select LINUX_KERNEL_IMAGE_HEADER
> > select XEN_SERIAL
> > select SSCANF
> > +
> > +config ARCH_NPCM
> > + bool "Support Nuvoton SoCs"
> > + select DM
> > + select OF_CONTROL
> > + imply CMD_DM
> > +
> > endchoice
> >
> > config SUPPORT_PASSING_ATAGS
> > @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
> >
> > source "arch/arm/mach-nexell/Kconfig"
> >
> > +source "arch/arm/mach-nuvoton/Kconfig"
> > +
> > source "board/armltd/total_compute/Kconfig"
> >
> > source "board/bosch/shc/Kconfig"
> > diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> > index ad757e982e..29a0250ab6 100644
> > --- a/arch/arm/Makefile
> > +++ b/arch/arm/Makefile
> > @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
> > machine-$(CONFIG_ARCH_ZYNQ) += zynq
> > machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
> > machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
> > +machine-$(CONFIG_ARCH_NPCM) += nuvoton
> >
> > machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
> >
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
> > new file mode 100644
> > index 0000000000..088b536b7b
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
> > @@ -0,0 +1,164 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef _NPCM_CLOCK_H_
> > +#define _NPCM_CLOCK_H_
> > +
> > +#define NPCM_CLK_BA 0xF0801000
> > +enum {
> > + APB1 = 1,
> > + APB2 = 2,
> > + APB3 = 3,
> > + APB4 = 4,
> > + APB5 = 5,
> > + SPI0 = 10,
> > + SPI1 = 11,
> > + SPI3 = 13,
> > + SPIX = 14,
> > +};
> > +
> > +/* Clock Select Register (CLKSEL) */
> > +#define CLKSEL_RCPCKSEL 27
> > +#define CLKSEL_RGSEL 25
> > +#define CLKSEL_GFXMSEL 21
> > +#define CLKSEL_CLKOUTSEL 18
> > +#define CLKSEL_PCICKSEL 16
> > +#define CLKSEL_ADCCKSEL 14
> > +#define CLKSEL_MCCKSEL 12
> > +#define CLKSEL_SUCKSEL 10
> > +#define CLKSEL_UARTCKSEL 8
> > +#define CLKSEL_SDCKSEL 6
> > +#define CLKSEL_PIXCKSEL 4
> > +#define CLKSEL_CPUCKSEL 0
> > +
> > +/* Clock Divider Control Register 1 (CLKDIV1) */
> > +#define CLKDIV1_ADCCKDIV 28
> > +#define CLKDIV1_CLK4DIV 26
> > +#define CLKDIV1_PRE_ADCCKDIV 21
> > +#define CLKDIV1_UARTDIV 16
> > +#define CLKDIV1_MMCCKDIV 11
> > +#define CLKDIV1_SPI3CKDIV 6
> > +#define CLKDIV1_PCICKDIV 2
> > +
> > +/* Clock Divider Control Register 2 (CLKDIV2) */
> > +#define CLKDIV2_APB4CKDIV 30
> > +#define CLKDIV2_APB3CKDIV 28
> > +#define CLKDIV2_APB2CKDIV 26
> > +#define CLKDIV2_APB1CKDIV 24
> > +#define CLKDIV2_APB5CKDIV 22
> > +#define CLKDIV2_CLKOUTDIV 16
> > +#define CLKDIV2_GFXCKDIV 13
> > +#define CLKDIV2_SUCKDIV 8
> > +#define CLKDIV2_SU48CKDIV 4
> > +
> > +/* PLL Control Register 2 (PLLCON2) */
> > +#define PLLCON_LOKI 31
> > +#define PLLCON_LOKS 30
> > +#define PLLCON_FBDV 16
> > +#define PLLCON_OTDV2 13
> > +#define PLLCON_PWDEN 12
> > +#define PLLCON_OTDV1 8
> > +#define PLLCON_INDV 0
> > +
> > +/* CPUCKSEL (CPU/AMBA/MC Clock Source Select Bit) */
> > +#define CLKSEL_CPUCKSEL_PLL0 0x00 /* 0 0: PLL0 clock*/
> > +#define CLKSEL_CPUCKSEL_PLL1 0x01 /* 0 1: PLL1 clock */
> > +#define CLKSEL_CPUCKSEL_CLKREF 0x02 /* 1 0: CLKREF input (25 MHZ, default) */
> > +#define CLKSEL_CPUCKSEL_SYSBPCK 0x03 /* 1 1: Bypass clock from pin SYSBPCK */
> > +
> > +/* UARTCKSEL (Core and Host UART Clock Source Select Bit). */
> > +#define CLKSEL_UARTCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> > +#define CLKSEL_UARTCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> > +#define CLKSEL_UARTCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> > +#define CLKSEL_UARTCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> > +
> > +/* SDCKSEL (SDHC Clock Source Select Bit). */
> > +#define CLKSEL_SDCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> > +#define CLKSEL_SDCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> > +#define CLKSEL_SDCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> > +#define CLKSEL_SDCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> > +
> > +/* IP Software Reset Register 1 (IPSRST1), offset 0x20 */
> > +#define IPSRST1_USBDEV1 5
> > +#define IPSRST1_USBDEV2 8
> > +#define IPSRST1_USBDEV3 25
> > +#define IPSRST1_USBDEV4 22
> > +#define IPSRST1_USBDEV5 23
> > +#define IPSRST1_USBDEV6 24
> > +#define IPSRST1_GMAC4 21
> > +#define IPSRST1_GMAC3 6
> > +
> > +/* IP Software Reset Register 2 (IPSRST2), offset 0x24 */
> > +#define IPSRST2_GMAC1 28
> > +#define IPSRST2_GMAC2 25
> > +#define IPSRST2_USBHOST1 26
> > +#define IPSRST2_SDHC 9
> > +#define IPSRST2_MMC 8
> > +
> > +/* IP Software Reset Register 3 (IPSRST3), offset 0x34 */
> > +#define IPSRST3_USBPHY1 24
> > +#define IPSRST3_USBPHY2 25
> > +#define IPSRST3_USBHUB 8
> > +#define IPSRST3_USBDEV9 7
> > +#define IPSRST3_USBDEV8 6
> > +#define IPSRST3_USBDEV7 5
> > +#define IPSRST3_USBDEV0 4
> > +
> > +/* IP Software Reset Register 4 (IPSRST4), offset 0x74 */
> > +#define IPSRST4_USBHOST2 31
> > +#define IPSRST4_USBPHY3 25
> > +
> > +#define EXT_CLOCK_FREQUENCY_KHZ 25 * 1000 * 1UL
> > +#define EXT_CLOCK_FREQUENCY_MHZ 25
> > +
> > +struct clk_ctl {
> > + unsigned int clken1;
> > + unsigned int clksel;
> > + unsigned int clkdiv1;
> > + unsigned int pllcon0;
> > + unsigned int pllcon1;
> > + unsigned int swrstr;
> > + unsigned char res1[0x8];
> > + unsigned int ipsrst1;
> > + unsigned int ipsrst2;
> > + unsigned int clken2;
> > + unsigned int clkdiv2;
> > + unsigned int clken3;
> > + unsigned int ipsrst3;
> > + unsigned int wd0rcr;
> > + unsigned int wd1rcr;
> > + unsigned int wd2rcr;
> > + unsigned int swrstc1;
> > + unsigned int swrstc2;
> > + unsigned int swrstc3;
> > + unsigned int tiprstc;
> > + unsigned int pllcon2;
> > + unsigned int clkdiv3;
> > + unsigned int corstc;
> > + unsigned int pllcong;
> > + unsigned int ahbckfi;
> > + unsigned int seccnt;
> > + unsigned int cntr25m;
> > + unsigned int clken4;
> > + unsigned int ipsrst4;
> > + unsigned int busto;
> > + unsigned int clkdiv4;
> > + unsigned int wd0rcrb;
> > + unsigned int wd1rcrb;
> > + unsigned int wd2rcrb;
> > + unsigned int swrstc1b;
> > + unsigned int swrstc2b;
> > + unsigned int swrstc3b;
> > + unsigned int tiprstcb;
> > + unsigned int corstcb;
> > + unsigned int ipsrstdis1;
> > + unsigned int ipsrstdis2;
> > + unsigned int ipsrstdis3;
> > + unsigned int ipsrstdis4;
> > + unsigned char res2[0x10];
> > + unsigned int thrtl_cnt;
> > +};
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/espi.h b/arch/arm/include/asm/arch-npcm8xx/espi.h
> > new file mode 100644
> > index 0000000000..d4de012b02
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/espi.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +#ifndef _NPCM_ESPI_H_
> > +#define _NPCM_ESPI_H_
> > +
> > +#define NPCM_ESPI_BA 0xF009F000
> > +/* Register offsets */
> > +#define ESPICFG 0x04
> > +#define ESPIHINDP 0x80
> > +
> > +/* Channel Supported */
> > +#define ESPICFG_CHNSUPP_MASK 0x0F
> > +#define ESPICFG_CHNSUPP_SHFT 24
> > +
> > +/* I/O Mode Supported */
> > +#define ESPICFG_IOMODE_SHIFT 8
> > +#define ESPI_IO_MODE_SINGLE_DUAL_QUAD 3
> > +
> > +/* Maximum Frequency Supported */
> > +#define ESPICFG_MAXFREQ_SHIFT 10
> > +#define ESPI_MAX_33_MHZ 2
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> > new file mode 100644
> > index 0000000000..14a4b2dbfb
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> > @@ -0,0 +1,313 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef _NPCM_GCR_H_
> > +#define _NPCM_GCR_H_
> > +
> > +#define NPCM_GCR_BA 0xF0800000
> > +/* On-Chip ARBEL NPCM8XX VERSIONS */
> > +
> > +#define ARBEL_Z1 0x00A35850
> > +#define ARBEL_A1 0x04a35850
> > +#define ARBEL_NPCM845 0x00000000
> > +#define ARBEL_NPCM830 0x00300395
> > +#define ARBEL_NPCM810 0x00000220
> > +
> > +/* Function Lock Register 2 (FLOCKR2) */
> > +#define FLOCKR2_MMCRST 12
> > +#define FLOCKR2_MMCRSTLK 13
> > +#define FLOCKR2_G35DA2P 18
> > +
> > +/* Power-On Setting Register (PWRON) */
> > +#define PWRON_BSPA 4 /* STRAP5 */
> > +#define PWRON_SECEN 7 /* STRAP8 */
> > +
> > +/* Multiple Function Pin Select Register 1 (MFSEL1) */
> > +#define MFSEL1_SIRQSE 31
> > +#define MFSEL1_IOX1SEL 30
> > +#define MFSEL1_HSI2BSEL 29
> > +#define MFSEL1_HSI1BSEL 28
> > +#define MFSEL1_DVH1SEL 27
> > +#define MFSEL1_LPCSEL 26
> > +#define MFSEL1_PECIB 25
> > +#define MFSEL1_GSPISEL 24
> > +#define MFSEL1_SMISEL 22
> > +#define MFSEL1_CLKOSEL 21
> > +#define MFSEL1_DVOSEL 18
> > +#define MFSEL1_KBCICSEL 17
> > +#define MFSEL1_R2MDSEL 16
> > +#define MFSEL1_R2ERRSEL 15
> > +#define MFSEL1_RMII2SEL 14
> > +#define MFSEL1_R1MDSEL 13
> > +#define MFSEL1_R1ERRSEL 12
> > +#define MFSEL1_HSI2ASEL 11
> > +#define MFSEL1_HSI1ASEL 10
> > +#define MFSEL1_BSPSEL 9
> > +#define MFSEL1_SMB2SEL 8
> > +#define MFSEL1_SMB1SEL 7
> > +#define MFSEL1_SMB0SEL 6
> > +#define MFSEL1_HSI2CSEL 5
> > +#define MFSEL1_HSI1CSEL 4
> > +#define MFSEL1_S0CS1SEL 3
> > +#define MFSEL1_SMB5SEL 2
> > +#define MFSEL1_SMB4SEL 1
> > +#define MFSEL1_SMB3SEL 0
> > +
> > +/* Multiple Function Pin Select Register 3 (MFSEL3) */
> > +#define MFSEL3_DVODEDLY 27
> > +#define MFSEL3_DDRDVOSEL 26
> > +#define MFSEL3_MMCCDSEL 25
> > +#define MFSEL3_BU1SEL 24
> > +#define MFSEL3_I3C5SEL 22
> > +#define MFSEL3_WDO2SEL 20
> > +#define MFSEL3_WDO1SEL 19
> > +#define MFSEL3_IOXHSEL 18
> > +#define MFSEL3_PCIEPUSE 17
> > +#define MFSEL3_CLKRUNSEL 16
> > +#define MFSEL3_IOX2SEL 14
> > +#define MFSEL3_PSPISEL 13
> > +#define MFSEL3_MMC8SEL 11
> > +#define MFSEL3_MMCSEL 10
> > +#define MFSEL3_RMII1SEL 9
> > +#define MFSEL3_SMB15SEL 8
> > +#define MFSEL3_SMB14SEL 7
> > +#define MFSEL3_SMB13SEL 6
> > +#define MFSEL3_SMB12SEL 5
> > +#define MFSEL3_SPI1SEL 4
> > +#define MFSEL3_FIN1916SELB 3
> > +#define MFSEL3_SMB7SEL 2
> > +#define MFSEL3_SMB6SEL 1
> > +#define MFSEL3_SCISEL 0
> > +
> > +/* Multiple Function Pin Select Register 4 (MFSEL4) */
> > +#define MFSEL4_SMB11DDC 29
> > +#define MFSEL4_SXCS1SEL 28
> > +#define MFSEL4_SPXSEL 27
> > +#define MFSEL4_RG2SEL 24
> > +#define MFSEL4_RG2MSEL 23
> > +#define MFSEL4_BU2SELB 22
> > +#define MFSEL4_SG1MSEL 21
> > +#define MFSEL4_SP3QSEL 20
> > +#define MFSEL4_S3CS3SEL 19
> > +#define MFSEL4_S3CS2SEL 18
> > +#define MFSEL4_S3CS1SEL 17
> > +#define MFSEL4_SP3SEL 16
> > +#define MFSEL4_SP0QSEL 15
> > +#define MFSEL4_SMB11SEL 14
> > +#define MFSEL4_SMB10SEL 13
> > +#define MFSEL4_SMB9SEL 12
> > +#define MFSEL4_SMB8SEL 11
> > +#define MFSEL4_DBGTRSEL 10
> > +#define MFSEL4_CKRQSEL 9
> > +#define MFSEL4_ESPISEL 8
> > +#define MFSEL4_MMCRSEL 6
> > +#define MFSEL4_SD1PSEL 5
> > +#define MFSEL4_ROSEL 4
> > +#define MFSEL4_ESPIPMESEL 2
> > +#define MFSEL4_BSPASEL 1
> > +#define MFSEL4_JTAG2SEL 0
> > +
> > +/* Multiple Function Pin Select Register 5 (MFSEL5) */
> > +#define MFSEL5_R3OENSEL 14
> > +#define MFSEL5_RMII3SEL 11
> > +#define MFSEL5_R2OENSEL 10
> > +#define MFSEL5_R1OENSEL 9
> > +#define MFSEL5_NSPI1CS3SEL 5
> > +#define MFSEL5_NSPI1CS2SEL 4
> > +#define MFSEL5_SPI1D23SEL 3
> > +#define MFSEL5_NSPI1CS1SEL 0
> > +
> > +/* Multiple Function Pin Select Register 6 (MFSEL6) */
> > +#define MFSEL6_GPIO1836SEL 19
> > +#define MFSEL6_FM1SEL 17
> > +
> > +/* Multiple Function Pin Select Register 7 (MFSEL7) */
> > +#define MFSEL7_SMB15SELB 27
> > +#define MFSEL7_GPIO1889SEL 25
> > +
> > +/* USB PHY1 Control Register (USB1PHYCTL) */
> > +#define USB1PHYCTL_RS 28
> > +/* USB PHY2 Control Register (USB2PHYCTL) */
> > +#define USB2PHYCTL_RS 28
> > +/* USB PHY2 Control Register (USB3PHYCTL) */
> > +#define USB3PHYCTL_RS 28
> > +
> > +/* Integration Control Register (INTCR) */
> > +#define INTCR_DUDKSMOD 30
> > +#define INTCR_DDC3I 29
> > +#define INTCR_KVMSI 28
> > +#define INTCR_DEHS 27
> > +#define INTCR_GGPCT2_0 24
> > +#define INTCR_SGC2 23
> > +#define INTCR_DSNS_TRIG 21
> > +#define INTCR_DAC_SNS 20
> > +#define INTCR_SGC1 19
> > +#define INTCR_LDDRB 18
> > +#define INTCR_GIRST 17
> > +#define INTCR_DUDKSEN 16
> > +#define INTCR_DACOFF 15
> > +#define INTCR_DACSEL 14
> > +#define INTCR_GFXINT 12
> > +#define INTCR_DACOSOVR 10
> > +#define INTCR_GFXIFDIS 8
> > +#define INTCR_H2RQDIS 9
> > +#define INTCR_H2DISPOFF 8
> > +#define INTCR_GFXINT2 7
> > +#define INTCR_VGAIOEN 6
> > +#define INTCR_PSPIFEN 4
> > +#define INTCR_HIFEN 3
> > +#define INTCR_SMBFEN 2
> > +#define INTCR_MFTFEN 1
> > +#define INTCR_KCSRST_MODE 0
> > +
> > +/* Integration Control Register (INTCR2) */
> > +#define INTCR2_WDC 21
> > +
> > +/* Integration Control Register (INTCR3) */
> > +#define INTCR3_USBLPBK2 31 /* USB loop-backed HOST 1/2 */
> > +#define INTCR3_USBLPBK 24 /* USB loop-backed mode on/off */
> > +#define INTCR3_USBPHY3SW 14 /* 2 bits */
> > +#define INTCR3_USBPHY2SW 12 /* 2 bits */
> > +#define INTCR3_USBPPS 6
> > +#define INTCR3_UHUB_RWUD 5
> > +
> > +/* Integration Control Register (INTCR4) */
> > +#define INTCR4_GMMAP1 24
> > +#define INTCR4_GMMAP0 16
> > +#define INTCR4_R3EN 14
> > +#define INTCR4_R2EN 13
> > +#define INTCR4_R1EN 12
> > +#define INTCR4_RGMIIREF 6
> > +
> > +/* I2C Segment Pin Select Register (I2CSEGSEL) */
> > +#define I2CSEGSEL_S0DECFG 3
> > +#define I2CSEGSEL_S4DECFG 17
> > +
> > +/* I2C Segment Control Register (I2CSEGCTL) */
> > +#define I2CSEGCTL_S0DEN 20
> > +#define I2CSEGCTL_S0DWE 21
> > +#define I2CSEGCTL_S4DEN 24
> > +#define I2CSEGCTL_S4DWE 25
> > +#define I2CSEGCTL_INIT_VAL 0x9333F000
> > +
> > +struct npcm_gcr {
> > + unsigned int pdid;
> > + unsigned int pwron;
> > + unsigned int swstrps;
> > + unsigned int rsvd1[2];
> > + unsigned int miscpe;
> > + unsigned int spldcnt;
> > + unsigned int rsvd2[1];
> > + unsigned int flockr2;
> > + unsigned int flockr3;
> > + unsigned int rsvd3[3];
> > + unsigned int a35_mode;
> > + unsigned int spswc;
> > + unsigned int intcr;
> > + unsigned int intsr;
> > + unsigned int obscr1;
> > + unsigned int obsdr1;
> > + unsigned int rsvd4[1];
> > + unsigned int hifcr;
> > + unsigned int rsvd5[3];
> > + unsigned int intcr2;
> > + unsigned int rsvd6[1];
> > + unsigned int srcnt;
> > + unsigned int ressr;
> > + unsigned int rlockr1;
> > + unsigned int flockr1;
> > + unsigned int dscnt;
> > + unsigned int mdlr;
> > + unsigned int scrpad_c;
> > + /* scrpad_b: holds the active dram size (value set by bootblock) */
> > + unsigned int scrpad_b;
> > + unsigned int rsvd7[4];
> > + unsigned int daclvlr;
> > + unsigned int intcr3;
> > + unsigned int pcirctl;
> > + unsigned int rsvd8[2];
> > + unsigned int vsintr;
> > + unsigned int rsvd9[1];
> > + unsigned int sd2sur1;
> > + unsigned int sd2sur2;
> > + unsigned int sd2irv3;
> > + unsigned int intcr4;
> > + unsigned int obscr2;
> > + unsigned int obsdr2;
> > + unsigned int rsvd10[5];
> > + unsigned int i2csegsel;
> > + unsigned int i2csegctl;
> > + unsigned int vsrcr;
> > + unsigned int mlockr;
> > + unsigned int rsvd11[8];
> > + unsigned int etsr;
> > + unsigned int dft1r;
> > + unsigned int dft2r;
> > + unsigned int dft3r;
> > + unsigned int edffsr;
> > + unsigned int rsvd12[1];
> > + unsigned int intcrpce3;
> > + unsigned int intcrpce2;
> > + unsigned int intcrpce0;
> > + unsigned int intcrpce1;
> > + unsigned int dactest;
> > + unsigned int scrpad;
> > + unsigned int usb1phyctl;
> > + unsigned int usb2phyctl;
> > + unsigned int usb3phyctl;
> > + unsigned int intsr2;
> > + unsigned int intcrpce2b;
> > + unsigned int intcrpce0b;
> > + unsigned int intcrpce1b;
> > + unsigned int intcrpce3b;
> > + unsigned int rsvd13[4];
> > + unsigned int intcrpce2c;
> > + unsigned int intcrpce0c;
> > + unsigned int intcrpce1c;
> > + unsigned int intcrpce3c;
> > + unsigned int rsvd14[40];
> > + unsigned int sd2irv4;
> > + unsigned int sd2irv5;
> > + unsigned int sd2irv6;
> > + unsigned int sd2irv7;
> > + unsigned int sd2irv8;
> > + unsigned int sd2irv9;
> > + unsigned int sd2irv10;
> > + unsigned int sd2irv11;
> > + unsigned int rsvd15[8];
> > + unsigned int mfsel1;
> > + unsigned int mfsel2;
> > + unsigned int mfsel3;
> > + unsigned int mfsel4;
> > + unsigned int mfsel5;
> > + unsigned int mfsel6;
> > + unsigned int mfsel7;
> > + unsigned int rsvd16[1];
> > + unsigned int mfsel_lk1;
> > + unsigned int mfsel_lk2;
> > + unsigned int mfsel_lk3;
> > + unsigned int mfsel_lk4;
> > + unsigned int mfsel_lk5;
> > + unsigned int mfsel_lk6;
> > + unsigned int mfsel_lk7;
> > + unsigned int rsvd17[1];
> > + unsigned int mfsel_set1;
> > + unsigned int mfsel_set2;
> > + unsigned int mfsel_set3;
> > + unsigned int mfsel_set4;
> > + unsigned int mfsel_set5;
> > + unsigned int mfsel_set6;
> > + unsigned int mfsel_set7;
> > + unsigned int rsvd18[1];
> > + unsigned int mfsel_clr1;
> > + unsigned int mfsel_clr2;
> > + unsigned int mfsel_clr3;
> > + unsigned int mfsel_clr4;
> > + unsigned int mfsel_clr5;
> > + unsigned int mfsel_clr6;
> > + unsigned int mfsel_clr7;
> > + };
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/gpio.h b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> > new file mode 100644
> > index 0000000000..234a1d3de9
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> > @@ -0,0 +1,11 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef _NPCM_GPIO_H_
> > +#define _NPCM_GPIO_H_
> > +
> > +#define NPCM_GPIO_BA 0xF0010000
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
> > new file mode 100644
> > index 0000000000..ffaff50fe2
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
> > @@ -0,0 +1,32 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +#ifndef _NPCM_RST_H_
> > +#define _NPCM_RST_H_
> > +
> > +enum reset_type {
> > + PORST_TYPE = 0x01,
> > + CORST_TYPE = 0x02,
> > + WD0RST_TYPE = 0x03,
> > + SWR1ST_TYPE = 0x04,
> > + SWR2ST_TYPE = 0x05,
> > + SWR3ST_TYPE = 0x06,
> > + SWR4ST_TYPE = 0x07,
> > + WD1RST_TYPE = 0x08,
> > + WD2RST_TYPE = 0x09,
> > + UNKNOWN_TYPE = 0x10,
> > +};
> > +
> > +#define PORST 0x80000000
> > +#define CORST 0x40000000
> > +#define WD0RST 0x20000000
> > +#define SWR1ST 0x10000000
> > +#define SWR2ST 0x08000000
> > +#define SWR3ST 0x04000000
> > +#define SWR4ST 0x02000000
> > +#define WD1RST 0x01000000
> > +#define WD2RST 0x00800000
> > +#define RESSR_MASK 0xff800000
> > +
> > +enum reset_type npcm8xx_reset_reason(void);
> > +
> > +#endif
> > diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig
> > new file mode 100644
> > index 0000000000..e014dd4b79
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/Kconfig
> > @@ -0,0 +1,24 @@
> > +if ARCH_NPCM
> > +
> > +config SYS_ARCH
> > + default "arm"
> > +
> > +config SYS_TEXT_BASE
> > + default 0x8000
> > +
> > +choice
> > + prompt "Nuvoton SoC select"
> > + default ARCH_NPCM8XX
> > +
> > +config ARCH_NPCM8XX
> > + bool "Support Nuvoton NPCM8xx SoC"
> > + select ARM64
> > + help
> > + General support for NPCM8xx BMC (Arbel).
> > + Nuvoton NPCM8xx BMC is based on the Cortex A35.
> > +
> > +endchoice
> > +
> > +source "arch/arm/mach-nuvoton/npcm8xx/Kconfig"
> > +
> > +endif
> > diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile
> > new file mode 100644
> > index 0000000000..e75689a1a0
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/Kconfig b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> > new file mode 100644
> > index 0000000000..478a046ad5
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> > @@ -0,0 +1,18 @@
> > +if ARCH_NPCM8XX
> > +
> > +config SYS_CPU
> > + default "armv8"
> > +
> > +config SYS_SOC
> > + default "npcm8xx"
> > +
> > +config TARGET_ARBEL_EVB
> > + bool "Arbel-EVB"
> > + help
> > + ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
> > + supports general functions of Basebase Management Controller
> > + (BMC).
> > +
> > +source "board/nuvoton/arbel/Kconfig"
> > +
> > +endif
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/Makefile b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> > new file mode 100644
> > index 0000000000..c62a4aa20a
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> > @@ -0,0 +1 @@
> > +obj-y += reset.o cpu.o
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/cpu.c b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> > new file mode 100644
> > index 0000000000..8a7315d535
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> > @@ -0,0 +1,170 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <cpu_func.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/gcr.h>
> > +#include <asm/arch/espi.h>
> > +#include <asm/armv8/mmu.h>
> > +#include <asm/system.h>
> > +#include <asm/global_data.h>
> > +
> > +/* System Counter */
> > +struct sctr_regs {
> > + u32 cntcr;
> > + u32 cntsr;
> > + u32 cntcv1;
> > + u32 cntcv2;
> > + u32 resv1[4];
> > + u32 cntfid0;
> > + u32 cntfid1;
> > + u32 cntfid2;
> > + u32 resv2[1001];
> > + u32 counterid[1];
> > +};
> > +
> > +#define SC_CNTCR_ENABLE BIT(0)
> > +#define SC_CNTCR_HDBG BIT(1)
> > +#define SC_CNTCR_FREQ0 BIT(8)
> > +#define SC_CNTCR_FREQ1 BIT(9)
> > +
> > +#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int print_cpuinfo(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > + unsigned int id = 0;
> > + unsigned long mpidr_val = 0;
> > + unsigned int mdlr = 0;
> > +
> > + asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
> > +
> > + mdlr = readl(&gcr->mdlr);
> > +
> > + printf("CPU-%d: ", (unsigned int)(mpidr_val & 0x3));
> > +
> > + switch (mdlr) {
> > + case ARBEL_NPCM845:
> > + printf("NPCM845 ");
> > + break;
> > + case ARBEL_NPCM830:
> > + printf("NPCM830 ");
> > + break;
> > + case ARBEL_NPCM810:
> > + printf("NPCM810 ");
> > + break;
> > + default:
> > + printf("NPCM8XX ");
> > + break;
> > + }
> > +
> > + id = readl(&gcr->pdid);
> > + switch (id) {
> > + case ARBEL_Z1:
> > + printf("Z1 @ ");
> > + break;
> > + case ARBEL_A1:
> > + printf("A1 @ ");
> > + break;
> > + default:
> > + printf("Unknown\n");
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void npcm_sysintf_init(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > + u32 espi_ch_supp, val;
> > +
> > + espi_ch_supp = ofnode_conf_read_int("espi-channel-support", 0);
> > +
> > + if (espi_ch_supp) {
> > + /* Use eSPI function and initialize ESPICFG */
> > + u32 hindp = 0x00011110 | espi_ch_supp;
> > +
> > + writel((readl(&gcr->mfsel4) | (1 << MFSEL4_ESPISEL)), &gcr->mfsel4);
> > + writel(hindp, NPCM_ESPI_BA + ESPIHINDP);
> > + val = readl(NPCM_ESPI_BA + ESPICFG);
> > + val |= ESPI_IO_MODE_SINGLE_DUAL_QUAD << ESPICFG_IOMODE_SHIFT;
> > + val |= ESPI_MAX_33_MHZ << ESPICFG_MAXFREQ_SHIFT;
> > + val |= ((espi_ch_supp & ESPICFG_CHNSUPP_MASK) << ESPICFG_CHNSUPP_SHFT);
> > + writel(val, NPCM_ESPI_BA + ESPICFG);
> > + } else {
> > + /* Use LPC function */
> > + writel((readl(&gcr->mfsel1) | (1 << MFSEL1_LPCSEL)), &gcr->mfsel1);
> > + }
> > +}
> > +
> > +int arch_cpu_init(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > +
> > + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
> > + /* enable cache to speed up system running */
> > + if (get_sctlr() & CR_M)
> > + return 0;
> > +
> > + icache_enable();
> > + __asm_invalidate_dcache_all();
> > + __asm_invalidate_tlb_all();
> > + set_sctlr(get_sctlr() | CR_C);
> > + }
> > +
> > + /* Power voltage select setup */
> > + setbits_le32(&gcr->vsrcr, BIT(30));
> > +
> > + npcm_sysintf_init();
> > +
> > + return 0;
> > +}
> > +
> > +static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
> > + {
> > + /* DRAM */
> > + .phys = 0x0UL,
> > + .virt = 0x0UL,
> > + .size = 0x80000000UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > + PTE_BLOCK_INNER_SHARE
> > + },
> > + {
> > + .phys = 0x80000000UL,
> > + .virt = 0x80000000UL,
> > + .size = 0x80000000UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > + PTE_BLOCK_NON_SHARE |
> > + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > + },
> > + {
> > + /* List terminator */
> > + 0,
> > + }
> > +};
> > +
> > +struct mm_region *mem_map = npcm_mem_map;
> > +
> > +int timer_init(void)
> > +{
> > + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
> > + unsigned int cntfrq_el0;
> > +
> > + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
> > + writel(cntfrq_el0, &sctr->cntfid0);
> > +
> > + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
> > + SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
> > +
> > + gd->arch.tbl = 0;
> > + gd->arch.tbu = 0;
> > +
> > + return 0;
> > +}
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/reset.c b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> > new file mode 100644
> > index 0000000000..7fbed7ba76
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> > @@ -0,0 +1,51 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/rst.h>
> > +#include <asm/arch/gcr.h>
> > +
> > +void reset_cpu(void)
> > +{
> > + /* Watcdog reset - WTCR register set WTE-BIT7 WTRE-BIT1 WTR-BIT0 */
> > + writel(0x83, 0xf000801c);
> > +
> > + while (1)
> > + ;
> > +}
> > +
> > +void reset_misc(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > +
> > + /* clear WDC */
> > + writel(readl(&gcr->intcr2) & ~(1 << INTCR2_WDC), &gcr->intcr2);
> > +}
> > +
> > +enum reset_type npcm8xx_reset_reason(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > + enum reset_type type = UNKNOWN_TYPE;
> > + u32 value = readl(&gcr->ressr);
> > +
> > + if (value == 0)
> > + value = ~readl(&gcr->intcr2);
> > +
> > + value &= RESSR_MASK;
> > +
> > + if (value & CORST)
> > + type = CORST;
> > + if (value & WD0RST)
> > + type = WD0RST;
> > + if (value & WD1RST)
> > + type = WD1RST;
> > + if (value & WD2RST)
> > + type = WD2RST;
> > + if (value & PORST)
> > + type = PORST;
> > +
> > + return type;
> > +}
> > diff --git a/board/nuvoton/arbel/Kconfig b/board/nuvoton/arbel/Kconfig
> > new file mode 100644
> > index 0000000000..4a03ea1abf
> > --- /dev/null
> > +++ b/board/nuvoton/arbel/Kconfig
> > @@ -0,0 +1,18 @@
> > +if TARGET_ARBEL_EVB
> > +
> > +config SYS_BOARD
> > + default "arbel"
> > +
> > +config SYS_VENDOR
> > + default "nuvoton"
> > +
> > +config SYS_CONFIG_NAME
> > + default "arbel"
> > +
> > +config SYS_MEM_TOP_HIDE
> > + hex "Reserved TOP memory"
> > + default 0xB000000
> > + help
> > + Reserve memory for ECC/GFX/VCD/ECE.
> > +
> > +endif
> > diff --git a/board/nuvoton/arbel/Makefile b/board/nuvoton/arbel/Makefile
> > new file mode 100644
> > index 0000000000..f9ad1dea34
> > --- /dev/null
> > +++ b/board/nuvoton/arbel/Makefile
> > @@ -0,0 +1 @@
> > +obj-y += arbel.o
> > diff --git a/board/nuvoton/arbel/arbel.c b/board/nuvoton/arbel/arbel.c
> > new file mode 100644
> > index 0000000000..86cef98c5f
> > --- /dev/null
> > +++ b/board/nuvoton/arbel/arbel.c
> > @@ -0,0 +1,33 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/gcr.h>
> > +#include <asm/mach-types.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int board_init(void)
> > +{
> > + gd->bd->bi_arch_number = MACH_TYPE_NPCMX50;
> > + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100UL);
> > +
> > + return 0;
> > +}
> > +
> > +int dram_init(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > +
> > + /*
> > + * get dram active size value from bootblock.
> > + * Value sent using scrpad_02 register.
> > + */
> > + gd->ram_size = readl(&gcr->scrpad_b);
> > +
> > + return 0;
> > +}
> > diff --git a/include/configs/arbel.h b/include/configs/arbel.h
> > new file mode 100644
> > index 0000000000..2cb658c3e6
> > --- /dev/null
> > +++ b/include/configs/arbel.h
> > @@ -0,0 +1,54 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef __CONFIG_ARBEL_H
> > +#define __CONFIG_ARBEL_H
> > +
> > +#define CONFIG_GICV2
> > +#define GICD_BASE (0xDFFF9000)
> > +#define GICC_BASE (0xDFFFA000)
> > +
> > +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
> > +#define CONFIG_USB_OHCI_NEW
> > +#define CONFIG_SETUP_MEMORY_TAGS
> > +#define CONFIG_INITRD_TAG
> > +#define CONFIG_SYS_MAXARGS 32
> > +#define CONFIG_SYS_CBSIZE 256
> > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > +#define CONFIG_SYS_BOOTM_LEN (20 << 20)
> > +#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
> > +#define CONFIG_SYS_SDRAM_BASE 0x0
> > +#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
> > +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
> > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> > +#define CONFIG_BAUDRATE 115200
> > +#define CONFIG_SYS_HZ 1000
> > +#define CONFIG_BITBANGMII_MULTI
> > +
> > +/* Default environemnt variables */
> > +#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot"
> > +#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
> > + "stdin=serial\0" \
> > + "stdout=serial\0" \
> > + "stderr=serial\0" \
> > + "ethact=gmac1\0" \
> > + "autostart=no\0" \
> > + "ethaddr=00:00:F7:A0:00:FC\0" \
> > + "eth1addr=00:00:F7:A0:00:FD\0" \
> > + "eth2addr=00:00:F7:A0:00:FE\0" \
> > + "eth3addr=00:00:F7:A0:00:FF\0" \
> > + "gatewayip=192.168.0.17\0" \
> > + "serverip=192.168.0.17\0" \
> > + "ipaddr=192.168.0.15\0" \
> > + "romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
> > + "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
> > + "earlycon=uart8250,mmio32,0xf0000000\0" \
> > + "console=ttyS0,115200n8\0" \
> > + "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
> > + "console=${console} ramdisk_size=48000\0" \
> > + "\0"
> > +
> > +#endif
> >
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2021-12-15 18:32 ` Sean Anderson
@ 2022-03-11 0:55 ` Stanley Chu
[not found] ` <d23d2925-d5ea-e23b-fb99-7856aedfb328@gmail.com>
1 sibling, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2022-03-11 0:55 UTC (permalink / raw)
To: Sean Anderson, Tom Rini, Stanley Chu; +Cc: u-boot, kwliu, ctcchien
Hi Sean,
Thank you for your comment, I've submitted a clk driver patch to address this.
https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-yschu@nuvoton.com/
As for the reset controller, I will take reset-syscon driver for that.
--
Stanley
On Thu, Dec 16, 2021 at 2:32 AM Sean Anderson <seanga2@gmail.com> wrote:
>
> On 12/14/21 9:57 PM, Stanley Chu wrote:
> > Add basic support for the Nuvoton NPCM845 BMC.
> >
> > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> > ---
> > arch/arm/Kconfig | 9 +
> > arch/arm/Makefile | 1 +
> > arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
> > arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
> > arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
> > arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
> > arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
> > arch/arm/mach-nuvoton/Kconfig | 24 ++
> > arch/arm/mach-nuvoton/Makefile | 1 +
> > arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
> > arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
> > arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
> > arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
> > board/nuvoton/arbel/Kconfig | 18 ++
> > board/nuvoton/arbel/Makefile | 1 +
> > board/nuvoton/arbel/arbel.c | 33 +++
> > include/configs/arbel.h | 54 ++++
> > 17 files changed, 924 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
> > create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
> > create mode 100644 arch/arm/mach-nuvoton/Kconfig
> > create mode 100644 arch/arm/mach-nuvoton/Makefile
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
> > create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
> > create mode 100644 board/nuvoton/arbel/Kconfig
> > create mode 100644 board/nuvoton/arbel/Makefile
> > create mode 100644 board/nuvoton/arbel/arbel.c
> > create mode 100644 include/configs/arbel.h
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index f7f03837fe..80ec42f6be 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
> > select LINUX_KERNEL_IMAGE_HEADER
> > select XEN_SERIAL
> > select SSCANF
> > +
> > +config ARCH_NPCM
> > + bool "Support Nuvoton SoCs"
> > + select DM
> > + select OF_CONTROL
> > + imply CMD_DM
> > +
> > endchoice
> >
> > config SUPPORT_PASSING_ATAGS
> > @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
> >
> > source "arch/arm/mach-nexell/Kconfig"
> >
> > +source "arch/arm/mach-nuvoton/Kconfig"
> > +
> > source "board/armltd/total_compute/Kconfig"
> >
> > source "board/bosch/shc/Kconfig"
> > diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> > index ad757e982e..29a0250ab6 100644
> > --- a/arch/arm/Makefile
> > +++ b/arch/arm/Makefile
> > @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
> > machine-$(CONFIG_ARCH_ZYNQ) += zynq
> > machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
> > machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
> > +machine-$(CONFIG_ARCH_NPCM) += nuvoton
> >
> > machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
> >
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
> > new file mode 100644
> > index 0000000000..088b536b7b
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
>
> Please add this (and all the other includes) in the patches adding the
> drivers which use them. This makes it much easier to review.
>
> Additionally, if these defines are not used elsewhere, they can be
> included at the beginning of the clock driver itself.
>
> > @@ -0,0 +1,164 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef _NPCM_CLOCK_H_
> > +#define _NPCM_CLOCK_H_
> > +
> > +#define NPCM_CLK_BA 0xF0801000
> > +enum {
>
> Don't redefine these. Just use include/dt-bindings/clock/npcm845-clock.h
>
> > + APB1 = 1,
> > + APB2 = 2,
> > + APB3 = 3,
> > + APB4 = 4,
> > + APB5 = 5,
> > + SPI0 = 10,
> > + SPI1 = 11,
> > + SPI3 = 13,
> > + SPIX = 14,
> > +};
> > +
> > +/* Clock Select Register (CLKSEL) */
> > +#define CLKSEL_RCPCKSEL 27
> > +#define CLKSEL_RGSEL 25
> > +#define CLKSEL_GFXMSEL 21
> > +#define CLKSEL_CLKOUTSEL 18
> > +#define CLKSEL_PCICKSEL 16
> > +#define CLKSEL_ADCCKSEL 14
> > +#define CLKSEL_MCCKSEL 12
> > +#define CLKSEL_SUCKSEL 10
> > +#define CLKSEL_UARTCKSEL 8
> > +#define CLKSEL_SDCKSEL 6
> > +#define CLKSEL_PIXCKSEL 4
> > +#define CLKSEL_CPUCKSEL 0
>
> Please use GENMASK for this. For example,
>
> #define CLKSEL_CPUCKSEL GENMASK(1, 0)
>
> This allows you to do things like
>
> u32 clksel = readl(®s->clksel);
>
> switch (FIELD_GET(CLKSEL_CPUCKSEL, clksel)) {
>
> }
>
> later on, instead of having magic masks everywhere.
>
> > +
> > +/* Clock Divider Control Register 1 (CLKDIV1) */
> > +#define CLKDIV1_ADCCKDIV 28
> > +#define CLKDIV1_CLK4DIV 26
> > +#define CLKDIV1_PRE_ADCCKDIV 21
> > +#define CLKDIV1_UARTDIV 16
> > +#define CLKDIV1_MMCCKDIV 11
> > +#define CLKDIV1_SPI3CKDIV 6
> > +#define CLKDIV1_PCICKDIV 2
> > +
> > +/* Clock Divider Control Register 2 (CLKDIV2) */
> > +#define CLKDIV2_APB4CKDIV 30
> > +#define CLKDIV2_APB3CKDIV 28
> > +#define CLKDIV2_APB2CKDIV 26
> > +#define CLKDIV2_APB1CKDIV 24
> > +#define CLKDIV2_APB5CKDIV 22
> > +#define CLKDIV2_CLKOUTDIV 16
> > +#define CLKDIV2_GFXCKDIV 13
> > +#define CLKDIV2_SUCKDIV 8
> > +#define CLKDIV2_SU48CKDIV 4
> > +
> > +/* PLL Control Register 2 (PLLCON2) */
> > +#define PLLCON_LOKI 31
> > +#define PLLCON_LOKS 30
> > +#define PLLCON_FBDV 16
> > +#define PLLCON_OTDV2 13
> > +#define PLLCON_PWDEN 12
> > +#define PLLCON_OTDV1 8
> > +#define PLLCON_INDV 0
> > +
> > +/* CPUCKSEL (CPU/AMBA/MC Clock Source Select Bit) */
> > +#define CLKSEL_CPUCKSEL_PLL0 0x00 /* 0 0: PLL0 clock*/
> > +#define CLKSEL_CPUCKSEL_PLL1 0x01 /* 0 1: PLL1 clock */
> > +#define CLKSEL_CPUCKSEL_CLKREF 0x02 /* 1 0: CLKREF input (25 MHZ, default) */
> > +#define CLKSEL_CPUCKSEL_SYSBPCK 0x03 /* 1 1: Bypass clock from pin SYSBPCK */
> > +
> > +/* UARTCKSEL (Core and Host UART Clock Source Select Bit). */
> > +#define CLKSEL_UARTCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> > +#define CLKSEL_UARTCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> > +#define CLKSEL_UARTCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> > +#define CLKSEL_UARTCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> > +
> > +/* SDCKSEL (SDHC Clock Source Select Bit). */
> > +#define CLKSEL_SDCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
> > +#define CLKSEL_SDCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
> > +#define CLKSEL_SDCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
> > +#define CLKSEL_SDCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
> > +
> > +/* IP Software Reset Register 1 (IPSRST1), offset 0x20 */
>
> If you have multiple logical devices in one group of registers, you
> should look into organizing your bindings like
>
> syscon@0xf0801000 {
> compatible = "simple-mfd";
> reg = <0x0 0xf0801000 0x0 0x70>;
>
> clks: clock-controller {
> compatible = "nuvoton,npcm845-clock";
> #clock-cells = <1>;
> clocks = <&some_oscillator>;
> clock-names = "extclk";
> u-boot,dm-pre-reloc;
> };
>
> rsts: reset-controller {
> compatible = "nuvoton,npcm845-reset";
> #reset-cells = <1>;
> }
> }
>
> > +#define IPSRST1_USBDEV1 5
> > +#define IPSRST1_USBDEV2 8
> > +#define IPSRST1_USBDEV3 25
> > +#define IPSRST1_USBDEV4 22
> > +#define IPSRST1_USBDEV5 23
> > +#define IPSRST1_USBDEV6 24
> > +#define IPSRST1_GMAC4 21
> > +#define IPSRST1_GMAC3 6
> > +
> > +/* IP Software Reset Register 2 (IPSRST2), offset 0x24 */
> > +#define IPSRST2_GMAC1 28
> > +#define IPSRST2_GMAC2 25
> > +#define IPSRST2_USBHOST1 26
> > +#define IPSRST2_SDHC 9
> > +#define IPSRST2_MMC 8
> > +
> > +/* IP Software Reset Register 3 (IPSRST3), offset 0x34 */
> > +#define IPSRST3_USBPHY1 24
> > +#define IPSRST3_USBPHY2 25
> > +#define IPSRST3_USBHUB 8
> > +#define IPSRST3_USBDEV9 7
> > +#define IPSRST3_USBDEV8 6
> > +#define IPSRST3_USBDEV7 5
> > +#define IPSRST3_USBDEV0 4
> > +
> > +/* IP Software Reset Register 4 (IPSRST4), offset 0x74 */
> > +#define IPSRST4_USBHOST2 31
> > +#define IPSRST4_USBPHY3 25
> > +
> > +#define EXT_CLOCK_FREQUENCY_KHZ 25 * 1000 * 1UL
> > +#define EXT_CLOCK_FREQUENCY_MHZ 25
>
> Just define it in HZ and divide it as needed. The compiler will optimize
> it. But see also my comments on your other patch.
>
> > +
> > +struct clk_ctl {
>
> Please name this npcm_clk_ctl or similar.
>
> > + unsigned int clken1;
>
> Please use u32/u64 as the case may be.
>
> --Sean
>
> > + unsigned int clksel;
> > + unsigned int clkdiv1;
> > + unsigned int pllcon0;
> > + unsigned int pllcon1;
> > + unsigned int swrstr;
> > + unsigned char res1[0x8];
> > + unsigned int ipsrst1;
> > + unsigned int ipsrst2;
> > + unsigned int clken2;
> > + unsigned int clkdiv2;
> > + unsigned int clken3;
> > + unsigned int ipsrst3;
> > + unsigned int wd0rcr;
> > + unsigned int wd1rcr;
> > + unsigned int wd2rcr;
> > + unsigned int swrstc1;
> > + unsigned int swrstc2;
> > + unsigned int swrstc3;
> > + unsigned int tiprstc;
> > + unsigned int pllcon2;
> > + unsigned int clkdiv3;
> > + unsigned int corstc;
> > + unsigned int pllcong;
> > + unsigned int ahbckfi;
> > + unsigned int seccnt;
> > + unsigned int cntr25m;
> > + unsigned int clken4;
> > + unsigned int ipsrst4;
> > + unsigned int busto;
> > + unsigned int clkdiv4;
> > + unsigned int wd0rcrb;
> > + unsigned int wd1rcrb;
> > + unsigned int wd2rcrb;
> > + unsigned int swrstc1b;
> > + unsigned int swrstc2b;
> > + unsigned int swrstc3b;
> > + unsigned int tiprstcb;
> > + unsigned int corstcb;
> > + unsigned int ipsrstdis1;
> > + unsigned int ipsrstdis2;
> > + unsigned int ipsrstdis3;
> > + unsigned int ipsrstdis4;
> > + unsigned char res2[0x10];
> > + unsigned int thrtl_cnt;
> > +};
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/espi.h b/arch/arm/include/asm/arch-npcm8xx/espi.h
> > new file mode 100644
> > index 0000000000..d4de012b02
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/espi.h
> > @@ -0,0 +1,23 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +#ifndef _NPCM_ESPI_H_
> > +#define _NPCM_ESPI_H_
> > +
> > +#define NPCM_ESPI_BA 0xF009F000
> > +/* Register offsets */
> > +#define ESPICFG 0x04
> > +#define ESPIHINDP 0x80
> > +
> > +/* Channel Supported */
> > +#define ESPICFG_CHNSUPP_MASK 0x0F
> > +#define ESPICFG_CHNSUPP_SHFT 24
> > +
> > +/* I/O Mode Supported */
> > +#define ESPICFG_IOMODE_SHIFT 8
> > +#define ESPI_IO_MODE_SINGLE_DUAL_QUAD 3
> > +
> > +/* Maximum Frequency Supported */
> > +#define ESPICFG_MAXFREQ_SHIFT 10
> > +#define ESPI_MAX_33_MHZ 2
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> > new file mode 100644
> > index 0000000000..14a4b2dbfb
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
> > @@ -0,0 +1,313 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef _NPCM_GCR_H_
> > +#define _NPCM_GCR_H_
> > +
> > +#define NPCM_GCR_BA 0xF0800000
> > +/* On-Chip ARBEL NPCM8XX VERSIONS */
> > +
> > +#define ARBEL_Z1 0x00A35850
> > +#define ARBEL_A1 0x04a35850
> > +#define ARBEL_NPCM845 0x00000000
> > +#define ARBEL_NPCM830 0x00300395
> > +#define ARBEL_NPCM810 0x00000220
> > +
> > +/* Function Lock Register 2 (FLOCKR2) */
> > +#define FLOCKR2_MMCRST 12
> > +#define FLOCKR2_MMCRSTLK 13
> > +#define FLOCKR2_G35DA2P 18
> > +
> > +/* Power-On Setting Register (PWRON) */
> > +#define PWRON_BSPA 4 /* STRAP5 */
> > +#define PWRON_SECEN 7 /* STRAP8 */
> > +
> > +/* Multiple Function Pin Select Register 1 (MFSEL1) */
> > +#define MFSEL1_SIRQSE 31
> > +#define MFSEL1_IOX1SEL 30
> > +#define MFSEL1_HSI2BSEL 29
> > +#define MFSEL1_HSI1BSEL 28
> > +#define MFSEL1_DVH1SEL 27
> > +#define MFSEL1_LPCSEL 26
> > +#define MFSEL1_PECIB 25
> > +#define MFSEL1_GSPISEL 24
> > +#define MFSEL1_SMISEL 22
> > +#define MFSEL1_CLKOSEL 21
> > +#define MFSEL1_DVOSEL 18
> > +#define MFSEL1_KBCICSEL 17
> > +#define MFSEL1_R2MDSEL 16
> > +#define MFSEL1_R2ERRSEL 15
> > +#define MFSEL1_RMII2SEL 14
> > +#define MFSEL1_R1MDSEL 13
> > +#define MFSEL1_R1ERRSEL 12
> > +#define MFSEL1_HSI2ASEL 11
> > +#define MFSEL1_HSI1ASEL 10
> > +#define MFSEL1_BSPSEL 9
> > +#define MFSEL1_SMB2SEL 8
> > +#define MFSEL1_SMB1SEL 7
> > +#define MFSEL1_SMB0SEL 6
> > +#define MFSEL1_HSI2CSEL 5
> > +#define MFSEL1_HSI1CSEL 4
> > +#define MFSEL1_S0CS1SEL 3
> > +#define MFSEL1_SMB5SEL 2
> > +#define MFSEL1_SMB4SEL 1
> > +#define MFSEL1_SMB3SEL 0
> > +
> > +/* Multiple Function Pin Select Register 3 (MFSEL3) */
> > +#define MFSEL3_DVODEDLY 27
> > +#define MFSEL3_DDRDVOSEL 26
> > +#define MFSEL3_MMCCDSEL 25
> > +#define MFSEL3_BU1SEL 24
> > +#define MFSEL3_I3C5SEL 22
> > +#define MFSEL3_WDO2SEL 20
> > +#define MFSEL3_WDO1SEL 19
> > +#define MFSEL3_IOXHSEL 18
> > +#define MFSEL3_PCIEPUSE 17
> > +#define MFSEL3_CLKRUNSEL 16
> > +#define MFSEL3_IOX2SEL 14
> > +#define MFSEL3_PSPISEL 13
> > +#define MFSEL3_MMC8SEL 11
> > +#define MFSEL3_MMCSEL 10
> > +#define MFSEL3_RMII1SEL 9
> > +#define MFSEL3_SMB15SEL 8
> > +#define MFSEL3_SMB14SEL 7
> > +#define MFSEL3_SMB13SEL 6
> > +#define MFSEL3_SMB12SEL 5
> > +#define MFSEL3_SPI1SEL 4
> > +#define MFSEL3_FIN1916SELB 3
> > +#define MFSEL3_SMB7SEL 2
> > +#define MFSEL3_SMB6SEL 1
> > +#define MFSEL3_SCISEL 0
> > +
> > +/* Multiple Function Pin Select Register 4 (MFSEL4) */
> > +#define MFSEL4_SMB11DDC 29
> > +#define MFSEL4_SXCS1SEL 28
> > +#define MFSEL4_SPXSEL 27
> > +#define MFSEL4_RG2SEL 24
> > +#define MFSEL4_RG2MSEL 23
> > +#define MFSEL4_BU2SELB 22
> > +#define MFSEL4_SG1MSEL 21
> > +#define MFSEL4_SP3QSEL 20
> > +#define MFSEL4_S3CS3SEL 19
> > +#define MFSEL4_S3CS2SEL 18
> > +#define MFSEL4_S3CS1SEL 17
> > +#define MFSEL4_SP3SEL 16
> > +#define MFSEL4_SP0QSEL 15
> > +#define MFSEL4_SMB11SEL 14
> > +#define MFSEL4_SMB10SEL 13
> > +#define MFSEL4_SMB9SEL 12
> > +#define MFSEL4_SMB8SEL 11
> > +#define MFSEL4_DBGTRSEL 10
> > +#define MFSEL4_CKRQSEL 9
> > +#define MFSEL4_ESPISEL 8
> > +#define MFSEL4_MMCRSEL 6
> > +#define MFSEL4_SD1PSEL 5
> > +#define MFSEL4_ROSEL 4
> > +#define MFSEL4_ESPIPMESEL 2
> > +#define MFSEL4_BSPASEL 1
> > +#define MFSEL4_JTAG2SEL 0
> > +
> > +/* Multiple Function Pin Select Register 5 (MFSEL5) */
> > +#define MFSEL5_R3OENSEL 14
> > +#define MFSEL5_RMII3SEL 11
> > +#define MFSEL5_R2OENSEL 10
> > +#define MFSEL5_R1OENSEL 9
> > +#define MFSEL5_NSPI1CS3SEL 5
> > +#define MFSEL5_NSPI1CS2SEL 4
> > +#define MFSEL5_SPI1D23SEL 3
> > +#define MFSEL5_NSPI1CS1SEL 0
> > +
> > +/* Multiple Function Pin Select Register 6 (MFSEL6) */
> > +#define MFSEL6_GPIO1836SEL 19
> > +#define MFSEL6_FM1SEL 17
> > +
> > +/* Multiple Function Pin Select Register 7 (MFSEL7) */
> > +#define MFSEL7_SMB15SELB 27
> > +#define MFSEL7_GPIO1889SEL 25
> > +
> > +/* USB PHY1 Control Register (USB1PHYCTL) */
> > +#define USB1PHYCTL_RS 28
> > +/* USB PHY2 Control Register (USB2PHYCTL) */
> > +#define USB2PHYCTL_RS 28
> > +/* USB PHY2 Control Register (USB3PHYCTL) */
> > +#define USB3PHYCTL_RS 28
> > +
> > +/* Integration Control Register (INTCR) */
> > +#define INTCR_DUDKSMOD 30
> > +#define INTCR_DDC3I 29
> > +#define INTCR_KVMSI 28
> > +#define INTCR_DEHS 27
> > +#define INTCR_GGPCT2_0 24
> > +#define INTCR_SGC2 23
> > +#define INTCR_DSNS_TRIG 21
> > +#define INTCR_DAC_SNS 20
> > +#define INTCR_SGC1 19
> > +#define INTCR_LDDRB 18
> > +#define INTCR_GIRST 17
> > +#define INTCR_DUDKSEN 16
> > +#define INTCR_DACOFF 15
> > +#define INTCR_DACSEL 14
> > +#define INTCR_GFXINT 12
> > +#define INTCR_DACOSOVR 10
> > +#define INTCR_GFXIFDIS 8
> > +#define INTCR_H2RQDIS 9
> > +#define INTCR_H2DISPOFF 8
> > +#define INTCR_GFXINT2 7
> > +#define INTCR_VGAIOEN 6
> > +#define INTCR_PSPIFEN 4
> > +#define INTCR_HIFEN 3
> > +#define INTCR_SMBFEN 2
> > +#define INTCR_MFTFEN 1
> > +#define INTCR_KCSRST_MODE 0
> > +
> > +/* Integration Control Register (INTCR2) */
> > +#define INTCR2_WDC 21
> > +
> > +/* Integration Control Register (INTCR3) */
> > +#define INTCR3_USBLPBK2 31 /* USB loop-backed HOST 1/2 */
> > +#define INTCR3_USBLPBK 24 /* USB loop-backed mode on/off */
> > +#define INTCR3_USBPHY3SW 14 /* 2 bits */
> > +#define INTCR3_USBPHY2SW 12 /* 2 bits */
> > +#define INTCR3_USBPPS 6
> > +#define INTCR3_UHUB_RWUD 5
> > +
> > +/* Integration Control Register (INTCR4) */
> > +#define INTCR4_GMMAP1 24
> > +#define INTCR4_GMMAP0 16
> > +#define INTCR4_R3EN 14
> > +#define INTCR4_R2EN 13
> > +#define INTCR4_R1EN 12
> > +#define INTCR4_RGMIIREF 6
> > +
> > +/* I2C Segment Pin Select Register (I2CSEGSEL) */
> > +#define I2CSEGSEL_S0DECFG 3
> > +#define I2CSEGSEL_S4DECFG 17
> > +
> > +/* I2C Segment Control Register (I2CSEGCTL) */
> > +#define I2CSEGCTL_S0DEN 20
> > +#define I2CSEGCTL_S0DWE 21
> > +#define I2CSEGCTL_S4DEN 24
> > +#define I2CSEGCTL_S4DWE 25
> > +#define I2CSEGCTL_INIT_VAL 0x9333F000
> > +
> > +struct npcm_gcr {
> > + unsigned int pdid;
> > + unsigned int pwron;
> > + unsigned int swstrps;
> > + unsigned int rsvd1[2];
> > + unsigned int miscpe;
> > + unsigned int spldcnt;
> > + unsigned int rsvd2[1];
> > + unsigned int flockr2;
> > + unsigned int flockr3;
> > + unsigned int rsvd3[3];
> > + unsigned int a35_mode;
> > + unsigned int spswc;
> > + unsigned int intcr;
> > + unsigned int intsr;
> > + unsigned int obscr1;
> > + unsigned int obsdr1;
> > + unsigned int rsvd4[1];
> > + unsigned int hifcr;
> > + unsigned int rsvd5[3];
> > + unsigned int intcr2;
> > + unsigned int rsvd6[1];
> > + unsigned int srcnt;
> > + unsigned int ressr;
> > + unsigned int rlockr1;
> > + unsigned int flockr1;
> > + unsigned int dscnt;
> > + unsigned int mdlr;
> > + unsigned int scrpad_c;
> > + /* scrpad_b: holds the active dram size (value set by bootblock) */
> > + unsigned int scrpad_b;
> > + unsigned int rsvd7[4];
> > + unsigned int daclvlr;
> > + unsigned int intcr3;
> > + unsigned int pcirctl;
> > + unsigned int rsvd8[2];
> > + unsigned int vsintr;
> > + unsigned int rsvd9[1];
> > + unsigned int sd2sur1;
> > + unsigned int sd2sur2;
> > + unsigned int sd2irv3;
> > + unsigned int intcr4;
> > + unsigned int obscr2;
> > + unsigned int obsdr2;
> > + unsigned int rsvd10[5];
> > + unsigned int i2csegsel;
> > + unsigned int i2csegctl;
> > + unsigned int vsrcr;
> > + unsigned int mlockr;
> > + unsigned int rsvd11[8];
> > + unsigned int etsr;
> > + unsigned int dft1r;
> > + unsigned int dft2r;
> > + unsigned int dft3r;
> > + unsigned int edffsr;
> > + unsigned int rsvd12[1];
> > + unsigned int intcrpce3;
> > + unsigned int intcrpce2;
> > + unsigned int intcrpce0;
> > + unsigned int intcrpce1;
> > + unsigned int dactest;
> > + unsigned int scrpad;
> > + unsigned int usb1phyctl;
> > + unsigned int usb2phyctl;
> > + unsigned int usb3phyctl;
> > + unsigned int intsr2;
> > + unsigned int intcrpce2b;
> > + unsigned int intcrpce0b;
> > + unsigned int intcrpce1b;
> > + unsigned int intcrpce3b;
> > + unsigned int rsvd13[4];
> > + unsigned int intcrpce2c;
> > + unsigned int intcrpce0c;
> > + unsigned int intcrpce1c;
> > + unsigned int intcrpce3c;
> > + unsigned int rsvd14[40];
> > + unsigned int sd2irv4;
> > + unsigned int sd2irv5;
> > + unsigned int sd2irv6;
> > + unsigned int sd2irv7;
> > + unsigned int sd2irv8;
> > + unsigned int sd2irv9;
> > + unsigned int sd2irv10;
> > + unsigned int sd2irv11;
> > + unsigned int rsvd15[8];
> > + unsigned int mfsel1;
> > + unsigned int mfsel2;
> > + unsigned int mfsel3;
> > + unsigned int mfsel4;
> > + unsigned int mfsel5;
> > + unsigned int mfsel6;
> > + unsigned int mfsel7;
> > + unsigned int rsvd16[1];
> > + unsigned int mfsel_lk1;
> > + unsigned int mfsel_lk2;
> > + unsigned int mfsel_lk3;
> > + unsigned int mfsel_lk4;
> > + unsigned int mfsel_lk5;
> > + unsigned int mfsel_lk6;
> > + unsigned int mfsel_lk7;
> > + unsigned int rsvd17[1];
> > + unsigned int mfsel_set1;
> > + unsigned int mfsel_set2;
> > + unsigned int mfsel_set3;
> > + unsigned int mfsel_set4;
> > + unsigned int mfsel_set5;
> > + unsigned int mfsel_set6;
> > + unsigned int mfsel_set7;
> > + unsigned int rsvd18[1];
> > + unsigned int mfsel_clr1;
> > + unsigned int mfsel_clr2;
> > + unsigned int mfsel_clr3;
> > + unsigned int mfsel_clr4;
> > + unsigned int mfsel_clr5;
> > + unsigned int mfsel_clr6;
> > + unsigned int mfsel_clr7;
> > + };
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/gpio.h b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> > new file mode 100644
> > index 0000000000..234a1d3de9
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/gpio.h
> > @@ -0,0 +1,11 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef _NPCM_GPIO_H_
> > +#define _NPCM_GPIO_H_
> > +
> > +#define NPCM_GPIO_BA 0xF0010000
> > +
> > +#endif
> > diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
> > new file mode 100644
> > index 0000000000..ffaff50fe2
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
> > @@ -0,0 +1,32 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +#ifndef _NPCM_RST_H_
> > +#define _NPCM_RST_H_
> > +
> > +enum reset_type {
> > + PORST_TYPE = 0x01,
> > + CORST_TYPE = 0x02,
> > + WD0RST_TYPE = 0x03,
> > + SWR1ST_TYPE = 0x04,
> > + SWR2ST_TYPE = 0x05,
> > + SWR3ST_TYPE = 0x06,
> > + SWR4ST_TYPE = 0x07,
> > + WD1RST_TYPE = 0x08,
> > + WD2RST_TYPE = 0x09,
> > + UNKNOWN_TYPE = 0x10,
> > +};
> > +
> > +#define PORST 0x80000000
> > +#define CORST 0x40000000
> > +#define WD0RST 0x20000000
> > +#define SWR1ST 0x10000000
> > +#define SWR2ST 0x08000000
> > +#define SWR3ST 0x04000000
> > +#define SWR4ST 0x02000000
> > +#define WD1RST 0x01000000
> > +#define WD2RST 0x00800000
> > +#define RESSR_MASK 0xff800000
> > +
> > +enum reset_type npcm8xx_reset_reason(void);
> > +
> > +#endif
> > diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig
> > new file mode 100644
> > index 0000000000..e014dd4b79
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/Kconfig
> > @@ -0,0 +1,24 @@
> > +if ARCH_NPCM
> > +
> > +config SYS_ARCH
> > + default "arm"
> > +
> > +config SYS_TEXT_BASE
> > + default 0x8000
> > +
> > +choice
> > + prompt "Nuvoton SoC select"
> > + default ARCH_NPCM8XX
> > +
> > +config ARCH_NPCM8XX
> > + bool "Support Nuvoton NPCM8xx SoC"
> > + select ARM64
> > + help
> > + General support for NPCM8xx BMC (Arbel).
> > + Nuvoton NPCM8xx BMC is based on the Cortex A35.
> > +
> > +endchoice
> > +
> > +source "arch/arm/mach-nuvoton/npcm8xx/Kconfig"
> > +
> > +endif
> > diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile
> > new file mode 100644
> > index 0000000000..e75689a1a0
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/Kconfig b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> > new file mode 100644
> > index 0000000000..478a046ad5
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
> > @@ -0,0 +1,18 @@
> > +if ARCH_NPCM8XX
> > +
> > +config SYS_CPU
> > + default "armv8"
> > +
> > +config SYS_SOC
> > + default "npcm8xx"
> > +
> > +config TARGET_ARBEL_EVB
> > + bool "Arbel-EVB"
> > + help
> > + ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
> > + supports general functions of Basebase Management Controller
> > + (BMC).
> > +
> > +source "board/nuvoton/arbel/Kconfig"
> > +
> > +endif
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/Makefile b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> > new file mode 100644
> > index 0000000000..c62a4aa20a
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/Makefile
> > @@ -0,0 +1 @@
> > +obj-y += reset.o cpu.o
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/cpu.c b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> > new file mode 100644
> > index 0000000000..8a7315d535
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
> > @@ -0,0 +1,170 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <cpu_func.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/gcr.h>
> > +#include <asm/arch/espi.h>
> > +#include <asm/armv8/mmu.h>
> > +#include <asm/system.h>
> > +#include <asm/global_data.h>
> > +
> > +/* System Counter */
> > +struct sctr_regs {
> > + u32 cntcr;
> > + u32 cntsr;
> > + u32 cntcv1;
> > + u32 cntcv2;
> > + u32 resv1[4];
> > + u32 cntfid0;
> > + u32 cntfid1;
> > + u32 cntfid2;
> > + u32 resv2[1001];
> > + u32 counterid[1];
> > +};
> > +
> > +#define SC_CNTCR_ENABLE BIT(0)
> > +#define SC_CNTCR_HDBG BIT(1)
> > +#define SC_CNTCR_FREQ0 BIT(8)
> > +#define SC_CNTCR_FREQ1 BIT(9)
> > +
> > +#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int print_cpuinfo(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > + unsigned int id = 0;
> > + unsigned long mpidr_val = 0;
> > + unsigned int mdlr = 0;
> > +
> > + asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
> > +
> > + mdlr = readl(&gcr->mdlr);
> > +
> > + printf("CPU-%d: ", (unsigned int)(mpidr_val & 0x3));
> > +
> > + switch (mdlr) {
> > + case ARBEL_NPCM845:
> > + printf("NPCM845 ");
> > + break;
> > + case ARBEL_NPCM830:
> > + printf("NPCM830 ");
> > + break;
> > + case ARBEL_NPCM810:
> > + printf("NPCM810 ");
> > + break;
> > + default:
> > + printf("NPCM8XX ");
> > + break;
> > + }
> > +
> > + id = readl(&gcr->pdid);
> > + switch (id) {
> > + case ARBEL_Z1:
> > + printf("Z1 @ ");
> > + break;
> > + case ARBEL_A1:
> > + printf("A1 @ ");
> > + break;
> > + default:
> > + printf("Unknown\n");
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void npcm_sysintf_init(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > + u32 espi_ch_supp, val;
> > +
> > + espi_ch_supp = ofnode_conf_read_int("espi-channel-support", 0);
> > +
> > + if (espi_ch_supp) {
> > + /* Use eSPI function and initialize ESPICFG */
> > + u32 hindp = 0x00011110 | espi_ch_supp;
> > +
> > + writel((readl(&gcr->mfsel4) | (1 << MFSEL4_ESPISEL)), &gcr->mfsel4);
> > + writel(hindp, NPCM_ESPI_BA + ESPIHINDP);
> > + val = readl(NPCM_ESPI_BA + ESPICFG);
> > + val |= ESPI_IO_MODE_SINGLE_DUAL_QUAD << ESPICFG_IOMODE_SHIFT;
> > + val |= ESPI_MAX_33_MHZ << ESPICFG_MAXFREQ_SHIFT;
> > + val |= ((espi_ch_supp & ESPICFG_CHNSUPP_MASK) << ESPICFG_CHNSUPP_SHFT);
> > + writel(val, NPCM_ESPI_BA + ESPICFG);
> > + } else {
> > + /* Use LPC function */
> > + writel((readl(&gcr->mfsel1) | (1 << MFSEL1_LPCSEL)), &gcr->mfsel1);
> > + }
> > +}
> > +
> > +int arch_cpu_init(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > +
> > + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
> > + /* enable cache to speed up system running */
> > + if (get_sctlr() & CR_M)
> > + return 0;
> > +
> > + icache_enable();
> > + __asm_invalidate_dcache_all();
> > + __asm_invalidate_tlb_all();
> > + set_sctlr(get_sctlr() | CR_C);
> > + }
> > +
> > + /* Power voltage select setup */
> > + setbits_le32(&gcr->vsrcr, BIT(30));
> > +
> > + npcm_sysintf_init();
> > +
> > + return 0;
> > +}
> > +
> > +static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
> > + {
> > + /* DRAM */
> > + .phys = 0x0UL,
> > + .virt = 0x0UL,
> > + .size = 0x80000000UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > + PTE_BLOCK_INNER_SHARE
> > + },
> > + {
> > + .phys = 0x80000000UL,
> > + .virt = 0x80000000UL,
> > + .size = 0x80000000UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > + PTE_BLOCK_NON_SHARE |
> > + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > + },
> > + {
> > + /* List terminator */
> > + 0,
> > + }
> > +};
> > +
> > +struct mm_region *mem_map = npcm_mem_map;
> > +
> > +int timer_init(void)
> > +{
> > + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
> > + unsigned int cntfrq_el0;
> > +
> > + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
> > + writel(cntfrq_el0, &sctr->cntfid0);
> > +
> > + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
> > + SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
> > +
> > + gd->arch.tbl = 0;
> > + gd->arch.tbu = 0;
> > +
> > + return 0;
> > +}
> > diff --git a/arch/arm/mach-nuvoton/npcm8xx/reset.c b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> > new file mode 100644
> > index 0000000000..7fbed7ba76
> > --- /dev/null
> > +++ b/arch/arm/mach-nuvoton/npcm8xx/reset.c
> > @@ -0,0 +1,51 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/rst.h>
> > +#include <asm/arch/gcr.h>
> > +
> > +void reset_cpu(void)
> > +{
> > + /* Watcdog reset - WTCR register set WTE-BIT7 WTRE-BIT1 WTR-BIT0 */
> > + writel(0x83, 0xf000801c);
> > +
> > + while (1)
> > + ;
> > +}
> > +
> > +void reset_misc(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > +
> > + /* clear WDC */
> > + writel(readl(&gcr->intcr2) & ~(1 << INTCR2_WDC), &gcr->intcr2);
> > +}
> > +
> > +enum reset_type npcm8xx_reset_reason(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > + enum reset_type type = UNKNOWN_TYPE;
> > + u32 value = readl(&gcr->ressr);
> > +
> > + if (value == 0)
> > + value = ~readl(&gcr->intcr2);
> > +
> > + value &= RESSR_MASK;
> > +
> > + if (value & CORST)
> > + type = CORST;
> > + if (value & WD0RST)
> > + type = WD0RST;
> > + if (value & WD1RST)
> > + type = WD1RST;
> > + if (value & WD2RST)
> > + type = WD2RST;
> > + if (value & PORST)
> > + type = PORST;
> > +
> > + return type;
> > +}
> > diff --git a/board/nuvoton/arbel/Kconfig b/board/nuvoton/arbel/Kconfig
> > new file mode 100644
> > index 0000000000..4a03ea1abf
> > --- /dev/null
> > +++ b/board/nuvoton/arbel/Kconfig
> > @@ -0,0 +1,18 @@
> > +if TARGET_ARBEL_EVB
> > +
> > +config SYS_BOARD
> > + default "arbel"
> > +
> > +config SYS_VENDOR
> > + default "nuvoton"
> > +
> > +config SYS_CONFIG_NAME
> > + default "arbel"
> > +
> > +config SYS_MEM_TOP_HIDE
> > + hex "Reserved TOP memory"
> > + default 0xB000000
> > + help
> > + Reserve memory for ECC/GFX/VCD/ECE.
> > +
> > +endif
> > diff --git a/board/nuvoton/arbel/Makefile b/board/nuvoton/arbel/Makefile
> > new file mode 100644
> > index 0000000000..f9ad1dea34
> > --- /dev/null
> > +++ b/board/nuvoton/arbel/Makefile
> > @@ -0,0 +1 @@
> > +obj-y += arbel.o
> > diff --git a/board/nuvoton/arbel/arbel.c b/board/nuvoton/arbel/arbel.c
> > new file mode 100644
> > index 0000000000..86cef98c5f
> > --- /dev/null
> > +++ b/board/nuvoton/arbel/arbel.c
> > @@ -0,0 +1,33 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/gcr.h>
> > +#include <asm/mach-types.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +int board_init(void)
> > +{
> > + gd->bd->bi_arch_number = MACH_TYPE_NPCMX50;
> > + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100UL);
> > +
> > + return 0;
> > +}
> > +
> > +int dram_init(void)
> > +{
> > + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
> > +
> > + /*
> > + * get dram active size value from bootblock.
> > + * Value sent using scrpad_02 register.
> > + */
> > + gd->ram_size = readl(&gcr->scrpad_b);
> > +
> > + return 0;
> > +}
> > diff --git a/include/configs/arbel.h b/include/configs/arbel.h
> > new file mode 100644
> > index 0000000000..2cb658c3e6
> > --- /dev/null
> > +++ b/include/configs/arbel.h
> > @@ -0,0 +1,54 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2021 Nuvoton Technology Corp.
> > + */
> > +
> > +#ifndef __CONFIG_ARBEL_H
> > +#define __CONFIG_ARBEL_H
> > +
> > +#define CONFIG_GICV2
> > +#define GICD_BASE (0xDFFF9000)
> > +#define GICC_BASE (0xDFFFA000)
> > +
> > +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
> > +#define CONFIG_USB_OHCI_NEW
> > +#define CONFIG_SETUP_MEMORY_TAGS
> > +#define CONFIG_INITRD_TAG
> > +#define CONFIG_SYS_MAXARGS 32
> > +#define CONFIG_SYS_CBSIZE 256
> > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > +#define CONFIG_SYS_BOOTM_LEN (20 << 20)
> > +#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
> > +#define CONFIG_SYS_SDRAM_BASE 0x0
> > +#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
> > +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
> > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> > +#define CONFIG_BAUDRATE 115200
> > +#define CONFIG_SYS_HZ 1000
> > +#define CONFIG_BITBANGMII_MULTI
> > +
> > +/* Default environemnt variables */
> > +#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot"
> > +#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
> > + "stdin=serial\0" \
> > + "stdout=serial\0" \
> > + "stderr=serial\0" \
> > + "ethact=gmac1\0" \
> > + "autostart=no\0" \
> > + "ethaddr=00:00:F7:A0:00:FC\0" \
> > + "eth1addr=00:00:F7:A0:00:FD\0" \
> > + "eth2addr=00:00:F7:A0:00:FE\0" \
> > + "eth3addr=00:00:F7:A0:00:FF\0" \
> > + "gatewayip=192.168.0.17\0" \
> > + "serverip=192.168.0.17\0" \
> > + "ipaddr=192.168.0.15\0" \
> > + "romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
> > + "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
> > + "earlycon=uart8250,mmio32,0xf0000000\0" \
> > + "console=ttyS0,115200n8\0" \
> > + "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
> > + "console=${console} ramdisk_size=48000\0" \
> > + "\0"
> > +
> > +#endif
> >
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
[not found] ` <d23d2925-d5ea-e23b-fb99-7856aedfb328@gmail.com>
[not found] ` <0fee2e28-b3c8-d649-0921-52e6fb098e71@gmail.com>
@ 2022-03-11 0:57 ` Stanley Chu
1 sibling, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2022-03-11 0:57 UTC (permalink / raw)
To: Jesse Taube, Tom Rini, Stanley Chu; +Cc: kwliu, ctcchien, u-boot
Hi Jesse,
Thanks for the comment, this will be addressed in the next patches.
--
Stanley
On Thu, Dec 16, 2021 at 6:16 AM Jesse Taube <mr.bossman075@gmail.com> wrote:
>
>
>
> On 12/15/21 13:32, Sean Anderson wrote:
> > On 12/14/21 9:57 PM, Stanley Chu wrote:
> >> Add basic support for the Nuvoton NPCM845 BMC.
> >>
> >> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> >> ---
> >> arch/arm/Kconfig | 9 +
> >> arch/arm/Makefile | 1 +
> >> arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
> >> arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
> >> arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
> >> arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
> >> arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
> >> arch/arm/mach-nuvoton/Kconfig | 24 ++
> >> arch/arm/mach-nuvoton/Makefile | 1 +
> >> arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
> >> arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
> >> arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
> >> arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
> >> board/nuvoton/arbel/Kconfig | 18 ++
> >> board/nuvoton/arbel/Makefile | 1 +
> >> board/nuvoton/arbel/arbel.c | 33 +++
> >> include/configs/arbel.h | 54 ++++
> >> 17 files changed, 924 insertions(+)
> Hello World!
>
> Because I was CC'ed I guess I will keep myself up-to date.
> This commit has 17 files changed and almost 1k insertions,
> That is a relatively large commit. Would it be better to split
> /arch/arm/include/asm
> /arch/arm/mach-nuvoton
> /board
> /include/configs
> into different commits.
> I ask this because I split them for a patch I'm working on
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2022-03-11 0:50 ` Stanley Chu
@ 2022-03-11 1:06 ` Giulio Benetti
2022-03-11 1:07 ` Giulio Benetti
0 siblings, 1 reply; 31+ messages in thread
From: Giulio Benetti @ 2022-03-11 1:06 UTC (permalink / raw)
To: Stanley Chu, Tom Rini; +Cc: kwliu, ctcchien, avifishman70, tmaimon77, u-boot
Hi Stanley,
On 11/03/22 01:50, Stanley Chu wrote:
> Hi Giulio,
>
> Thank you for your comment, I've submitted a clk driver patch to address this.
> https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-yschu@nuvoton.com/
Good to see that!
But I think you should submit the entire patchset:
https://patchwork.ozlabs.org/project/uboot/list/?series=276836&state=%2A&archive=both
including this patch as V2. Otherwise it's difficult to test it.
As you see in Patchwork you have superseded and changes requested on
other patches. So you should modify them accordingly and send V2 series.
If other patches have been applied then send only the ones not applied.
But as I can see here they are still not applied.
Kind regards
--
Giulio Benetti
Benetti Engineering sas
> --
> Stanley
>
> On Wed, Dec 15, 2021 at 8:12 PM Giulio Benetti
> <giulio.benetti@benettiengineering.com> wrote:
>>
>> Hi Stanley,
>>
>> On 15/12/21 03:57, Stanley Chu wrote:
>>> Add basic support for the Nuvoton NPCM845 BMC.
>>>
>>> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
>>> ---
>>> arch/arm/Kconfig | 9 +
>>> arch/arm/Makefile | 1 +
>>> arch/arm/include/asm/arch-npcm8xx/clock.h | 164 ++++++++++++
>>> arch/arm/include/asm/arch-npcm8xx/espi.h | 23 ++
>>> arch/arm/include/asm/arch-npcm8xx/gcr.h | 313 ++++++++++++++++++++++
>>> arch/arm/include/asm/arch-npcm8xx/gpio.h | 11 +
>>> arch/arm/include/asm/arch-npcm8xx/rst.h | 32 +++
>>> arch/arm/mach-nuvoton/Kconfig | 24 ++
>>> arch/arm/mach-nuvoton/Makefile | 1 +
>>> arch/arm/mach-nuvoton/npcm8xx/Kconfig | 18 ++
>>> arch/arm/mach-nuvoton/npcm8xx/Makefile | 1 +
>>> arch/arm/mach-nuvoton/npcm8xx/cpu.c | 170 ++++++++++++
>>
>> Here ^^^ you setup timer, but it should be a separate driver IMHO. At
>> least this is what I've done for imxrt.
>> Same goes for clock, there is no clock driver and you setup spi clock
>> directly inside the same file with npcm_sysintf_init() while that should
>> be part of the clock driver.
>>
>> Also all defines regarding to clocks and peripherals should go into
>> their driver.
>>
>>> arch/arm/mach-nuvoton/npcm8xx/reset.c | 51 ++++
>>
>> Here you've mixed up the architecture(above) and the board(below) in a
>> single patch.
>>
>>> board/nuvoton/arbel/Kconfig | 18 ++
>>> board/nuvoton/arbel/Makefile | 1 +
>>> board/nuvoton/arbel/arbel.c | 33 +++
>>> include/configs/arbel.h | 54 ++++
>>
>> arbel should be arbel-evk
>>
>> I stop here, because there could be big changes if others agree.
>>
>> Best regards
>> --
>> Giulio Benetti
>> Benetti Engineering sas
>>
>>> 17 files changed, 924 insertions(+)
>>> create mode 100644 arch/arm/include/asm/arch-npcm8xx/clock.h
>>> create mode 100644 arch/arm/include/asm/arch-npcm8xx/espi.h
>>> create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h
>>> create mode 100644 arch/arm/include/asm/arch-npcm8xx/gpio.h
>>> create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h
>>> create mode 100644 arch/arm/mach-nuvoton/Kconfig
>>> create mode 100644 arch/arm/mach-nuvoton/Makefile
>>> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Kconfig
>>> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/Makefile
>>> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/cpu.c
>>> create mode 100644 arch/arm/mach-nuvoton/npcm8xx/reset.c
>>> create mode 100644 board/nuvoton/arbel/Kconfig
>>> create mode 100644 board/nuvoton/arbel/Makefile
>>> create mode 100644 board/nuvoton/arbel/arbel.c
>>> create mode 100644 include/configs/arbel.h
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index f7f03837fe..80ec42f6be 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -1952,6 +1952,13 @@ config TARGET_XENGUEST_ARM64
>>> select LINUX_KERNEL_IMAGE_HEADER
>>> select XEN_SERIAL
>>> select SSCANF
>>> +
>>> +config ARCH_NPCM
>>> + bool "Support Nuvoton SoCs"
>>> + select DM
>>> + select OF_CONTROL
>>> + imply CMD_DM
>>> +
>>> endchoice
>>>
>>> config SUPPORT_PASSING_ATAGS
>>> @@ -2150,6 +2157,8 @@ source "arch/arm/mach-imx/Kconfig"
>>>
>>> source "arch/arm/mach-nexell/Kconfig"
>>>
>>> +source "arch/arm/mach-nuvoton/Kconfig"
>>> +
>>> source "board/armltd/total_compute/Kconfig"
>>>
>>> source "board/bosch/shc/Kconfig"
>>> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
>>> index ad757e982e..29a0250ab6 100644
>>> --- a/arch/arm/Makefile
>>> +++ b/arch/arm/Makefile
>>> @@ -92,6 +92,7 @@ machine-$(CONFIG_ARCH_VERSAL) += versal
>>> machine-$(CONFIG_ARCH_ZYNQ) += zynq
>>> machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
>>> machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
>>> +machine-$(CONFIG_ARCH_NPCM) += nuvoton
>>>
>>> machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
>>>
>>> diff --git a/arch/arm/include/asm/arch-npcm8xx/clock.h b/arch/arm/include/asm/arch-npcm8xx/clock.h
>>> new file mode 100644
>>> index 0000000000..088b536b7b
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-npcm8xx/clock.h
>>> @@ -0,0 +1,164 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#ifndef _NPCM_CLOCK_H_
>>> +#define _NPCM_CLOCK_H_
>>> +
>>> +#define NPCM_CLK_BA 0xF0801000
>>> +enum {
>>> + APB1 = 1,
>>> + APB2 = 2,
>>> + APB3 = 3,
>>> + APB4 = 4,
>>> + APB5 = 5,
>>> + SPI0 = 10,
>>> + SPI1 = 11,
>>> + SPI3 = 13,
>>> + SPIX = 14,
>>> +};
>>> +
>>> +/* Clock Select Register (CLKSEL) */
>>> +#define CLKSEL_RCPCKSEL 27
>>> +#define CLKSEL_RGSEL 25
>>> +#define CLKSEL_GFXMSEL 21
>>> +#define CLKSEL_CLKOUTSEL 18
>>> +#define CLKSEL_PCICKSEL 16
>>> +#define CLKSEL_ADCCKSEL 14
>>> +#define CLKSEL_MCCKSEL 12
>>> +#define CLKSEL_SUCKSEL 10
>>> +#define CLKSEL_UARTCKSEL 8
>>> +#define CLKSEL_SDCKSEL 6
>>> +#define CLKSEL_PIXCKSEL 4
>>> +#define CLKSEL_CPUCKSEL 0
>>> +
>>> +/* Clock Divider Control Register 1 (CLKDIV1) */
>>> +#define CLKDIV1_ADCCKDIV 28
>>> +#define CLKDIV1_CLK4DIV 26
>>> +#define CLKDIV1_PRE_ADCCKDIV 21
>>> +#define CLKDIV1_UARTDIV 16
>>> +#define CLKDIV1_MMCCKDIV 11
>>> +#define CLKDIV1_SPI3CKDIV 6
>>> +#define CLKDIV1_PCICKDIV 2
>>> +
>>> +/* Clock Divider Control Register 2 (CLKDIV2) */
>>> +#define CLKDIV2_APB4CKDIV 30
>>> +#define CLKDIV2_APB3CKDIV 28
>>> +#define CLKDIV2_APB2CKDIV 26
>>> +#define CLKDIV2_APB1CKDIV 24
>>> +#define CLKDIV2_APB5CKDIV 22
>>> +#define CLKDIV2_CLKOUTDIV 16
>>> +#define CLKDIV2_GFXCKDIV 13
>>> +#define CLKDIV2_SUCKDIV 8
>>> +#define CLKDIV2_SU48CKDIV 4
>>> +
>>> +/* PLL Control Register 2 (PLLCON2) */
>>> +#define PLLCON_LOKI 31
>>> +#define PLLCON_LOKS 30
>>> +#define PLLCON_FBDV 16
>>> +#define PLLCON_OTDV2 13
>>> +#define PLLCON_PWDEN 12
>>> +#define PLLCON_OTDV1 8
>>> +#define PLLCON_INDV 0
>>> +
>>> +/* CPUCKSEL (CPU/AMBA/MC Clock Source Select Bit) */
>>> +#define CLKSEL_CPUCKSEL_PLL0 0x00 /* 0 0: PLL0 clock*/
>>> +#define CLKSEL_CPUCKSEL_PLL1 0x01 /* 0 1: PLL1 clock */
>>> +#define CLKSEL_CPUCKSEL_CLKREF 0x02 /* 1 0: CLKREF input (25 MHZ, default) */
>>> +#define CLKSEL_CPUCKSEL_SYSBPCK 0x03 /* 1 1: Bypass clock from pin SYSBPCK */
>>> +
>>> +/* UARTCKSEL (Core and Host UART Clock Source Select Bit). */
>>> +#define CLKSEL_UARTCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
>>> +#define CLKSEL_UARTCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
>>> +#define CLKSEL_UARTCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
>>> +#define CLKSEL_UARTCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
>>> +
>>> +/* SDCKSEL (SDHC Clock Source Select Bit). */
>>> +#define CLKSEL_SDCKSEL_PLL0 0x00 /* 0 0: PLL0 clock. */
>>> +#define CLKSEL_SDCKSEL_PLL1 0x01 /* 0 1: PLL1 clock. */
>>> +#define CLKSEL_SDCKSEL_CLKREF 0x02 /* 1 0: CLKREF clock (25 MHZ, default). */
>>> +#define CLKSEL_SDCKSEL_PLL2 0x03 /* 1 1: PLL2 clock divided by 2. */
>>> +
>>> +/* IP Software Reset Register 1 (IPSRST1), offset 0x20 */
>>> +#define IPSRST1_USBDEV1 5
>>> +#define IPSRST1_USBDEV2 8
>>> +#define IPSRST1_USBDEV3 25
>>> +#define IPSRST1_USBDEV4 22
>>> +#define IPSRST1_USBDEV5 23
>>> +#define IPSRST1_USBDEV6 24
>>> +#define IPSRST1_GMAC4 21
>>> +#define IPSRST1_GMAC3 6
>>> +
>>> +/* IP Software Reset Register 2 (IPSRST2), offset 0x24 */
>>> +#define IPSRST2_GMAC1 28
>>> +#define IPSRST2_GMAC2 25
>>> +#define IPSRST2_USBHOST1 26
>>> +#define IPSRST2_SDHC 9
>>> +#define IPSRST2_MMC 8
>>> +
>>> +/* IP Software Reset Register 3 (IPSRST3), offset 0x34 */
>>> +#define IPSRST3_USBPHY1 24
>>> +#define IPSRST3_USBPHY2 25
>>> +#define IPSRST3_USBHUB 8
>>> +#define IPSRST3_USBDEV9 7
>>> +#define IPSRST3_USBDEV8 6
>>> +#define IPSRST3_USBDEV7 5
>>> +#define IPSRST3_USBDEV0 4
>>> +
>>> +/* IP Software Reset Register 4 (IPSRST4), offset 0x74 */
>>> +#define IPSRST4_USBHOST2 31
>>> +#define IPSRST4_USBPHY3 25
>>> +
>>> +#define EXT_CLOCK_FREQUENCY_KHZ 25 * 1000 * 1UL
>>> +#define EXT_CLOCK_FREQUENCY_MHZ 25
>>> +
>>> +struct clk_ctl {
>>> + unsigned int clken1;
>>> + unsigned int clksel;
>>> + unsigned int clkdiv1;
>>> + unsigned int pllcon0;
>>> + unsigned int pllcon1;
>>> + unsigned int swrstr;
>>> + unsigned char res1[0x8];
>>> + unsigned int ipsrst1;
>>> + unsigned int ipsrst2;
>>> + unsigned int clken2;
>>> + unsigned int clkdiv2;
>>> + unsigned int clken3;
>>> + unsigned int ipsrst3;
>>> + unsigned int wd0rcr;
>>> + unsigned int wd1rcr;
>>> + unsigned int wd2rcr;
>>> + unsigned int swrstc1;
>>> + unsigned int swrstc2;
>>> + unsigned int swrstc3;
>>> + unsigned int tiprstc;
>>> + unsigned int pllcon2;
>>> + unsigned int clkdiv3;
>>> + unsigned int corstc;
>>> + unsigned int pllcong;
>>> + unsigned int ahbckfi;
>>> + unsigned int seccnt;
>>> + unsigned int cntr25m;
>>> + unsigned int clken4;
>>> + unsigned int ipsrst4;
>>> + unsigned int busto;
>>> + unsigned int clkdiv4;
>>> + unsigned int wd0rcrb;
>>> + unsigned int wd1rcrb;
>>> + unsigned int wd2rcrb;
>>> + unsigned int swrstc1b;
>>> + unsigned int swrstc2b;
>>> + unsigned int swrstc3b;
>>> + unsigned int tiprstcb;
>>> + unsigned int corstcb;
>>> + unsigned int ipsrstdis1;
>>> + unsigned int ipsrstdis2;
>>> + unsigned int ipsrstdis3;
>>> + unsigned int ipsrstdis4;
>>> + unsigned char res2[0x10];
>>> + unsigned int thrtl_cnt;
>>> +};
>>> +
>>> +#endif
>>> diff --git a/arch/arm/include/asm/arch-npcm8xx/espi.h b/arch/arm/include/asm/arch-npcm8xx/espi.h
>>> new file mode 100644
>>> index 0000000000..d4de012b02
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-npcm8xx/espi.h
>>> @@ -0,0 +1,23 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +
>>> +#ifndef _NPCM_ESPI_H_
>>> +#define _NPCM_ESPI_H_
>>> +
>>> +#define NPCM_ESPI_BA 0xF009F000
>>> +/* Register offsets */
>>> +#define ESPICFG 0x04
>>> +#define ESPIHINDP 0x80
>>> +
>>> +/* Channel Supported */
>>> +#define ESPICFG_CHNSUPP_MASK 0x0F
>>> +#define ESPICFG_CHNSUPP_SHFT 24
>>> +
>>> +/* I/O Mode Supported */
>>> +#define ESPICFG_IOMODE_SHIFT 8
>>> +#define ESPI_IO_MODE_SINGLE_DUAL_QUAD 3
>>> +
>>> +/* Maximum Frequency Supported */
>>> +#define ESPICFG_MAXFREQ_SHIFT 10
>>> +#define ESPI_MAX_33_MHZ 2
>>> +
>>> +#endif
>>> diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
>>> new file mode 100644
>>> index 0000000000..14a4b2dbfb
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
>>> @@ -0,0 +1,313 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#ifndef _NPCM_GCR_H_
>>> +#define _NPCM_GCR_H_
>>> +
>>> +#define NPCM_GCR_BA 0xF0800000
>>> +/* On-Chip ARBEL NPCM8XX VERSIONS */
>>> +
>>> +#define ARBEL_Z1 0x00A35850
>>> +#define ARBEL_A1 0x04a35850
>>> +#define ARBEL_NPCM845 0x00000000
>>> +#define ARBEL_NPCM830 0x00300395
>>> +#define ARBEL_NPCM810 0x00000220
>>> +
>>> +/* Function Lock Register 2 (FLOCKR2) */
>>> +#define FLOCKR2_MMCRST 12
>>> +#define FLOCKR2_MMCRSTLK 13
>>> +#define FLOCKR2_G35DA2P 18
>>> +
>>> +/* Power-On Setting Register (PWRON) */
>>> +#define PWRON_BSPA 4 /* STRAP5 */
>>> +#define PWRON_SECEN 7 /* STRAP8 */
>>> +
>>> +/* Multiple Function Pin Select Register 1 (MFSEL1) */
>>> +#define MFSEL1_SIRQSE 31
>>> +#define MFSEL1_IOX1SEL 30
>>> +#define MFSEL1_HSI2BSEL 29
>>> +#define MFSEL1_HSI1BSEL 28
>>> +#define MFSEL1_DVH1SEL 27
>>> +#define MFSEL1_LPCSEL 26
>>> +#define MFSEL1_PECIB 25
>>> +#define MFSEL1_GSPISEL 24
>>> +#define MFSEL1_SMISEL 22
>>> +#define MFSEL1_CLKOSEL 21
>>> +#define MFSEL1_DVOSEL 18
>>> +#define MFSEL1_KBCICSEL 17
>>> +#define MFSEL1_R2MDSEL 16
>>> +#define MFSEL1_R2ERRSEL 15
>>> +#define MFSEL1_RMII2SEL 14
>>> +#define MFSEL1_R1MDSEL 13
>>> +#define MFSEL1_R1ERRSEL 12
>>> +#define MFSEL1_HSI2ASEL 11
>>> +#define MFSEL1_HSI1ASEL 10
>>> +#define MFSEL1_BSPSEL 9
>>> +#define MFSEL1_SMB2SEL 8
>>> +#define MFSEL1_SMB1SEL 7
>>> +#define MFSEL1_SMB0SEL 6
>>> +#define MFSEL1_HSI2CSEL 5
>>> +#define MFSEL1_HSI1CSEL 4
>>> +#define MFSEL1_S0CS1SEL 3
>>> +#define MFSEL1_SMB5SEL 2
>>> +#define MFSEL1_SMB4SEL 1
>>> +#define MFSEL1_SMB3SEL 0
>>> +
>>> +/* Multiple Function Pin Select Register 3 (MFSEL3) */
>>> +#define MFSEL3_DVODEDLY 27
>>> +#define MFSEL3_DDRDVOSEL 26
>>> +#define MFSEL3_MMCCDSEL 25
>>> +#define MFSEL3_BU1SEL 24
>>> +#define MFSEL3_I3C5SEL 22
>>> +#define MFSEL3_WDO2SEL 20
>>> +#define MFSEL3_WDO1SEL 19
>>> +#define MFSEL3_IOXHSEL 18
>>> +#define MFSEL3_PCIEPUSE 17
>>> +#define MFSEL3_CLKRUNSEL 16
>>> +#define MFSEL3_IOX2SEL 14
>>> +#define MFSEL3_PSPISEL 13
>>> +#define MFSEL3_MMC8SEL 11
>>> +#define MFSEL3_MMCSEL 10
>>> +#define MFSEL3_RMII1SEL 9
>>> +#define MFSEL3_SMB15SEL 8
>>> +#define MFSEL3_SMB14SEL 7
>>> +#define MFSEL3_SMB13SEL 6
>>> +#define MFSEL3_SMB12SEL 5
>>> +#define MFSEL3_SPI1SEL 4
>>> +#define MFSEL3_FIN1916SELB 3
>>> +#define MFSEL3_SMB7SEL 2
>>> +#define MFSEL3_SMB6SEL 1
>>> +#define MFSEL3_SCISEL 0
>>> +
>>> +/* Multiple Function Pin Select Register 4 (MFSEL4) */
>>> +#define MFSEL4_SMB11DDC 29
>>> +#define MFSEL4_SXCS1SEL 28
>>> +#define MFSEL4_SPXSEL 27
>>> +#define MFSEL4_RG2SEL 24
>>> +#define MFSEL4_RG2MSEL 23
>>> +#define MFSEL4_BU2SELB 22
>>> +#define MFSEL4_SG1MSEL 21
>>> +#define MFSEL4_SP3QSEL 20
>>> +#define MFSEL4_S3CS3SEL 19
>>> +#define MFSEL4_S3CS2SEL 18
>>> +#define MFSEL4_S3CS1SEL 17
>>> +#define MFSEL4_SP3SEL 16
>>> +#define MFSEL4_SP0QSEL 15
>>> +#define MFSEL4_SMB11SEL 14
>>> +#define MFSEL4_SMB10SEL 13
>>> +#define MFSEL4_SMB9SEL 12
>>> +#define MFSEL4_SMB8SEL 11
>>> +#define MFSEL4_DBGTRSEL 10
>>> +#define MFSEL4_CKRQSEL 9
>>> +#define MFSEL4_ESPISEL 8
>>> +#define MFSEL4_MMCRSEL 6
>>> +#define MFSEL4_SD1PSEL 5
>>> +#define MFSEL4_ROSEL 4
>>> +#define MFSEL4_ESPIPMESEL 2
>>> +#define MFSEL4_BSPASEL 1
>>> +#define MFSEL4_JTAG2SEL 0
>>> +
>>> +/* Multiple Function Pin Select Register 5 (MFSEL5) */
>>> +#define MFSEL5_R3OENSEL 14
>>> +#define MFSEL5_RMII3SEL 11
>>> +#define MFSEL5_R2OENSEL 10
>>> +#define MFSEL5_R1OENSEL 9
>>> +#define MFSEL5_NSPI1CS3SEL 5
>>> +#define MFSEL5_NSPI1CS2SEL 4
>>> +#define MFSEL5_SPI1D23SEL 3
>>> +#define MFSEL5_NSPI1CS1SEL 0
>>> +
>>> +/* Multiple Function Pin Select Register 6 (MFSEL6) */
>>> +#define MFSEL6_GPIO1836SEL 19
>>> +#define MFSEL6_FM1SEL 17
>>> +
>>> +/* Multiple Function Pin Select Register 7 (MFSEL7) */
>>> +#define MFSEL7_SMB15SELB 27
>>> +#define MFSEL7_GPIO1889SEL 25
>>> +
>>> +/* USB PHY1 Control Register (USB1PHYCTL) */
>>> +#define USB1PHYCTL_RS 28
>>> +/* USB PHY2 Control Register (USB2PHYCTL) */
>>> +#define USB2PHYCTL_RS 28
>>> +/* USB PHY2 Control Register (USB3PHYCTL) */
>>> +#define USB3PHYCTL_RS 28
>>> +
>>> +/* Integration Control Register (INTCR) */
>>> +#define INTCR_DUDKSMOD 30
>>> +#define INTCR_DDC3I 29
>>> +#define INTCR_KVMSI 28
>>> +#define INTCR_DEHS 27
>>> +#define INTCR_GGPCT2_0 24
>>> +#define INTCR_SGC2 23
>>> +#define INTCR_DSNS_TRIG 21
>>> +#define INTCR_DAC_SNS 20
>>> +#define INTCR_SGC1 19
>>> +#define INTCR_LDDRB 18
>>> +#define INTCR_GIRST 17
>>> +#define INTCR_DUDKSEN 16
>>> +#define INTCR_DACOFF 15
>>> +#define INTCR_DACSEL 14
>>> +#define INTCR_GFXINT 12
>>> +#define INTCR_DACOSOVR 10
>>> +#define INTCR_GFXIFDIS 8
>>> +#define INTCR_H2RQDIS 9
>>> +#define INTCR_H2DISPOFF 8
>>> +#define INTCR_GFXINT2 7
>>> +#define INTCR_VGAIOEN 6
>>> +#define INTCR_PSPIFEN 4
>>> +#define INTCR_HIFEN 3
>>> +#define INTCR_SMBFEN 2
>>> +#define INTCR_MFTFEN 1
>>> +#define INTCR_KCSRST_MODE 0
>>> +
>>> +/* Integration Control Register (INTCR2) */
>>> +#define INTCR2_WDC 21
>>> +
>>> +/* Integration Control Register (INTCR3) */
>>> +#define INTCR3_USBLPBK2 31 /* USB loop-backed HOST 1/2 */
>>> +#define INTCR3_USBLPBK 24 /* USB loop-backed mode on/off */
>>> +#define INTCR3_USBPHY3SW 14 /* 2 bits */
>>> +#define INTCR3_USBPHY2SW 12 /* 2 bits */
>>> +#define INTCR3_USBPPS 6
>>> +#define INTCR3_UHUB_RWUD 5
>>> +
>>> +/* Integration Control Register (INTCR4) */
>>> +#define INTCR4_GMMAP1 24
>>> +#define INTCR4_GMMAP0 16
>>> +#define INTCR4_R3EN 14
>>> +#define INTCR4_R2EN 13
>>> +#define INTCR4_R1EN 12
>>> +#define INTCR4_RGMIIREF 6
>>> +
>>> +/* I2C Segment Pin Select Register (I2CSEGSEL) */
>>> +#define I2CSEGSEL_S0DECFG 3
>>> +#define I2CSEGSEL_S4DECFG 17
>>> +
>>> +/* I2C Segment Control Register (I2CSEGCTL) */
>>> +#define I2CSEGCTL_S0DEN 20
>>> +#define I2CSEGCTL_S0DWE 21
>>> +#define I2CSEGCTL_S4DEN 24
>>> +#define I2CSEGCTL_S4DWE 25
>>> +#define I2CSEGCTL_INIT_VAL 0x9333F000
>>> +
>>> +struct npcm_gcr {
>>> + unsigned int pdid;
>>> + unsigned int pwron;
>>> + unsigned int swstrps;
>>> + unsigned int rsvd1[2];
>>> + unsigned int miscpe;
>>> + unsigned int spldcnt;
>>> + unsigned int rsvd2[1];
>>> + unsigned int flockr2;
>>> + unsigned int flockr3;
>>> + unsigned int rsvd3[3];
>>> + unsigned int a35_mode;
>>> + unsigned int spswc;
>>> + unsigned int intcr;
>>> + unsigned int intsr;
>>> + unsigned int obscr1;
>>> + unsigned int obsdr1;
>>> + unsigned int rsvd4[1];
>>> + unsigned int hifcr;
>>> + unsigned int rsvd5[3];
>>> + unsigned int intcr2;
>>> + unsigned int rsvd6[1];
>>> + unsigned int srcnt;
>>> + unsigned int ressr;
>>> + unsigned int rlockr1;
>>> + unsigned int flockr1;
>>> + unsigned int dscnt;
>>> + unsigned int mdlr;
>>> + unsigned int scrpad_c;
>>> + /* scrpad_b: holds the active dram size (value set by bootblock) */
>>> + unsigned int scrpad_b;
>>> + unsigned int rsvd7[4];
>>> + unsigned int daclvlr;
>>> + unsigned int intcr3;
>>> + unsigned int pcirctl;
>>> + unsigned int rsvd8[2];
>>> + unsigned int vsintr;
>>> + unsigned int rsvd9[1];
>>> + unsigned int sd2sur1;
>>> + unsigned int sd2sur2;
>>> + unsigned int sd2irv3;
>>> + unsigned int intcr4;
>>> + unsigned int obscr2;
>>> + unsigned int obsdr2;
>>> + unsigned int rsvd10[5];
>>> + unsigned int i2csegsel;
>>> + unsigned int i2csegctl;
>>> + unsigned int vsrcr;
>>> + unsigned int mlockr;
>>> + unsigned int rsvd11[8];
>>> + unsigned int etsr;
>>> + unsigned int dft1r;
>>> + unsigned int dft2r;
>>> + unsigned int dft3r;
>>> + unsigned int edffsr;
>>> + unsigned int rsvd12[1];
>>> + unsigned int intcrpce3;
>>> + unsigned int intcrpce2;
>>> + unsigned int intcrpce0;
>>> + unsigned int intcrpce1;
>>> + unsigned int dactest;
>>> + unsigned int scrpad;
>>> + unsigned int usb1phyctl;
>>> + unsigned int usb2phyctl;
>>> + unsigned int usb3phyctl;
>>> + unsigned int intsr2;
>>> + unsigned int intcrpce2b;
>>> + unsigned int intcrpce0b;
>>> + unsigned int intcrpce1b;
>>> + unsigned int intcrpce3b;
>>> + unsigned int rsvd13[4];
>>> + unsigned int intcrpce2c;
>>> + unsigned int intcrpce0c;
>>> + unsigned int intcrpce1c;
>>> + unsigned int intcrpce3c;
>>> + unsigned int rsvd14[40];
>>> + unsigned int sd2irv4;
>>> + unsigned int sd2irv5;
>>> + unsigned int sd2irv6;
>>> + unsigned int sd2irv7;
>>> + unsigned int sd2irv8;
>>> + unsigned int sd2irv9;
>>> + unsigned int sd2irv10;
>>> + unsigned int sd2irv11;
>>> + unsigned int rsvd15[8];
>>> + unsigned int mfsel1;
>>> + unsigned int mfsel2;
>>> + unsigned int mfsel3;
>>> + unsigned int mfsel4;
>>> + unsigned int mfsel5;
>>> + unsigned int mfsel6;
>>> + unsigned int mfsel7;
>>> + unsigned int rsvd16[1];
>>> + unsigned int mfsel_lk1;
>>> + unsigned int mfsel_lk2;
>>> + unsigned int mfsel_lk3;
>>> + unsigned int mfsel_lk4;
>>> + unsigned int mfsel_lk5;
>>> + unsigned int mfsel_lk6;
>>> + unsigned int mfsel_lk7;
>>> + unsigned int rsvd17[1];
>>> + unsigned int mfsel_set1;
>>> + unsigned int mfsel_set2;
>>> + unsigned int mfsel_set3;
>>> + unsigned int mfsel_set4;
>>> + unsigned int mfsel_set5;
>>> + unsigned int mfsel_set6;
>>> + unsigned int mfsel_set7;
>>> + unsigned int rsvd18[1];
>>> + unsigned int mfsel_clr1;
>>> + unsigned int mfsel_clr2;
>>> + unsigned int mfsel_clr3;
>>> + unsigned int mfsel_clr4;
>>> + unsigned int mfsel_clr5;
>>> + unsigned int mfsel_clr6;
>>> + unsigned int mfsel_clr7;
>>> + };
>>> +
>>> +#endif
>>> diff --git a/arch/arm/include/asm/arch-npcm8xx/gpio.h b/arch/arm/include/asm/arch-npcm8xx/gpio.h
>>> new file mode 100644
>>> index 0000000000..234a1d3de9
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-npcm8xx/gpio.h
>>> @@ -0,0 +1,11 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#ifndef _NPCM_GPIO_H_
>>> +#define _NPCM_GPIO_H_
>>> +
>>> +#define NPCM_GPIO_BA 0xF0010000
>>> +
>>> +#endif
>>> diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
>>> new file mode 100644
>>> index 0000000000..ffaff50fe2
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
>>> @@ -0,0 +1,32 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +
>>> +#ifndef _NPCM_RST_H_
>>> +#define _NPCM_RST_H_
>>> +
>>> +enum reset_type {
>>> + PORST_TYPE = 0x01,
>>> + CORST_TYPE = 0x02,
>>> + WD0RST_TYPE = 0x03,
>>> + SWR1ST_TYPE = 0x04,
>>> + SWR2ST_TYPE = 0x05,
>>> + SWR3ST_TYPE = 0x06,
>>> + SWR4ST_TYPE = 0x07,
>>> + WD1RST_TYPE = 0x08,
>>> + WD2RST_TYPE = 0x09,
>>> + UNKNOWN_TYPE = 0x10,
>>> +};
>>> +
>>> +#define PORST 0x80000000
>>> +#define CORST 0x40000000
>>> +#define WD0RST 0x20000000
>>> +#define SWR1ST 0x10000000
>>> +#define SWR2ST 0x08000000
>>> +#define SWR3ST 0x04000000
>>> +#define SWR4ST 0x02000000
>>> +#define WD1RST 0x01000000
>>> +#define WD2RST 0x00800000
>>> +#define RESSR_MASK 0xff800000
>>> +
>>> +enum reset_type npcm8xx_reset_reason(void);
>>> +
>>> +#endif
>>> diff --git a/arch/arm/mach-nuvoton/Kconfig b/arch/arm/mach-nuvoton/Kconfig
>>> new file mode 100644
>>> index 0000000000..e014dd4b79
>>> --- /dev/null
>>> +++ b/arch/arm/mach-nuvoton/Kconfig
>>> @@ -0,0 +1,24 @@
>>> +if ARCH_NPCM
>>> +
>>> +config SYS_ARCH
>>> + default "arm"
>>> +
>>> +config SYS_TEXT_BASE
>>> + default 0x8000
>>> +
>>> +choice
>>> + prompt "Nuvoton SoC select"
>>> + default ARCH_NPCM8XX
>>> +
>>> +config ARCH_NPCM8XX
>>> + bool "Support Nuvoton NPCM8xx SoC"
>>> + select ARM64
>>> + help
>>> + General support for NPCM8xx BMC (Arbel).
>>> + Nuvoton NPCM8xx BMC is based on the Cortex A35.
>>> +
>>> +endchoice
>>> +
>>> +source "arch/arm/mach-nuvoton/npcm8xx/Kconfig"
>>> +
>>> +endif
>>> diff --git a/arch/arm/mach-nuvoton/Makefile b/arch/arm/mach-nuvoton/Makefile
>>> new file mode 100644
>>> index 0000000000..e75689a1a0
>>> --- /dev/null
>>> +++ b/arch/arm/mach-nuvoton/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
>>> diff --git a/arch/arm/mach-nuvoton/npcm8xx/Kconfig b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
>>> new file mode 100644
>>> index 0000000000..478a046ad5
>>> --- /dev/null
>>> +++ b/arch/arm/mach-nuvoton/npcm8xx/Kconfig
>>> @@ -0,0 +1,18 @@
>>> +if ARCH_NPCM8XX
>>> +
>>> +config SYS_CPU
>>> + default "armv8"
>>> +
>>> +config SYS_SOC
>>> + default "npcm8xx"
>>> +
>>> +config TARGET_ARBEL_EVB
>>> + bool "Arbel-EVB"
>>> + help
>>> + ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
>>> + supports general functions of Basebase Management Controller
>>> + (BMC).
>>> +
>>> +source "board/nuvoton/arbel/Kconfig"
>>> +
>>> +endif
>>> diff --git a/arch/arm/mach-nuvoton/npcm8xx/Makefile b/arch/arm/mach-nuvoton/npcm8xx/Makefile
>>> new file mode 100644
>>> index 0000000000..c62a4aa20a
>>> --- /dev/null
>>> +++ b/arch/arm/mach-nuvoton/npcm8xx/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-y += reset.o cpu.o
>>> diff --git a/arch/arm/mach-nuvoton/npcm8xx/cpu.c b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
>>> new file mode 100644
>>> index 0000000000..8a7315d535
>>> --- /dev/null
>>> +++ b/arch/arm/mach-nuvoton/npcm8xx/cpu.c
>>> @@ -0,0 +1,170 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <cpu_func.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/gcr.h>
>>> +#include <asm/arch/espi.h>
>>> +#include <asm/armv8/mmu.h>
>>> +#include <asm/system.h>
>>> +#include <asm/global_data.h>
>>> +
>>> +/* System Counter */
>>> +struct sctr_regs {
>>> + u32 cntcr;
>>> + u32 cntsr;
>>> + u32 cntcv1;
>>> + u32 cntcv2;
>>> + u32 resv1[4];
>>> + u32 cntfid0;
>>> + u32 cntfid1;
>>> + u32 cntfid2;
>>> + u32 resv2[1001];
>>> + u32 counterid[1];
>>> +};
>>> +
>>> +#define SC_CNTCR_ENABLE BIT(0)
>>> +#define SC_CNTCR_HDBG BIT(1)
>>> +#define SC_CNTCR_FREQ0 BIT(8)
>>> +#define SC_CNTCR_FREQ1 BIT(9)
>>> +
>>> +#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +int print_cpuinfo(void)
>>> +{
>>> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
>>> + unsigned int id = 0;
>>> + unsigned long mpidr_val = 0;
>>> + unsigned int mdlr = 0;
>>> +
>>> + asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
>>> +
>>> + mdlr = readl(&gcr->mdlr);
>>> +
>>> + printf("CPU-%d: ", (unsigned int)(mpidr_val & 0x3));
>>> +
>>> + switch (mdlr) {
>>> + case ARBEL_NPCM845:
>>> + printf("NPCM845 ");
>>> + break;
>>> + case ARBEL_NPCM830:
>>> + printf("NPCM830 ");
>>> + break;
>>> + case ARBEL_NPCM810:
>>> + printf("NPCM810 ");
>>> + break;
>>> + default:
>>> + printf("NPCM8XX ");
>>> + break;
>>> + }
>>> +
>>> + id = readl(&gcr->pdid);
>>> + switch (id) {
>>> + case ARBEL_Z1:
>>> + printf("Z1 @ ");
>>> + break;
>>> + case ARBEL_A1:
>>> + printf("A1 @ ");
>>> + break;
>>> + default:
>>> + printf("Unknown\n");
>>> + break;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void npcm_sysintf_init(void)
>>> +{
>>> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
>>> + u32 espi_ch_supp, val;
>>> +
>>> + espi_ch_supp = ofnode_conf_read_int("espi-channel-support", 0);
>>> +
>>> + if (espi_ch_supp) {
>>> + /* Use eSPI function and initialize ESPICFG */
>>> + u32 hindp = 0x00011110 | espi_ch_supp;
>>> +
>>> + writel((readl(&gcr->mfsel4) | (1 << MFSEL4_ESPISEL)), &gcr->mfsel4);
>>> + writel(hindp, NPCM_ESPI_BA + ESPIHINDP);
>>> + val = readl(NPCM_ESPI_BA + ESPICFG);
>>> + val |= ESPI_IO_MODE_SINGLE_DUAL_QUAD << ESPICFG_IOMODE_SHIFT;
>>> + val |= ESPI_MAX_33_MHZ << ESPICFG_MAXFREQ_SHIFT;
>>> + val |= ((espi_ch_supp & ESPICFG_CHNSUPP_MASK) << ESPICFG_CHNSUPP_SHFT);
>>> + writel(val, NPCM_ESPI_BA + ESPICFG);
>>> + } else {
>>> + /* Use LPC function */
>>> + writel((readl(&gcr->mfsel1) | (1 << MFSEL1_LPCSEL)), &gcr->mfsel1);
>>> + }
>>> +}
>>> +
>>> +int arch_cpu_init(void)
>>> +{
>>> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
>>> +
>>> + if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
>>> + /* enable cache to speed up system running */
>>> + if (get_sctlr() & CR_M)
>>> + return 0;
>>> +
>>> + icache_enable();
>>> + __asm_invalidate_dcache_all();
>>> + __asm_invalidate_tlb_all();
>>> + set_sctlr(get_sctlr() | CR_C);
>>> + }
>>> +
>>> + /* Power voltage select setup */
>>> + setbits_le32(&gcr->vsrcr, BIT(30));
>>> +
>>> + npcm_sysintf_init();
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
>>> + {
>>> + /* DRAM */
>>> + .phys = 0x0UL,
>>> + .virt = 0x0UL,
>>> + .size = 0x80000000UL,
>>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>>> + PTE_BLOCK_INNER_SHARE
>>> + },
>>> + {
>>> + .phys = 0x80000000UL,
>>> + .virt = 0x80000000UL,
>>> + .size = 0x80000000UL,
>>> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>>> + PTE_BLOCK_NON_SHARE |
>>> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
>>> + },
>>> + {
>>> + /* List terminator */
>>> + 0,
>>> + }
>>> +};
>>> +
>>> +struct mm_region *mem_map = npcm_mem_map;
>>> +
>>> +int timer_init(void)
>>> +{
>>> + struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
>>> + unsigned int cntfrq_el0;
>>> +
>>> + __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
>>> + writel(cntfrq_el0, &sctr->cntfid0);
>>> +
>>> + clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
>>> + SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
>>> +
>>> + gd->arch.tbl = 0;
>>> + gd->arch.tbu = 0;
>>> +
>>> + return 0;
>>> +}
>>> diff --git a/arch/arm/mach-nuvoton/npcm8xx/reset.c b/arch/arm/mach-nuvoton/npcm8xx/reset.c
>>> new file mode 100644
>>> index 0000000000..7fbed7ba76
>>> --- /dev/null
>>> +++ b/arch/arm/mach-nuvoton/npcm8xx/reset.c
>>> @@ -0,0 +1,51 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/rst.h>
>>> +#include <asm/arch/gcr.h>
>>> +
>>> +void reset_cpu(void)
>>> +{
>>> + /* Watcdog reset - WTCR register set WTE-BIT7 WTRE-BIT1 WTR-BIT0 */
>>> + writel(0x83, 0xf000801c);
>>> +
>>> + while (1)
>>> + ;
>>> +}
>>> +
>>> +void reset_misc(void)
>>> +{
>>> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
>>> +
>>> + /* clear WDC */
>>> + writel(readl(&gcr->intcr2) & ~(1 << INTCR2_WDC), &gcr->intcr2);
>>> +}
>>> +
>>> +enum reset_type npcm8xx_reset_reason(void)
>>> +{
>>> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
>>> + enum reset_type type = UNKNOWN_TYPE;
>>> + u32 value = readl(&gcr->ressr);
>>> +
>>> + if (value == 0)
>>> + value = ~readl(&gcr->intcr2);
>>> +
>>> + value &= RESSR_MASK;
>>> +
>>> + if (value & CORST)
>>> + type = CORST;
>>> + if (value & WD0RST)
>>> + type = WD0RST;
>>> + if (value & WD1RST)
>>> + type = WD1RST;
>>> + if (value & WD2RST)
>>> + type = WD2RST;
>>> + if (value & PORST)
>>> + type = PORST;
>>> +
>>> + return type;
>>> +}
>>> diff --git a/board/nuvoton/arbel/Kconfig b/board/nuvoton/arbel/Kconfig
>>> new file mode 100644
>>> index 0000000000..4a03ea1abf
>>> --- /dev/null
>>> +++ b/board/nuvoton/arbel/Kconfig
>>> @@ -0,0 +1,18 @@
>>> +if TARGET_ARBEL_EVB
>>> +
>>> +config SYS_BOARD
>>> + default "arbel"
>>> +
>>> +config SYS_VENDOR
>>> + default "nuvoton"
>>> +
>>> +config SYS_CONFIG_NAME
>>> + default "arbel"
>>> +
>>> +config SYS_MEM_TOP_HIDE
>>> + hex "Reserved TOP memory"
>>> + default 0xB000000
>>> + help
>>> + Reserve memory for ECC/GFX/VCD/ECE.
>>> +
>>> +endif
>>> diff --git a/board/nuvoton/arbel/Makefile b/board/nuvoton/arbel/Makefile
>>> new file mode 100644
>>> index 0000000000..f9ad1dea34
>>> --- /dev/null
>>> +++ b/board/nuvoton/arbel/Makefile
>>> @@ -0,0 +1 @@
>>> +obj-y += arbel.o
>>> diff --git a/board/nuvoton/arbel/arbel.c b/board/nuvoton/arbel/arbel.c
>>> new file mode 100644
>>> index 0000000000..86cef98c5f
>>> --- /dev/null
>>> +++ b/board/nuvoton/arbel/arbel.c
>>> @@ -0,0 +1,33 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/gcr.h>
>>> +#include <asm/mach-types.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +int board_init(void)
>>> +{
>>> + gd->bd->bi_arch_number = MACH_TYPE_NPCMX50;
>>> + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100UL);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +int dram_init(void)
>>> +{
>>> + struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
>>> +
>>> + /*
>>> + * get dram active size value from bootblock.
>>> + * Value sent using scrpad_02 register.
>>> + */
>>> + gd->ram_size = readl(&gcr->scrpad_b);
>>> +
>>> + return 0;
>>> +}
>>> diff --git a/include/configs/arbel.h b/include/configs/arbel.h
>>> new file mode 100644
>>> index 0000000000..2cb658c3e6
>>> --- /dev/null
>>> +++ b/include/configs/arbel.h
>>> @@ -0,0 +1,54 @@
>>> +/* SPDX-License-Identifier: GPL-2.0+ */
>>> +/*
>>> + * Copyright (c) 2021 Nuvoton Technology Corp.
>>> + */
>>> +
>>> +#ifndef __CONFIG_ARBEL_H
>>> +#define __CONFIG_ARBEL_H
>>> +
>>> +#define CONFIG_GICV2
>>> +#define GICD_BASE (0xDFFF9000)
>>> +#define GICC_BASE (0xDFFFA000)
>>> +
>>> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
>>> +#define CONFIG_USB_OHCI_NEW
>>> +#define CONFIG_SETUP_MEMORY_TAGS
>>> +#define CONFIG_INITRD_TAG
>>> +#define CONFIG_SYS_MAXARGS 32
>>> +#define CONFIG_SYS_CBSIZE 256
>>> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
>>> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
>>> +#define CONFIG_SYS_BOOTM_LEN (20 << 20)
>>> +#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
>>> +#define CONFIG_SYS_SDRAM_BASE 0x0
>>> +#define CONFIG_SYS_INIT_SP_ADDR (0x00008000 - GENERATED_GBL_DATA_SIZE)
>>> +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
>>> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
>>> +#define CONFIG_BAUDRATE 115200
>>> +#define CONFIG_SYS_HZ 1000
>>> +#define CONFIG_BITBANGMII_MULTI
>>> +
>>> +/* Default environemnt variables */
>>> +#define CONFIG_BOOTCOMMAND "run common_bootargs; run romboot"
>>> +#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
>>> + "stdin=serial\0" \
>>> + "stdout=serial\0" \
>>> + "stderr=serial\0" \
>>> + "ethact=gmac1\0" \
>>> + "autostart=no\0" \
>>> + "ethaddr=00:00:F7:A0:00:FC\0" \
>>> + "eth1addr=00:00:F7:A0:00:FD\0" \
>>> + "eth2addr=00:00:F7:A0:00:FE\0" \
>>> + "eth3addr=00:00:F7:A0:00:FF\0" \
>>> + "gatewayip=192.168.0.17\0" \
>>> + "serverip=192.168.0.17\0" \
>>> + "ipaddr=192.168.0.15\0" \
>>> + "romboot=echo Booting Kernel from flash at 0x${uimage_flash_addr}; " \
>>> + "echo Using bootargs: ${bootargs};bootm ${uimage_flash_addr}\0" \
>>> + "earlycon=uart8250,mmio32,0xf0000000\0" \
>>> + "console=ttyS0,115200n8\0" \
>>> + "common_bootargs=setenv bootargs earlycon=${earlycon} root=/dev/ram " \
>>> + "console=${console} ramdisk_size=48000\0" \
>>> + "\0"
>>> +
>>> +#endif
>>>
>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2022-03-11 1:06 ` Giulio Benetti
@ 2022-03-11 1:07 ` Giulio Benetti
0 siblings, 0 replies; 31+ messages in thread
From: Giulio Benetti @ 2022-03-11 1:07 UTC (permalink / raw)
To: Stanley Chu, Tom Rini; +Cc: kwliu, ctcchien, avifishman70, tmaimon77, u-boot
On 11/03/22 02:06, Giulio Benetti wrote:
> Hi Stanley,
>
> On 11/03/22 01:50, Stanley Chu wrote:
>> Hi Giulio,
>>
>> Thank you for your comment, I've submitted a clk driver patch to address this.
>> https://patchwork.ozlabs.org/project/uboot/patch/20220225075954.3965-1-yschu@nuvoton.com/
>
> Good to see that!
>
> But I think you should submit the entire patchset:
> https://patchwork.ozlabs.org/project/uboot/list/?series=276836&state=%2A&archive=both
>
> including this patch as V2. Otherwise it's difficult to test it.
>
> As you see in Patchwork you have superseded and changes requested on
> other patches. So you should modify them accordingly and send V2 series.
> If other patches have been applied then send only the ones not applied.
> But as I can see here they are still not applied.
Ah, forgotten to mention, please add me and other people involved in
reviewing in Cc for V2.
Thank you!
Best regards
--
Giulio Benetti
Benetti Engineering sas
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2022-03-10 18:49 ` Tom Rini
@ 2022-03-11 2:13 ` Stanley Chu
2022-03-11 2:50 ` Tom Rini
2022-03-11 2:53 ` Giulio Benetti
0 siblings, 2 replies; 31+ messages in thread
From: Stanley Chu @ 2022-03-11 2:13 UTC (permalink / raw)
To: Tom Rini, Stanley Chu; +Cc: kwliu, ctcchien, avifishman70, tmaimon77, u-boot
Hi Tom,
We need time to prepare linux dts, can I send the rest of the drivers
first or need to wait until the linux dts is submitted?
Because I want to remove some unused nodes/properties away from linux
dts to reduce dtb size, can we use different dts for uboot?
Thanks a lot for your comments.
--
Stanley
On Fri, Mar 11, 2022 at 2:49 AM Tom Rini <trini@konsulko.com> wrote:
>
> On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote:
>
> > Add basic support for the Nuvoton NPCM845 BMC.
> >
> > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
>
> I see there's a number of outstanding questions to this first part of
> the port. Can you please address them? Furthermore, the defconfig and
> dts patches should be part of this first patch and the dts needs to be
> in linux-next at least, if not a full linux kernel release. Thanks and
> sorry for the delay here.
>
> --
> Tom
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2022-03-11 2:13 ` Stanley Chu
@ 2022-03-11 2:50 ` Tom Rini
2022-03-11 2:53 ` Giulio Benetti
1 sibling, 0 replies; 31+ messages in thread
From: Tom Rini @ 2022-03-11 2:50 UTC (permalink / raw)
To: Stanley Chu; +Cc: Stanley Chu, kwliu, ctcchien, avifishman70, tmaimon77, u-boot
[-- Attachment #1: Type: text/plain, Size: 1179 bytes --]
On Fri, Mar 11, 2022 at 10:13:19AM +0800, Stanley Chu wrote:
> Hi Tom,
> We need time to prepare linux dts, can I send the rest of the drivers
> first or need to wait until the linux dts is submitted?
> Because I want to remove some unused nodes/properties away from linux
> dts to reduce dtb size, can we use different dts for uboot?
> Thanks a lot for your comments.
The dts should be the same, except for any U-Boot specific bindings that
we're still working to upstream, between Linux and U-Boot.
>
> --
> Stanley
>
> On Fri, Mar 11, 2022 at 2:49 AM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote:
> >
> > > Add basic support for the Nuvoton NPCM845 BMC.
> > >
> > > Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> >
> > I see there's a number of outstanding questions to this first part of
> > the port. Can you please address them? Furthermore, the defconfig and
> > dts patches should be part of this first patch and the dts needs to be
> > in linux-next at least, if not a full linux kernel release. Thanks and
> > sorry for the delay here.
> >
> > --
> > Tom
--
Tom
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2022-03-11 2:13 ` Stanley Chu
2022-03-11 2:50 ` Tom Rini
@ 2022-03-11 2:53 ` Giulio Benetti
2022-03-11 4:07 ` Stanley Chu
1 sibling, 1 reply; 31+ messages in thread
From: Giulio Benetti @ 2022-03-11 2:53 UTC (permalink / raw)
To: Stanley Chu
Cc: Tom Rini, Stanley Chu, kwliu, ctcchien, avifishman70, tmaimon77, u-boot
Hi Stanley,
> Il giorno 11 mar 2022, alle ore 03:13, Stanley Chu <stanley.chuys@gmail.com> ha scritto:
>
> Hi Tom,
> We need time to prepare linux dts, can I send the rest of the drivers
> first or need to wait until the linux dts is submitted?
> Because I want to remove some unused nodes/properties away from linux
> dts to reduce dtb size, can we use different dts for uboot?
You can add a specific -uboot.dtsi file where you tag every node to be or not to be part of final uboot .dtb
This way the original .dts file will be synced with Linux, except the -uboot.dtsi inclusion.
Take a look at upstreamed .dts files and look for uboot.dtsi suffix files.
Best regards
—-
Giulio Benetti
Benetti Engineering sas
> Thanks a lot for your comments.
>
> --
> Stanley
>
>> On Fri, Mar 11, 2022 at 2:49 AM Tom Rini <trini@konsulko.com> wrote:
>>
>>> On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote:
>>>
>>> Add basic support for the Nuvoton NPCM845 BMC.
>>>
>>> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
>>
>> I see there's a number of outstanding questions to this first part of
>> the port. Can you please address them? Furthermore, the defconfig and
>> dts patches should be part of this first patch and the dts needs to be
>> in linux-next at least, if not a full linux kernel release. Thanks and
>> sorry for the delay here.
>>
>> --
>> Tom
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC
2022-03-11 2:53 ` Giulio Benetti
@ 2022-03-11 4:07 ` Stanley Chu
0 siblings, 0 replies; 31+ messages in thread
From: Stanley Chu @ 2022-03-11 4:07 UTC (permalink / raw)
To: Giulio Benetti
Cc: Tom Rini, Stanley Chu, kwliu, ctcchien, avifishman70, tmaimon77, u-boot
On Fri, Mar 11, 2022 at 10:53 AM Giulio Benetti
<giulio.benetti@benettiengineering.com> wrote:
>
> Hi Stanley,
>
> > Il giorno 11 mar 2022, alle ore 03:13, Stanley Chu <stanley.chuys@gmail.com> ha scritto:
> >
> > Hi Tom,
> > We need time to prepare linux dts, can I send the rest of the drivers
> > first or need to wait until the linux dts is submitted?
> > Because I want to remove some unused nodes/properties away from linux
> > dts to reduce dtb size, can we use different dts for uboot?
>
> You can add a specific -uboot.dtsi file where you tag every node to be or not to be part of final uboot .dtb
> This way the original .dts file will be synced with Linux, except the -uboot.dtsi inclusion.
> Take a look at upstreamed .dts files and look for uboot.dtsi suffix files.
Hi Giulio,
Thanks a lot.
It will be done in v2.
--
Stanley
>
> Best regards
> —-
> Giulio Benetti
> Benetti Engineering sas
>
> > Thanks a lot for your comments.
> >
> > --
> > Stanley
> >
> >> On Fri, Mar 11, 2022 at 2:49 AM Tom Rini <trini@konsulko.com> wrote:
> >>
> >>> On Wed, Dec 15, 2021 at 10:57:52AM +0800, Stanley Chu wrote:
> >>>
> >>> Add basic support for the Nuvoton NPCM845 BMC.
> >>>
> >>> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
> >>
> >> I see there's a number of outstanding questions to this first part of
> >> the port. Can you please address them? Furthermore, the defconfig and
> >> dts patches should be part of this first patch and the dts needs to be
> >> in linux-next at least, if not a full linux kernel release. Thanks and
> >> sorry for the delay here.
> >>
> >> --
> >> Tom
>
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2022-03-11 4:07 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-15 2:57 [PATCH v1 0/9] Add Nuvoton NPCM845 support Stanley Chu
2021-12-15 2:57 ` [PATCH v1 1/9] arm: nuvoton: Add support for Nuvoton NPCM845 BMC Stanley Chu
2021-12-15 12:12 ` Giulio Benetti
2022-03-11 0:50 ` Stanley Chu
2022-03-11 1:06 ` Giulio Benetti
2022-03-11 1:07 ` Giulio Benetti
2021-12-15 18:32 ` Sean Anderson
2022-03-11 0:55 ` Stanley Chu
[not found] ` <d23d2925-d5ea-e23b-fb99-7856aedfb328@gmail.com>
[not found] ` <0fee2e28-b3c8-d649-0921-52e6fb098e71@gmail.com>
2022-03-11 0:39 ` Stanley Chu
2022-03-11 0:57 ` Stanley Chu
2022-03-10 18:49 ` Tom Rini
2022-03-11 2:13 ` Stanley Chu
2022-03-11 2:50 ` Tom Rini
2022-03-11 2:53 ` Giulio Benetti
2022-03-11 4:07 ` Stanley Chu
2021-12-15 2:57 ` [PATCH v1 2/9] clk: nuvoton: Add support for NPCM845 Stanley Chu
2021-12-15 18:32 ` Sean Anderson
2022-02-16 16:25 ` Tom Rini
2022-02-17 2:08 ` Stanley
2021-12-15 2:57 ` [PATCH v1 3/9] timer: npcm: Add NPCM timer support Stanley Chu
2021-12-15 2:57 ` [PATCH v1 4/9] serial: npcm: Add support for Nuvoton NPCM SoCs Stanley Chu
2021-12-15 2:57 ` [PATCH v1 5/9] gpio: " Stanley Chu
2021-12-15 2:57 ` [PATCH v1 6/9] pinctrl: nuvoton: Add NPCM8xx pinctrl driver Stanley Chu
2021-12-15 2:57 ` [PATCH v1 7/9] spi: npcm-fiu: add NPCM8xx FIU controller driver Stanley Chu
2021-12-15 2:57 ` [PATCH v1 8/9] ARM: dts: Add Nuvoton NPCM845 device tree Stanley Chu
2021-12-15 13:07 ` Tom Rini
2021-12-15 13:32 ` 盛
2021-12-15 13:35 ` Tom Rini
2021-12-15 15:32 ` Jesse Taube
2021-12-15 15:39 ` Tom Rini
2021-12-15 2:58 ` [PATCH v1 9/9] ARM: configs: Add defconfig for Nuvoton NPCM845 Stanley Chu
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