[virtio-dev] Re: [virtio-comment] Re: [PATCH 09/11] transport-pci: Describe PCI MMR dev config registers

[Jason Wang <jasowang@redhat.com>]

On Tue, Apr 18, 2023 at 4:29 AM Parav Pandit <parav@nvidia.com> wrote:
>
>
> > From: Michael S. Tsirkin <mst@redhat.com>
> > Sent: Monday, April 17, 2023 4:27 PM
> > On Mon, Apr 17, 2023 at 05:23:30PM +0000, Parav Pandit wrote:
> > > > Things might be simplified if we use separate queues for admin,
> > > > transport and legacy.
> > > >
> > > Do you mean say we have three AQs, AQ_1, AQ_2, and AQ_3;
> > > AQ_1 of the PF used by admin work as SIOV device create, SRIOV MSIX
> > configuration.
> > > AQ_2 of the PF used for transporting legacy config access of the PCI
> > > VF
> > > AQ_3 of the PF for some transport work.
> > >
> > > If yes, sounds find to me.
> >
> > Latest proposal simply leaves the split between AQs up to the driver.
> > Seems the most flexible.
> Yes. It is. Different opcode range and multiple AQs enable to do so.

Right, so it would be some facility that makes the transport commands
of modern and legacy are mutually exclusive.

Thanks

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