From: "Jan Beulich" <JBeulich@suse.com>
To: xen-devel <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: [PATCH 2/2] hvmloader: don't hard-code IO-APIC parameters
Date: Thu, 16 Jun 2016 03:40:43 -0600 [thread overview]
Message-ID: <5762903B02000078000F597E@prv-mh.provo.novell.com> (raw)
In-Reply-To: <57628EA302000078000F596B@prv-mh.provo.novell.com>
[-- Attachment #1: Type: text/plain, Size: 3222 bytes --]
The IO-APIC address has variable bits determined by the PCI-to-ISA
bridge, and the IO-APIC version should be read from the IO-APIC. (Note
that there's still implicit rather than explicit agreement on the
IO-APIC base address between qemu and the hypervisor.)
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/tools/firmware/hvmloader/acpi/build.c
+++ b/tools/firmware/hvmloader/acpi/build.c
@@ -138,7 +138,7 @@ static struct acpi_20_madt *construct_ma
io_apic->type = ACPI_IO_APIC;
io_apic->length = sizeof(*io_apic);
io_apic->ioapic_id = IOAPIC_ID;
- io_apic->ioapic_addr = IOAPIC_BASE_ADDRESS;
+ io_apic->ioapic_addr = ioapic_base_address;
lapic = (struct acpi_20_madt_lapic *)(io_apic + 1);
info->nr_cpus = hvm_info->nr_vcpus;
--- a/tools/firmware/hvmloader/config.h
+++ b/tools/firmware/hvmloader/config.h
@@ -42,9 +42,10 @@ extern struct bios_config ovmf_config;
#define PAGE_SHIFT 12
#define PAGE_SIZE (1ul << PAGE_SHIFT)
-#define IOAPIC_BASE_ADDRESS 0xfec00000
+extern uint32_t ioapic_base_address;
+extern uint8_t ioapic_version;
+
#define IOAPIC_ID 0x01
-#define IOAPIC_VERSION 0x11
#define LAPIC_BASE_ADDRESS 0xfee00000
#define LAPIC_ID(vcpu_id) ((vcpu_id) * 2)
--- a/tools/firmware/hvmloader/hvmloader.c
+++ b/tools/firmware/hvmloader/hvmloader.c
@@ -108,6 +108,9 @@ asm (
unsigned long scratch_start = SCRATCH_PHYSICAL_ADDRESS;
+uint32_t ioapic_base_address = 0xfec00000;
+uint8_t ioapic_version;
+
static void init_hypercalls(void)
{
uint32_t eax, ebx, ecx, edx;
@@ -185,6 +188,9 @@ static void init_vm86_tss(void)
static void apic_setup(void)
{
+ ioapic_base_address |= (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << 10;
+ ioapic_version = ioapic_read(0x01) & 0xff;
+
/* Set the IOAPIC ID to the static value used in the MP/ACPI tables. */
ioapic_write(0x00, IOAPIC_ID);
--- a/tools/firmware/hvmloader/mp_tables.c
+++ b/tools/firmware/hvmloader/mp_tables.c
@@ -227,9 +227,9 @@ static void fill_mp_ioapic_entry(struct
{
mpie->type = ENTRY_TYPE_IOAPIC;
mpie->ioapic_id = IOAPIC_ID;
- mpie->ioapic_version = IOAPIC_VERSION;
+ mpie->ioapic_version = ioapic_version;
mpie->ioapic_flags = 1; /* enabled */
- mpie->ioapic_addr = IOAPIC_BASE_ADDRESS;
+ mpie->ioapic_addr = ioapic_base_address;
}
--- a/tools/firmware/hvmloader/util.c
+++ b/tools/firmware/hvmloader/util.c
@@ -490,14 +490,14 @@ void *scratch_alloc(uint32_t size, uint3
uint32_t ioapic_read(uint32_t reg)
{
- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg;
- return *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10);
+ *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg;
+ return *(volatile uint32_t *)(ioapic_base_address + 0x10);
}
void ioapic_write(uint32_t reg, uint32_t val)
{
- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg;
- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) = val;
+ *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg;
+ *(volatile uint32_t *)(ioapic_base_address + 0x10) = val;
}
uint32_t lapic_read(uint32_t reg)
[-- Attachment #2: hvmloader-IOAPIC-settings.patch --]
[-- Type: text/plain, Size: 3265 bytes --]
hvmloader: don't hard-code IO-APIC parameters
The IO-APIC address has variable bits determined by the PCI-to-ISA
bridge, and the IO-APIC version should be read from the IO-APIC. (Note
that there's still implicit rather than explicit agreement on the
IO-APIC base address between qemu and the hypervisor.)
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/tools/firmware/hvmloader/acpi/build.c
+++ b/tools/firmware/hvmloader/acpi/build.c
@@ -138,7 +138,7 @@ static struct acpi_20_madt *construct_ma
io_apic->type = ACPI_IO_APIC;
io_apic->length = sizeof(*io_apic);
io_apic->ioapic_id = IOAPIC_ID;
- io_apic->ioapic_addr = IOAPIC_BASE_ADDRESS;
+ io_apic->ioapic_addr = ioapic_base_address;
lapic = (struct acpi_20_madt_lapic *)(io_apic + 1);
info->nr_cpus = hvm_info->nr_vcpus;
--- a/tools/firmware/hvmloader/config.h
+++ b/tools/firmware/hvmloader/config.h
@@ -42,9 +42,10 @@ extern struct bios_config ovmf_config;
#define PAGE_SHIFT 12
#define PAGE_SIZE (1ul << PAGE_SHIFT)
-#define IOAPIC_BASE_ADDRESS 0xfec00000
+extern uint32_t ioapic_base_address;
+extern uint8_t ioapic_version;
+
#define IOAPIC_ID 0x01
-#define IOAPIC_VERSION 0x11
#define LAPIC_BASE_ADDRESS 0xfee00000
#define LAPIC_ID(vcpu_id) ((vcpu_id) * 2)
--- a/tools/firmware/hvmloader/hvmloader.c
+++ b/tools/firmware/hvmloader/hvmloader.c
@@ -108,6 +108,9 @@ asm (
unsigned long scratch_start = SCRATCH_PHYSICAL_ADDRESS;
+uint32_t ioapic_base_address = 0xfec00000;
+uint8_t ioapic_version;
+
static void init_hypercalls(void)
{
uint32_t eax, ebx, ecx, edx;
@@ -185,6 +188,9 @@ static void init_vm86_tss(void)
static void apic_setup(void)
{
+ ioapic_base_address |= (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << 10;
+ ioapic_version = ioapic_read(0x01) & 0xff;
+
/* Set the IOAPIC ID to the static value used in the MP/ACPI tables. */
ioapic_write(0x00, IOAPIC_ID);
--- a/tools/firmware/hvmloader/mp_tables.c
+++ b/tools/firmware/hvmloader/mp_tables.c
@@ -227,9 +227,9 @@ static void fill_mp_ioapic_entry(struct
{
mpie->type = ENTRY_TYPE_IOAPIC;
mpie->ioapic_id = IOAPIC_ID;
- mpie->ioapic_version = IOAPIC_VERSION;
+ mpie->ioapic_version = ioapic_version;
mpie->ioapic_flags = 1; /* enabled */
- mpie->ioapic_addr = IOAPIC_BASE_ADDRESS;
+ mpie->ioapic_addr = ioapic_base_address;
}
--- a/tools/firmware/hvmloader/util.c
+++ b/tools/firmware/hvmloader/util.c
@@ -490,14 +490,14 @@ void *scratch_alloc(uint32_t size, uint3
uint32_t ioapic_read(uint32_t reg)
{
- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg;
- return *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10);
+ *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg;
+ return *(volatile uint32_t *)(ioapic_base_address + 0x10);
}
void ioapic_write(uint32_t reg, uint32_t val)
{
- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x00) = reg;
- *(volatile uint32_t *)(IOAPIC_BASE_ADDRESS + 0x10) = val;
+ *(volatile uint32_t *)(ioapic_base_address + 0x00) = reg;
+ *(volatile uint32_t *)(ioapic_base_address + 0x10) = val;
}
uint32_t lapic_read(uint32_t reg)
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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next prev parent reply other threads:[~2016-06-16 9:40 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-16 9:33 [PATCH 0/2] x86: hvmloader improvements Jan Beulich
2016-06-16 9:40 ` [PATCH 1/2] hvmloader: limit CPUs exposed to guests Jan Beulich
2016-06-16 15:09 ` Boris Ostrovsky
2016-06-16 15:25 ` Jan Beulich
2016-06-16 15:37 ` Boris Ostrovsky
2016-06-16 16:04 ` Jan Beulich
2016-06-16 16:38 ` Boris Ostrovsky
2016-06-17 9:40 ` Andrew Cooper
2016-06-16 9:40 ` Jan Beulich [this message]
2016-06-16 16:49 ` [PATCH 2/2] hvmloader: don't hard-code IO-APIC parameters Boris Ostrovsky
2016-06-17 6:00 ` Jan Beulich
2016-06-17 11:51 ` Boris Ostrovsky
2016-06-17 14:26 ` Jan Beulich
2016-06-17 10:05 ` Andrew Cooper
2016-06-17 10:23 ` Jan Beulich
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