Re: Ping: [PATCH 0/5] x86: more power-efficient CPU parking

From: "Jan Beulich" <JBeulich@suse.com>
To: Brian Woods <brian.woods@amd.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
	Kevin Tian <kevin.tian@intel.com>,
	Jun Nakajima <jun.nakajima@intel.com>
Subject: Re: Ping: [PATCH 0/5] x86: more power-efficient CPU parking
Date: Thu, 30 Aug 2018 01:29:47 -0600	[thread overview]
Message-ID: <5B879CEB02000078001E3584@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <0a2bdb90-fee3-895c-c40c-b4bfe03e5112@citrix.com>

>>> On 29.08.18 at 19:01, <andrew.cooper3@citrix.com> wrote:
> On 29/08/18 08:08, Jan Beulich wrote:
>>>>> On 01.08.18 at 16:22,  wrote:
>>> When putting CPUs to sleep permanently, we should try to put them into
>>> the most power conserving state possible. For now it is unclear whether,
>>> especially in a deep C-state, the P-state also matters, so this series only
>>> arranges for the C-state side of things (plus some cleanup).
>>>
>>> 1: x86/cpuidle: replace a pointless NULL check
>>> 2: x86/idle: re-arrange dead-idle handling
>>> 3: x86/cpuidle: push parked CPUs into deeper sleep states when possible
>>> 4: x86/cpuidle: clean up Cx dumping
>>> 5: x86: place non-parked CPUs into wait-for-SIPI state after offlining
> 
> I don't have a problem in principle, but I'm afraid that you're going to
> need either positive documentation, or a positive statement from Intel
> and AMD that wait-for-SIPI is the most power efficient state to park a
> CPU in.
> 
> At a guess, I'd expect that wait-for-SIPI isn't an optimised state
> (because the vendors wouldn't expect hardware to be in this state after
> boot), and from the various discussions around L1TF, there are
> definitely differences between wait-for-SIPI and mwait.

Well, that's a comment on patch 5 alone, which for that very reason
I've put last in the series. Do I imply your response to mean patches
2 and 3 can have your ack (4 already has and 1 has already gone in)?

Also you're comparing to MWAIT, but such CPUs would more likely get
put in a loop over HLT (as patch 5's description also says). That's
(part of) the background of why I'd like AMD to provide data to enable
mwait-idle for their CPUs.

As to the actual question raised: AMD (first and foremost), Intel?

Jan

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