* [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs
@ 2021-04-15 10:04 Igor Druzhinin
2021-04-15 10:04 ` [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Igor Druzhinin @ 2021-04-15 10:04 UTC (permalink / raw)
To: xen-devel
Cc: jun.nakajima, kevin.tian, jbeulich, andrew.cooper3, roger.pau,
wl, Igor Druzhinin
This MSR exists since Nehalem / Silvermont and is actively used by Linux,
for instance, to improve sampling efficiency.
Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
---
Changes in v5:
- added Silvermont+ LBR_SELECT support
New patch in v4 as suggested by Andrew.
---
xen/arch/x86/hvm/vmx/vmx.c | 20 ++++++++++++++++----
xen/include/asm-x86/msr-index.h | 10 ++++++++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 835b905..30c6a57 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2915,14 +2915,16 @@ static const struct lbr_info {
}, nh_lbr[] = {
{ MSR_IA32_LASTINTFROMIP, 1 },
{ MSR_IA32_LASTINTTOIP, 1 },
- { MSR_C2_LASTBRANCH_TOS, 1 },
+ { MSR_NHL_LBR_SELECT, 1 },
+ { MSR_NHL_LASTBRANCH_TOS, 1 },
{ MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
{ MSR_P4_LASTBRANCH_0_TO_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
{ 0, 0 }
}, sk_lbr[] = {
{ MSR_IA32_LASTINTFROMIP, 1 },
{ MSR_IA32_LASTINTTOIP, 1 },
- { MSR_SKL_LASTBRANCH_TOS, 1 },
+ { MSR_NHL_LBR_SELECT, 1 },
+ { MSR_NHL_LASTBRANCH_TOS, 1 },
{ MSR_SKL_LASTBRANCH_0_FROM_IP, NUM_MSR_SKL_LASTBRANCH },
{ MSR_SKL_LASTBRANCH_0_TO_IP, NUM_MSR_SKL_LASTBRANCH },
{ MSR_SKL_LASTBRANCH_0_INFO, NUM_MSR_SKL_LASTBRANCH },
@@ -2934,10 +2936,19 @@ static const struct lbr_info {
{ MSR_C2_LASTBRANCH_0_FROM_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
{ MSR_C2_LASTBRANCH_0_TO_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
{ 0, 0 }
+}, sm_lbr[] = {
+ { MSR_IA32_LASTINTFROMIP, 1 },
+ { MSR_IA32_LASTINTTOIP, 1 },
+ { MSR_SM_LBR_SELECT, 1 },
+ { MSR_SM_LASTBRANCH_TOS, 1 },
+ { MSR_C2_LASTBRANCH_0_FROM_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
+ { MSR_C2_LASTBRANCH_0_TO_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
+ { 0, 0 }
}, gm_lbr[] = {
{ MSR_IA32_LASTINTFROMIP, 1 },
{ MSR_IA32_LASTINTTOIP, 1 },
- { MSR_GM_LASTBRANCH_TOS, 1 },
+ { MSR_SM_LBR_SELECT, 1 },
+ { MSR_SM_LASTBRANCH_TOS, 1 },
{ MSR_GM_LASTBRANCH_0_FROM_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO },
{ MSR_GM_LASTBRANCH_0_TO_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO },
{ 0, 0 }
@@ -2991,6 +3002,7 @@ static const struct lbr_info *last_branch_msr_get(void)
return sk_lbr;
/* Atom */
case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36:
+ return at_lbr;
/* Silvermont */
case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d:
/* Xeon Phi Knights Landing */
@@ -2999,7 +3011,7 @@ static const struct lbr_info *last_branch_msr_get(void)
case 0x85:
/* Airmont */
case 0x4c:
- return at_lbr;
+ return sm_lbr;
/* Goldmont */
case 0x5c: case 0x5f:
return gm_lbr;
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 43d26ef..020908f 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -606,15 +606,21 @@
#define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
+/* Nehalem (and newer) last-branch recording */
+#define MSR_NHL_LBR_SELECT 0x000001c8
+#define MSR_NHL_LASTBRANCH_TOS 0x000001c9
+
/* Skylake (and newer) last-branch recording */
-#define MSR_SKL_LASTBRANCH_TOS 0x000001c9
#define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680
#define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0
#define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0
#define NUM_MSR_SKL_LASTBRANCH 32
+/* Silvermont (and newer) last-branch recording */
+#define MSR_SM_LBR_SELECT 0x000001c8
+#define MSR_SM_LASTBRANCH_TOS 0x000001c9
+
/* Goldmont last-branch recording */
-#define MSR_GM_LASTBRANCH_TOS 0x000001c9
#define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680
#define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0
#define NUM_MSR_GM_LASTBRANCH_FROM_TO 32
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers
2021-04-15 10:04 [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
@ 2021-04-15 10:04 ` Igor Druzhinin
2021-04-25 1:07 ` Tian, Kevin
2021-04-15 11:50 ` [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Jan Beulich
2021-04-25 1:07 ` Tian, Kevin
2 siblings, 1 reply; 5+ messages in thread
From: Igor Druzhinin @ 2021-04-15 10:04 UTC (permalink / raw)
To: xen-devel
Cc: jun.nakajima, kevin.tian, jbeulich, andrew.cooper3, roger.pau,
wl, Igor Druzhinin
LBR, C-state MSRs should correspond to Ice Lake desktop according to
SDM rev. 74 for both models.
Ice Lake-SP is known to expose IF_PSCHANGE_MC_NO in IA32_ARCH_CAPABILITIES MSR
(as advisory tells and Whitley SDP confirms) which means the erratum is fixed
in hardware for that model and therefore it shouldn't be present in
has_if_pschange_mc list. Provisionally assume the same to be the case
for Ice Lake-D.
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
---
No changes in v5.
Changes in v4:
- now based on SDM update
- new LBR (0x1e0)does not seem to be exposed in the docs
Changes in v3:
- Add Ice Lake-D model numbers
- Drop has_if_pschange_mc hunk following Tiger Lake related discussion
---
xen/arch/x86/acpi/cpu_idle.c | 2 ++
xen/arch/x86/hvm/vmx/vmx.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index c092086..d788c8b 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -181,6 +181,8 @@ static void do_get_hw_residencies(void *arg)
case 0x55:
case 0x5E:
/* Ice Lake */
+ case 0x6A:
+ case 0x6C:
case 0x7D:
case 0x7E:
/* Tiger Lake */
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 30c6a57..91cba19 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2990,7 +2990,7 @@ static const struct lbr_info *last_branch_msr_get(void)
/* Goldmont Plus */
case 0x7a:
/* Ice Lake */
- case 0x7d: case 0x7e:
+ case 0x6a: case 0x6c: case 0x7d: case 0x7e:
/* Tiger Lake */
case 0x8c: case 0x8d:
/* Tremont */
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* RE: [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers
2021-04-15 10:04 ` [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
@ 2021-04-25 1:07 ` Tian, Kevin
0 siblings, 0 replies; 5+ messages in thread
From: Tian, Kevin @ 2021-04-25 1:07 UTC (permalink / raw)
To: Igor Druzhinin, xen-devel
Cc: Nakajima, Jun, jbeulich, Cooper, Andrew, roger.pau, wl
> From: Igor Druzhinin <igor.druzhinin@citrix.com>
> Sent: Thursday, April 15, 2021 6:04 PM
>
> LBR, C-state MSRs should correspond to Ice Lake desktop according to
> SDM rev. 74 for both models.
>
> Ice Lake-SP is known to expose IF_PSCHANGE_MC_NO in
> IA32_ARCH_CAPABILITIES MSR
> (as advisory tells and Whitley SDP confirms) which means the erratum is
> fixed
> in hardware for that model and therefore it shouldn't be present in
> has_if_pschange_mc list. Provisionally assume the same to be the case
> for Ice Lake-D.
>
> Reviewed-by: Jan Beulich <jbeulich@suse.com>
> Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
> ---
> No changes in v5.
>
> Changes in v4:
> - now based on SDM update
> - new LBR (0x1e0)does not seem to be exposed in the docs
>
> Changes in v3:
> - Add Ice Lake-D model numbers
> - Drop has_if_pschange_mc hunk following Tiger Lake related discussion
> ---
> xen/arch/x86/acpi/cpu_idle.c | 2 ++
> xen/arch/x86/hvm/vmx/vmx.c | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
> index c092086..d788c8b 100644
> --- a/xen/arch/x86/acpi/cpu_idle.c
> +++ b/xen/arch/x86/acpi/cpu_idle.c
> @@ -181,6 +181,8 @@ static void do_get_hw_residencies(void *arg)
> case 0x55:
> case 0x5E:
> /* Ice Lake */
> + case 0x6A:
> + case 0x6C:
> case 0x7D:
> case 0x7E:
> /* Tiger Lake */
> diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
> index 30c6a57..91cba19 100644
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2990,7 +2990,7 @@ static const struct lbr_info
> *last_branch_msr_get(void)
> /* Goldmont Plus */
> case 0x7a:
> /* Ice Lake */
> - case 0x7d: case 0x7e:
> + case 0x6a: case 0x6c: case 0x7d: case 0x7e:
> /* Tiger Lake */
> case 0x8c: case 0x8d:
> /* Tremont */
> --
> 2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs
2021-04-15 10:04 [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
2021-04-15 10:04 ` [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
@ 2021-04-15 11:50 ` Jan Beulich
2021-04-25 1:07 ` Tian, Kevin
2 siblings, 0 replies; 5+ messages in thread
From: Jan Beulich @ 2021-04-15 11:50 UTC (permalink / raw)
To: Igor Druzhinin, xen-devel
Cc: jun.nakajima, kevin.tian, andrew.cooper3, roger.pau, wl
On 15.04.2021 12:04, Igor Druzhinin wrote:
> This MSR exists since Nehalem / Silvermont and is actively used by Linux,
> for instance, to improve sampling efficiency.
>
> Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs
2021-04-15 10:04 [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
2021-04-15 10:04 ` [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
2021-04-15 11:50 ` [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Jan Beulich
@ 2021-04-25 1:07 ` Tian, Kevin
2 siblings, 0 replies; 5+ messages in thread
From: Tian, Kevin @ 2021-04-25 1:07 UTC (permalink / raw)
To: Igor Druzhinin, xen-devel
Cc: Nakajima, Jun, jbeulich, Cooper, Andrew, roger.pau, wl
> From: Igor Druzhinin <igor.druzhinin@citrix.com>
> Sent: Thursday, April 15, 2021 6:04 PM
>
> This MSR exists since Nehalem / Silvermont and is actively used by Linux,
> for instance, to improve sampling efficiency.
>
> Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
> ---
> Changes in v5:
> - added Silvermont+ LBR_SELECT support
>
> New patch in v4 as suggested by Andrew.
> ---
> xen/arch/x86/hvm/vmx/vmx.c | 20 ++++++++++++++++----
> xen/include/asm-x86/msr-index.h | 10 ++++++++--
> 2 files changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
> index 835b905..30c6a57 100644
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2915,14 +2915,16 @@ static const struct lbr_info {
> }, nh_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_C2_LASTBRANCH_TOS, 1 },
> + { MSR_NHL_LBR_SELECT, 1 },
> + { MSR_NHL_LASTBRANCH_TOS, 1 },
> { MSR_P4_LASTBRANCH_0_FROM_LIP,
> NUM_MSR_P4_LASTBRANCH_FROM_TO },
> { MSR_P4_LASTBRANCH_0_TO_LIP,
> NUM_MSR_P4_LASTBRANCH_FROM_TO },
> { 0, 0 }
> }, sk_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_SKL_LASTBRANCH_TOS, 1 },
> + { MSR_NHL_LBR_SELECT, 1 },
> + { MSR_NHL_LASTBRANCH_TOS, 1 },
> { MSR_SKL_LASTBRANCH_0_FROM_IP, NUM_MSR_SKL_LASTBRANCH },
> { MSR_SKL_LASTBRANCH_0_TO_IP, NUM_MSR_SKL_LASTBRANCH },
> { MSR_SKL_LASTBRANCH_0_INFO, NUM_MSR_SKL_LASTBRANCH },
> @@ -2934,10 +2936,19 @@ static const struct lbr_info {
> { MSR_C2_LASTBRANCH_0_FROM_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> { MSR_C2_LASTBRANCH_0_TO_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> { 0, 0 }
> +}, sm_lbr[] = {
> + { MSR_IA32_LASTINTFROMIP, 1 },
> + { MSR_IA32_LASTINTTOIP, 1 },
> + { MSR_SM_LBR_SELECT, 1 },
> + { MSR_SM_LASTBRANCH_TOS, 1 },
> + { MSR_C2_LASTBRANCH_0_FROM_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> + { MSR_C2_LASTBRANCH_0_TO_IP,
> NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> + { 0, 0 }
> }, gm_lbr[] = {
> { MSR_IA32_LASTINTFROMIP, 1 },
> { MSR_IA32_LASTINTTOIP, 1 },
> - { MSR_GM_LASTBRANCH_TOS, 1 },
> + { MSR_SM_LBR_SELECT, 1 },
> + { MSR_SM_LASTBRANCH_TOS, 1 },
> { MSR_GM_LASTBRANCH_0_FROM_IP,
> NUM_MSR_GM_LASTBRANCH_FROM_TO },
> { MSR_GM_LASTBRANCH_0_TO_IP,
> NUM_MSR_GM_LASTBRANCH_FROM_TO },
> { 0, 0 }
> @@ -2991,6 +3002,7 @@ static const struct lbr_info
> *last_branch_msr_get(void)
> return sk_lbr;
> /* Atom */
> case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36:
> + return at_lbr;
> /* Silvermont */
> case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d:
> /* Xeon Phi Knights Landing */
> @@ -2999,7 +3011,7 @@ static const struct lbr_info
> *last_branch_msr_get(void)
> case 0x85:
> /* Airmont */
> case 0x4c:
> - return at_lbr;
> + return sm_lbr;
> /* Goldmont */
> case 0x5c: case 0x5f:
> return gm_lbr;
> diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-
> index.h
> index 43d26ef..020908f 100644
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -606,15 +606,21 @@
> #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
> #define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
>
> +/* Nehalem (and newer) last-branch recording */
> +#define MSR_NHL_LBR_SELECT 0x000001c8
> +#define MSR_NHL_LASTBRANCH_TOS 0x000001c9
> +
> /* Skylake (and newer) last-branch recording */
> -#define MSR_SKL_LASTBRANCH_TOS 0x000001c9
> #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680
> #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0
> #define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0
> #define NUM_MSR_SKL_LASTBRANCH 32
>
> +/* Silvermont (and newer) last-branch recording */
> +#define MSR_SM_LBR_SELECT 0x000001c8
> +#define MSR_SM_LASTBRANCH_TOS 0x000001c9
> +
> /* Goldmont last-branch recording */
> -#define MSR_GM_LASTBRANCH_TOS 0x000001c9
> #define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680
> #define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0
> #define NUM_MSR_GM_LASTBRANCH_FROM_TO 32
> --
> 2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-04-25 1:08 UTC | newest]
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2021-04-15 10:04 [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Igor Druzhinin
2021-04-15 10:04 ` [PATCH v5 2/2] x86/intel: insert Ice Lake-SP and Ice Lake-D model numbers Igor Druzhinin
2021-04-25 1:07 ` Tian, Kevin
2021-04-15 11:50 ` [PATCH v5 1/2] x86/vtx: add LBR_SELECT to the list of LBR MSRs Jan Beulich
2021-04-25 1:07 ` Tian, Kevin
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