* [PATCH v2 1/7] travis.yml: Rework the x86 64-bit tests
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 7:22 ` [PATCH v2 2/7] travis.yml: Refresh the x86 32-bit test list Thomas Huth
` (6 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
We currently have three test jobs here:
1) gcc, in-tree build
2) gcc, out-of-tree build
3) clang, in-tree build
Keeping everything in perspective, it should be sufficient to only use two
build jobs for this, one in-tree with one compiler, and one out-of-tree
with the other compiler.
So let's re-order the jobs accordingly now. And while we're at it, make
sure that all additional tests that work with the newer QEMU from Ubuntu
Focal now are tested, too, and that we check all possible tests with
Clang.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
.travis.yml | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index ef3cc40..0feaec1 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -12,30 +12,30 @@ jobs:
env:
- CONFIG=""
- BUILD_DIR="."
- - TESTS="access asyncpf debug emulator ept hypercall hyperv_stimer
- hyperv_synic idt_test intel_iommu ioapic ioapic-split
- kvmclock_test msr pcid rdpru realmode rmap_chain s3 setjmp umip"
+ - TESTS="access asyncpf debug emulator ept hypercall hyperv_clock
+ hyperv_connections hyperv_stimer hyperv_synic idt_test intel_iommu
+ ioapic ioapic-split kvmclock_test memory msr pcid pcid-disabled
+ rdpru realmode rmap_chain s3 setjmp sieve smap smptest smptest3
+ syscall tsc tsc_adjust tsx-ctrl umip vmexit_cpuid vmexit_inl_pmtimer
+ vmexit_ipi vmexit_ipi_halt vmexit_mov_from_cr8 vmexit_mov_to_cr8
+ vmexit_ple_round_robin vmexit_tscdeadline vmexit_tscdeadline_immed
+ vmexit_vmcall vmx_apic_passthrough_thread xsave"
- ACCEL="kvm"
- addons:
apt_packages: clang-10 qemu-system-x86
+ compiler: clang
env:
- CONFIG="--cc=clang-10"
- - BUILD_DIR="."
- - TESTS="access asyncpf debug emulator ept hypercall hyperv_stimer
- hyperv_synic idt_test intel_iommu ioapic ioapic-split
- kvmclock_test msr pcid rdpru realmode rmap_chain s3 setjmp umip"
- - ACCEL="kvm"
-
- - addons:
- apt_packages: gcc qemu-system-x86
- env:
- - CONFIG=""
- BUILD_DIR="x86-builddir"
- - TESTS="smptest smptest3 tsc tsc_adjust xsave vmexit_cpuid vmexit_vmcall
- sieve vmexit_inl_pmtimer vmexit_ipi_halt vmexit_mov_from_cr8
- vmexit_mov_to_cr8 vmexit_ple_round_robin vmexit_tscdeadline
- vmexit_tscdeadline_immed vmx_apic_passthrough_thread syscall"
+ - TESTS="access asyncpf debug emulator ept hypercall hyperv_clock
+ hyperv_connections hyperv_stimer hyperv_synic idt_test intel_iommu
+ ioapic ioapic-split kvmclock_test memory msr pcid pcid-disabled
+ rdpru realmode rmap_chain s3 setjmp sieve smap smptest smptest3
+ syscall tsc tsc_adjust tsx-ctrl umip vmexit_cpuid vmexit_inl_pmtimer
+ vmexit_ipi vmexit_ipi_halt vmexit_mov_from_cr8 vmexit_mov_to_cr8
+ vmexit_ple_round_robin vmexit_tscdeadline vmexit_tscdeadline_immed
+ vmexit_vmcall vmx_apic_passthrough_thread xsave"
- ACCEL="kvm"
- addons:
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 2/7] travis.yml: Refresh the x86 32-bit test list
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
2020-10-01 7:22 ` [PATCH v2 1/7] travis.yml: Rework the x86 64-bit tests Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 7:22 ` [PATCH v2 3/7] travis.yml: Add the selftest-setup ppc64 test Thomas Huth
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
With the new QEMU from Ubuntu Focal, we can now run additional
tests that were failing before.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
.travis.yml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 0feaec1..5cd6dbf 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -43,8 +43,8 @@ jobs:
env:
- CONFIG="--arch=i386"
- BUILD_DIR="."
- - TESTS="asyncpf hyperv_stimer hyperv_synic kvmclock_test msr pmu realmode
- s3 sieve smap smptest smptest3 taskswitch taskswitch2 tsc_adjust"
+ - TESTS="asyncpf kvmclock_test msr pmu realmode s3 setjmp sieve smap
+ smptest smptest3 taskswitch taskswitch2 tsc tsc_adjust tsx-ctrl umip"
- ACCEL="kvm"
- addons:
@@ -52,9 +52,9 @@ jobs:
env:
- CONFIG="--arch=i386"
- BUILD_DIR="i386-builddir"
- - TESTS="cmpxchg8b tsx-ctrl umip vmexit_cpuid vmexit_ipi vmexit_ipi_halt
- vmexit_mov_from_cr8 vmexit_mov_to_cr8 vmexit_ple_round_robin
- vmexit_tscdeadline vmexit_tscdeadline_immed vmexit_vmcall setjmp"
+ - TESTS="cmpxchg8b vmexit_vmcall vmexit_cpuid vmexit_ipi vmexit_ipi_halt
+ vmexit_mov_from_cr8 vmexit_mov_to_cr8 vmexit_ple_round_robin
+ vmexit_inl_pmtimer vmexit_tscdeadline vmexit_tscdeadline_immed"
- ACCEL="kvm"
- addons:
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 3/7] travis.yml: Add the selftest-setup ppc64 test
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
2020-10-01 7:22 ` [PATCH v2 1/7] travis.yml: Rework the x86 64-bit tests Thomas Huth
2020-10-01 7:22 ` [PATCH v2 2/7] travis.yml: Refresh the x86 32-bit test list Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 7:22 ` [PATCH v2 4/7] kbuild: fix asm-offset generation to work with clang Thomas Huth
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
This test now seems to be working with the newer version of QEMU in
Ubuntu Focal, so we can run it now in the Travis builds, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
.travis.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
index 5cd6dbf..547d8d7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -90,7 +90,7 @@ jobs:
env:
- CONFIG="--arch=ppc64 --endian=little --cross-prefix=powerpc64le-linux-gnu-"
- BUILD_DIR="."
- - TESTS="spapr_hcall emulator rtas-set-time-of-day"
+ - TESTS="selftest-setup spapr_hcall emulator rtas-set-time-of-day"
- ACCEL="tcg,cap-htm=off"
- addons:
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 4/7] kbuild: fix asm-offset generation to work with clang
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
` (2 preceding siblings ...)
2020-10-01 7:22 ` [PATCH v2 3/7] travis.yml: Add the selftest-setup ppc64 test Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 9:12 ` Andrew Jones
2020-10-01 7:22 ` [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang Thomas Huth
` (3 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
KBuild abuses the asm statement to write to a file and
clang chokes about these invalid asm statements. Hack it
even more by fooling this is actual valid asm code.
This is an adaption of the Linux kernel commit cf0c3e68aa81f992b0
which in turn is based on a patch for the U-Boot:
http://patchwork.ozlabs.org/patch/375026/
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
lib/kbuild.h | 6 +++---
scripts/asm-offsets.mak | 5 +++--
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/lib/kbuild.h b/lib/kbuild.h
index ab99db6..79644e5 100644
--- a/lib/kbuild.h
+++ b/lib/kbuild.h
@@ -1,8 +1,8 @@
#ifndef _KBUILD_H_
#define _KBUILD_H_
#define DEFINE(sym, val) \
- asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+ asm volatile("\n.ascii \"->" #sym " %0 " #val "\"" : : "i" (val))
#define OFFSET(sym, str, mem) DEFINE(sym, offsetof(struct str, mem))
-#define COMMENT(x) asm volatile("\n->#" x)
-#define BLANK() asm volatile("\n->" : : )
+#define COMMENT(x) asm volatile("\n.ascii \"->#" x "\"")
+#define BLANK() asm volatile("\n.ascii \"->\"" : : )
#endif
diff --git a/scripts/asm-offsets.mak b/scripts/asm-offsets.mak
index b35da09..7b64162 100644
--- a/scripts/asm-offsets.mak
+++ b/scripts/asm-offsets.mak
@@ -8,10 +8,11 @@
#
define sed-y
- "/^->/{s:->#\(.*\):/* \1 */:; \
+ 's:^[[:space:]]*\.ascii[[:space:]]*"\(.*\)".*:\1:; \
+ /^->/{s:->#\(.*\):/* \1 */:; \
s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
- s:->::; p;}"
+ s:->::; p;}'
endef
define make_asm_offsets
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
` (3 preceding siblings ...)
2020-10-01 7:22 ` [PATCH v2 4/7] kbuild: fix asm-offset generation to work with clang Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 9:12 ` Andrew Jones
2020-10-01 7:22 ` [PATCH v2 6/7] lib/arm64/spinlock: " Thomas Huth
` (2 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
Clang complains here:
arm/pmu.c:201:16: error: value size does not match register size specified by
the constraint and modifier [-Werror,-Wasm-operand-widths]
: [pmcr] "r" (pmcr)
^
arm/pmu.c:194:18: note: use constraint modifier "w"
" msr pmcr_el0, %[pmcr]\n"
^~~~~~~
%w[pmcr]
arm/pmu.c:200:17: error: value size does not match register size specified by
the constraint and modifier [-Werror,-Wasm-operand-widths]
: [loop] "+r" (loop)
^
arm/pmu.c:196:11: note: use constraint modifier "w"
"1: subs %[loop], %[loop], #1\n"
^~~~~~~
%w[loop]
arm/pmu.c:200:17: error: value size does not match register size specified by
the constraint and modifier [-Werror,-Wasm-operand-widths]
: [loop] "+r" (loop)
^
arm/pmu.c:196:20: note: use constraint modifier "w"
"1: subs %[loop], %[loop], #1\n"
^~~~~~~
%w[loop]
arm/pmu.c:284:35: error: value size does not match register size specified
by the constraint and modifier [-Werror,-Wasm-operand-widths]
: [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
^
arm/pmu.c:274:28: note: use constraint modifier "w"
" msr pmcr_el0, %[pmcr]\n"
^~~~~~~
%w[pmcr]
arm/pmu.c:284:54: error: value size does not match register size specified
by the constraint and modifier [-Werror,-Wasm-operand-widths]
: [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
^
arm/pmu.c:276:23: note: use constraint modifier "w"
" mov x10, %[loop]\n"
^~~~~~~
%w[loop]
pmcr should be 64-bit since it is a sysreg, but for loop we can use the
"w" modifier.
Suggested-by: Drew Jones <drjones@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
arm/pmu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arm/pmu.c b/arm/pmu.c
index cece53e..831fb66 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -190,15 +190,16 @@ static inline uint8_t get_pmu_version(void)
*/
static inline void precise_instrs_loop(int loop, uint32_t pmcr)
{
+ uint64_t pmcr64 = pmcr;
asm volatile(
" msr pmcr_el0, %[pmcr]\n"
" isb\n"
- "1: subs %[loop], %[loop], #1\n"
+ "1: subs %w[loop], %w[loop], #1\n"
" b.gt 1b\n"
" msr pmcr_el0, xzr\n"
" isb\n"
: [loop] "+r" (loop)
- : [pmcr] "r" (pmcr)
+ : [pmcr] "r" (pmcr64)
: "cc");
}
@@ -268,8 +269,9 @@ static void test_event_introspection(void)
* pmccntr read after this function returns the exact instructions executed
* in the controlled block. Loads @loop times the data at @address into x9.
*/
-static void mem_access_loop(void *addr, int loop, uint32_t pmcr)
+static void mem_access_loop(void *addr, long loop, uint32_t pmcr)
{
+ uint64_t pmcr64 = pmcr;
asm volatile(
" msr pmcr_el0, %[pmcr]\n"
" isb\n"
@@ -281,7 +283,7 @@ asm volatile(
" msr pmcr_el0, xzr\n"
" isb\n"
:
- : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
+ : [addr] "r" (addr), [pmcr] "r" (pmcr64), [loop] "r" (loop)
: "x9", "x10", "cc");
}
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang
2020-10-01 7:22 ` [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang Thomas Huth
@ 2020-10-01 9:12 ` Andrew Jones
2020-10-01 9:14 ` Andrew Jones
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Jones @ 2020-10-01 9:12 UTC (permalink / raw)
To: Thomas Huth; +Cc: kvm, pbonzini, lvivier
On Thu, Oct 01, 2020 at 09:22:32AM +0200, Thomas Huth wrote:
> Clang complains here:
>
> arm/pmu.c:201:16: error: value size does not match register size specified by
> the constraint and modifier [-Werror,-Wasm-operand-widths]
> : [pmcr] "r" (pmcr)
> ^
> arm/pmu.c:194:18: note: use constraint modifier "w"
> " msr pmcr_el0, %[pmcr]\n"
> ^~~~~~~
> %w[pmcr]
> arm/pmu.c:200:17: error: value size does not match register size specified by
> the constraint and modifier [-Werror,-Wasm-operand-widths]
> : [loop] "+r" (loop)
> ^
> arm/pmu.c:196:11: note: use constraint modifier "w"
> "1: subs %[loop], %[loop], #1\n"
> ^~~~~~~
> %w[loop]
> arm/pmu.c:200:17: error: value size does not match register size specified by
> the constraint and modifier [-Werror,-Wasm-operand-widths]
> : [loop] "+r" (loop)
> ^
> arm/pmu.c:196:20: note: use constraint modifier "w"
> "1: subs %[loop], %[loop], #1\n"
> ^~~~~~~
> %w[loop]
> arm/pmu.c:284:35: error: value size does not match register size specified
> by the constraint and modifier [-Werror,-Wasm-operand-widths]
> : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
> ^
> arm/pmu.c:274:28: note: use constraint modifier "w"
> " msr pmcr_el0, %[pmcr]\n"
> ^~~~~~~
> %w[pmcr]
> arm/pmu.c:284:54: error: value size does not match register size specified
> by the constraint and modifier [-Werror,-Wasm-operand-widths]
> : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
> ^
> arm/pmu.c:276:23: note: use constraint modifier "w"
> " mov x10, %[loop]\n"
> ^~~~~~~
> %w[loop]
>
> pmcr should be 64-bit since it is a sysreg, but for loop we can use the
> "w" modifier.
>
> Suggested-by: Drew Jones <drjones@redhat.com>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> arm/pmu.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Tested-by: Andrew Jones <drjones@redhat.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang
2020-10-01 9:12 ` Andrew Jones
@ 2020-10-01 9:14 ` Andrew Jones
2020-10-01 10:50 ` Thomas Huth
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Jones @ 2020-10-01 9:14 UTC (permalink / raw)
To: Thomas Huth; +Cc: kvm, pbonzini, lvivier
On Thu, Oct 01, 2020 at 11:12:43AM +0200, Andrew Jones wrote:
> On Thu, Oct 01, 2020 at 09:22:32AM +0200, Thomas Huth wrote:
> > Clang complains here:
> >
> > arm/pmu.c:201:16: error: value size does not match register size specified by
> > the constraint and modifier [-Werror,-Wasm-operand-widths]
> > : [pmcr] "r" (pmcr)
> > ^
> > arm/pmu.c:194:18: note: use constraint modifier "w"
> > " msr pmcr_el0, %[pmcr]\n"
> > ^~~~~~~
> > %w[pmcr]
> > arm/pmu.c:200:17: error: value size does not match register size specified by
> > the constraint and modifier [-Werror,-Wasm-operand-widths]
> > : [loop] "+r" (loop)
> > ^
> > arm/pmu.c:196:11: note: use constraint modifier "w"
> > "1: subs %[loop], %[loop], #1\n"
> > ^~~~~~~
> > %w[loop]
> > arm/pmu.c:200:17: error: value size does not match register size specified by
> > the constraint and modifier [-Werror,-Wasm-operand-widths]
> > : [loop] "+r" (loop)
> > ^
> > arm/pmu.c:196:20: note: use constraint modifier "w"
> > "1: subs %[loop], %[loop], #1\n"
> > ^~~~~~~
> > %w[loop]
> > arm/pmu.c:284:35: error: value size does not match register size specified
> > by the constraint and modifier [-Werror,-Wasm-operand-widths]
> > : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
> > ^
> > arm/pmu.c:274:28: note: use constraint modifier "w"
> > " msr pmcr_el0, %[pmcr]\n"
> > ^~~~~~~
> > %w[pmcr]
> > arm/pmu.c:284:54: error: value size does not match register size specified
> > by the constraint and modifier [-Werror,-Wasm-operand-widths]
> > : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
> > ^
> > arm/pmu.c:276:23: note: use constraint modifier "w"
> > " mov x10, %[loop]\n"
> > ^~~~~~~
> > %w[loop]
> >
> > pmcr should be 64-bit since it is a sysreg, but for loop we can use the
> > "w" modifier.
> >
> > Suggested-by: Drew Jones <drjones@redhat.com>
Not a huge deal, but I use my official first name 'Andrew' on my tags.
I know, I like confusing people by flipping back and forth between
Andrew and Drew...
Thanks,
drew a.k.a Andrew
> > Signed-off-by: Thomas Huth <thuth@redhat.com>
> > ---
> > arm/pmu.c | 10 ++++++----
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Tested-by: Andrew Jones <drjones@redhat.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang
2020-10-01 9:14 ` Andrew Jones
@ 2020-10-01 10:50 ` Thomas Huth
2020-10-01 12:02 ` Andrew Jones
0 siblings, 1 reply; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 10:50 UTC (permalink / raw)
To: Andrew Jones; +Cc: kvm, pbonzini, lvivier
On 01/10/2020 11.14, Andrew Jones wrote:
> On Thu, Oct 01, 2020 at 11:12:43AM +0200, Andrew Jones wrote:
>> On Thu, Oct 01, 2020 at 09:22:32AM +0200, Thomas Huth wrote:
>>> Clang complains here:
>>>
>>> arm/pmu.c:201:16: error: value size does not match register size specified by
>>> the constraint and modifier [-Werror,-Wasm-operand-widths]
>>> : [pmcr] "r" (pmcr)
>>> ^
>>> arm/pmu.c:194:18: note: use constraint modifier "w"
>>> " msr pmcr_el0, %[pmcr]\n"
>>> ^~~~~~~
>>> %w[pmcr]
>>> arm/pmu.c:200:17: error: value size does not match register size specified by
>>> the constraint and modifier [-Werror,-Wasm-operand-widths]
>>> : [loop] "+r" (loop)
>>> ^
>>> arm/pmu.c:196:11: note: use constraint modifier "w"
>>> "1: subs %[loop], %[loop], #1\n"
>>> ^~~~~~~
>>> %w[loop]
>>> arm/pmu.c:200:17: error: value size does not match register size specified by
>>> the constraint and modifier [-Werror,-Wasm-operand-widths]
>>> : [loop] "+r" (loop)
>>> ^
>>> arm/pmu.c:196:20: note: use constraint modifier "w"
>>> "1: subs %[loop], %[loop], #1\n"
>>> ^~~~~~~
>>> %w[loop]
>>> arm/pmu.c:284:35: error: value size does not match register size specified
>>> by the constraint and modifier [-Werror,-Wasm-operand-widths]
>>> : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
>>> ^
>>> arm/pmu.c:274:28: note: use constraint modifier "w"
>>> " msr pmcr_el0, %[pmcr]\n"
>>> ^~~~~~~
>>> %w[pmcr]
>>> arm/pmu.c:284:54: error: value size does not match register size specified
>>> by the constraint and modifier [-Werror,-Wasm-operand-widths]
>>> : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
>>> ^
>>> arm/pmu.c:276:23: note: use constraint modifier "w"
>>> " mov x10, %[loop]\n"
>>> ^~~~~~~
>>> %w[loop]
>>>
>>> pmcr should be 64-bit since it is a sysreg, but for loop we can use the
>>> "w" modifier.
>>>
>>> Suggested-by: Drew Jones <drjones@redhat.com>
>
> Not a huge deal, but I use my official first name 'Andrew' on my tags.
> I know, I like confusing people by flipping back and forth between
> Andrew and Drew...
Sorry, IIRC I simply copy-n-pasted your name and e-mail address from the
MAINTAINERS file ... maybe you should fix it there to avoid such situations?
Thomas
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang
2020-10-01 10:50 ` Thomas Huth
@ 2020-10-01 12:02 ` Andrew Jones
0 siblings, 0 replies; 15+ messages in thread
From: Andrew Jones @ 2020-10-01 12:02 UTC (permalink / raw)
To: Thomas Huth; +Cc: kvm, pbonzini, lvivier
On Thu, Oct 01, 2020 at 12:50:48PM +0200, Thomas Huth wrote:
> On 01/10/2020 11.14, Andrew Jones wrote:
> > On Thu, Oct 01, 2020 at 11:12:43AM +0200, Andrew Jones wrote:
> >> On Thu, Oct 01, 2020 at 09:22:32AM +0200, Thomas Huth wrote:
> >>> Clang complains here:
> >>>
> >>> arm/pmu.c:201:16: error: value size does not match register size specified by
> >>> the constraint and modifier [-Werror,-Wasm-operand-widths]
> >>> : [pmcr] "r" (pmcr)
> >>> ^
> >>> arm/pmu.c:194:18: note: use constraint modifier "w"
> >>> " msr pmcr_el0, %[pmcr]\n"
> >>> ^~~~~~~
> >>> %w[pmcr]
> >>> arm/pmu.c:200:17: error: value size does not match register size specified by
> >>> the constraint and modifier [-Werror,-Wasm-operand-widths]
> >>> : [loop] "+r" (loop)
> >>> ^
> >>> arm/pmu.c:196:11: note: use constraint modifier "w"
> >>> "1: subs %[loop], %[loop], #1\n"
> >>> ^~~~~~~
> >>> %w[loop]
> >>> arm/pmu.c:200:17: error: value size does not match register size specified by
> >>> the constraint and modifier [-Werror,-Wasm-operand-widths]
> >>> : [loop] "+r" (loop)
> >>> ^
> >>> arm/pmu.c:196:20: note: use constraint modifier "w"
> >>> "1: subs %[loop], %[loop], #1\n"
> >>> ^~~~~~~
> >>> %w[loop]
> >>> arm/pmu.c:284:35: error: value size does not match register size specified
> >>> by the constraint and modifier [-Werror,-Wasm-operand-widths]
> >>> : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
> >>> ^
> >>> arm/pmu.c:274:28: note: use constraint modifier "w"
> >>> " msr pmcr_el0, %[pmcr]\n"
> >>> ^~~~~~~
> >>> %w[pmcr]
> >>> arm/pmu.c:284:54: error: value size does not match register size specified
> >>> by the constraint and modifier [-Werror,-Wasm-operand-widths]
> >>> : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop)
> >>> ^
> >>> arm/pmu.c:276:23: note: use constraint modifier "w"
> >>> " mov x10, %[loop]\n"
> >>> ^~~~~~~
> >>> %w[loop]
> >>>
> >>> pmcr should be 64-bit since it is a sysreg, but for loop we can use the
> >>> "w" modifier.
> >>>
> >>> Suggested-by: Drew Jones <drjones@redhat.com>
> >
> > Not a huge deal, but I use my official first name 'Andrew' on my tags.
> > I know, I like confusing people by flipping back and forth between
> > Andrew and Drew...
>
> Sorry, IIRC I simply copy-n-pasted your name and e-mail address from the
> MAINTAINERS file ... maybe you should fix it there to avoid such situations?
>
Thanks for pointing that out. Patch sent.
drew
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 6/7] lib/arm64/spinlock: Fix inline assembly for Clang
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
` (4 preceding siblings ...)
2020-10-01 7:22 ` [PATCH v2 5/7] arm/pmu: Fix inline assembly for Clang Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 9:12 ` Andrew Jones
2020-10-01 7:22 ` [PATCH v2 7/7] travis.yml: Rework the aarch64 jobs Thomas Huth
2020-10-01 9:18 ` [PATCH v2 0/7] Update travis CI Paolo Bonzini
7 siblings, 1 reply; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
/home/travis/build/huth/kvm-unit-tests/lib/arm64/spinlock.c:29:12: error:
value size does not match register size specified by the constraint and
modifier [-Werror,-Wasm-operand-widths]
: "=&r" (val), "=&r" (fail)
^
/home/travis/build/huth/kvm-unit-tests/lib/arm64/spinlock.c:27:9: note: use
constraint modifier "w"
" mov %0, #1\n"
^~
%w0
Use the "w" modifier as suggested to fix the issue.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
lib/arm64/spinlock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/arm64/spinlock.c b/lib/arm64/spinlock.c
index fac4fc9..258303d 100644
--- a/lib/arm64/spinlock.c
+++ b/lib/arm64/spinlock.c
@@ -24,7 +24,7 @@ void spin_lock(struct spinlock *lock)
asm volatile(
"1: ldaxr %w0, [%2]\n"
" cbnz %w0, 1b\n"
- " mov %0, #1\n"
+ " mov %w0, #1\n"
" stxr %w1, %w0, [%2]\n"
: "=&r" (val), "=&r" (fail)
: "r" (&lock->v)
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 6/7] lib/arm64/spinlock: Fix inline assembly for Clang
2020-10-01 7:22 ` [PATCH v2 6/7] lib/arm64/spinlock: " Thomas Huth
@ 2020-10-01 9:12 ` Andrew Jones
0 siblings, 0 replies; 15+ messages in thread
From: Andrew Jones @ 2020-10-01 9:12 UTC (permalink / raw)
To: Thomas Huth; +Cc: kvm, pbonzini, lvivier
On Thu, Oct 01, 2020 at 09:22:33AM +0200, Thomas Huth wrote:
> /home/travis/build/huth/kvm-unit-tests/lib/arm64/spinlock.c:29:12: error:
> value size does not match register size specified by the constraint and
> modifier [-Werror,-Wasm-operand-widths]
> : "=&r" (val), "=&r" (fail)
> ^
> /home/travis/build/huth/kvm-unit-tests/lib/arm64/spinlock.c:27:9: note: use
> constraint modifier "w"
> " mov %0, #1\n"
> ^~
> %w0
>
> Use the "w" modifier as suggested to fix the issue.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> lib/arm64/spinlock.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/arm64/spinlock.c b/lib/arm64/spinlock.c
> index fac4fc9..258303d 100644
> --- a/lib/arm64/spinlock.c
> +++ b/lib/arm64/spinlock.c
> @@ -24,7 +24,7 @@ void spin_lock(struct spinlock *lock)
> asm volatile(
> "1: ldaxr %w0, [%2]\n"
> " cbnz %w0, 1b\n"
> - " mov %0, #1\n"
> + " mov %w0, #1\n"
> " stxr %w1, %w0, [%2]\n"
> : "=&r" (val), "=&r" (fail)
> : "r" (&lock->v)
> --
> 2.18.2
>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Tested-by: Andrew Jones <drjones@redhat.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 7/7] travis.yml: Rework the aarch64 jobs
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
` (5 preceding siblings ...)
2020-10-01 7:22 ` [PATCH v2 6/7] lib/arm64/spinlock: " Thomas Huth
@ 2020-10-01 7:22 ` Thomas Huth
2020-10-01 9:18 ` [PATCH v2 0/7] Update travis CI Paolo Bonzini
7 siblings, 0 replies; 15+ messages in thread
From: Thomas Huth @ 2020-10-01 7:22 UTC (permalink / raw)
To: kvm; +Cc: pbonzini, drjones, lvivier
With the new QEMU from Ubuntu Focal, we can now run some more tests
with TCG. Also switch the second build job to native arm64, so we
can use Clang to compile these tests to get some additional compiler
test coverage.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
.travis.yml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 547d8d7..5af7344 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -76,14 +76,21 @@ jobs:
env:
- CONFIG="--arch=arm64 --cross-prefix=aarch64-linux-gnu-"
- BUILD_DIR="."
- - TESTS="selftest-vectors-kernel selftest-vectors-user selftest-smp"
+ - TESTS="cache gicv2-active gicv2-ipi gicv3-active gicv3-ipi pci-test
+ pmu-cycle-counter pmu-event-counter-config pmu-sw-incr psci
+ selftest-setup selftest-smp selftest-vectors-kernel
+ selftest-vectors-user timer"
- - addons:
- apt_packages: gcc-aarch64-linux-gnu qemu-system-aarch64
+ - arch: arm64
+ addons:
+ apt_packages: clang-10 qemu-system-aarch64
+ compiler: clang
env:
- - CONFIG="--arch=arm64 --cross-prefix=aarch64-linux-gnu-"
+ - CONFIG="--arch=arm64 --cc=clang-10"
- BUILD_DIR="arm64-buildir"
- - TESTS="pci-test pmu gicv2-active gicv3-active psci timer selftest-setup"
+ - TESTS="cache gicv2-active gicv2-ipi gicv3-active gicv3-ipi pci-test
+ pmu-cycle-counter pmu-event-counter-config pmu-sw-incr selftest-setup
+ selftest-smp selftest-vectors-kernel selftest-vectors-user timer"
- addons:
apt_packages: gcc-powerpc64le-linux-gnu qemu-system-ppc
--
2.18.2
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 0/7] Update travis CI
2020-10-01 7:22 [PATCH v2 0/7] Update travis CI Thomas Huth
` (6 preceding siblings ...)
2020-10-01 7:22 ` [PATCH v2 7/7] travis.yml: Rework the aarch64 jobs Thomas Huth
@ 2020-10-01 9:18 ` Paolo Bonzini
7 siblings, 0 replies; 15+ messages in thread
From: Paolo Bonzini @ 2020-10-01 9:18 UTC (permalink / raw)
To: Thomas Huth, kvm; +Cc: drjones, lvivier
On 01/10/20 09:22, Thomas Huth wrote:
> Travis now features Ubuntu Focal containers, so we can update our
> kvm-unit-tests CI to use it for getting a newer version of QEMU and
> the compilers. Thanks to this QEMU update, we can now run more tests
> with TCG here.
>
> Additionally, this series switches the second aarch64 build job to
> use the native builder - this way we can use the Clang compiler
> there to get some additional test coverage. This indeed already helped
> to discover some bogus register constraints in the aarch64 code.
> (ppc64 and s390x are not using the native builders yet since there are
> still some issues with Clang there that I haven't quite figured out ...
> that's maybe something for later)
>
> v2:
> - The patch that changed "bionic" into "focal" and the s390x patch
> are already merged, so they are not included here anymore
> - Fixed rebase conflicts in the x86 patches
> - Dropped the hyperv tests from the 32-bit builds (they are going
> to be marked as 64-bit only)
>
> Thomas Huth (7):
> travis.yml: Rework the x86 64-bit tests
> travis.yml: Refresh the x86 32-bit test list
> travis.yml: Add the selftest-setup ppc64 test
> kbuild: fix asm-offset generation to work with clang
> arm/pmu: Fix inline assembly for Clang
> lib/arm64/spinlock: Fix inline assembly for Clang
> travis.yml: Rework the aarch64 jobs
>
> .travis.yml | 63 +++++++++++++++++++++++------------------
> arm/pmu.c | 10 ++++---
> lib/arm64/spinlock.c | 2 +-
> lib/kbuild.h | 6 ++--
> scripts/asm-offsets.mak | 5 ++--
> 5 files changed, 48 insertions(+), 38 deletions(-)
>
Queued, thanks.
Paolo
^ permalink raw reply [flat|nested] 15+ messages in thread