Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA

[Richard Henderson <rth@twiddle.net>]

On 05/13/2015 02:21 PM, Maciej W. Rozycki wrote:
> On Wed, 13 May 2015, Leon Alrae wrote:
> 
>>> Certainly we do.  It's all in softmmu_template.h.
>>
>> I believe the problem is that MSA vector register's size is 16-bytes
>> (this DATA_SIZE isn't supported in softmmu_template) and MSA load/store
>> is supposed to be atomic.
> 
>  Not really AFAICT.  Here's what the specification says[1]:
> 
> "The vector load instruction is atomic at the element level with no 
> guaranteed ordering among elements, i.e. each element load is an atomic 
> operation issued in no particular order with respect to the element's 
> vector position."
> 
> and[2]:
> 
> "The vector store instruction is atomic at the element level with no 
> guaranteed ordering among elements, i.e. each element store is an atomic 
> operation issued in no particular order with respect to the element's 
> vector position."
> 
> so you only need to get atomic up to 8 bytes (with LD.D and ST.D, less 
> with the narrower vector elements), and that looks supported to me.

There's "atomic" in the transactional sense, and then there's "atomic" in the
visibility to other actors on the bus sense.

Presumably Leon is talking about the first, wherein we must ensure all writes
to both pages must succeed.  Which just means making sure that both pages are
present and writable before modifying any memory.

This patch set *is* doing too much work for loads, since the loads can simply
be issued, and the result written back to the register at the end after all
have succeeded.


r~