Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA

[Yongbok Kim <yongbok.kim@imgtec.com>]

On 14/05/2015 10:00, Yongbok Kim wrote:
> On 13/05/2015 20:28, Richard Henderson wrote:
>> On 05/13/2015 08:37 AM, Yongbok Kim wrote:
>>> +static inline void ensure_atomic_msa_block_access(CPUMIPSState *env,
>>> +                                                  target_ulong addr,
>>> +                                                  int rw,
>>> +                                                  int mmu_idx)
>>>  {
>>> +#if !defined(CONFIG_USER_ONLY)
>>> +#define MSA_PAGESPAN(x) (unlikely((((x) & ~TARGET_PAGE_MASK)                \
>>> +                                   + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE))
>>> +    CPUState *cs = CPU(mips_env_get_cpu(env));
>>> +    target_ulong page_addr;
>>>  
>>> +    if (MSA_PAGESPAN(addr)) {
>>> +        /* first page */
>>> +        tlb_fill(cs, addr, rw, mmu_idx, 0);
>>> +        /* second page */
>>> +        page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
>>> +        tlb_fill(cs, page_addr, rw, mmu_idx, 0);
>>>      }
>>> +#endif
>>>  }
>> This doesn't do quite what you think it does.  It does trap if the page isn't
>> mapped at all, but it doesn't trap if e.g. rw is set and the page is read-only.
>> That requires a subsequent check for what permissions were installed by
>> tlb_set_page.
> I must double check the behaviour but please note that here we are filling qemu's tlb entries
> according to target's tlb entries. Therefore permission issue would be cleared.
> I agree with your comment from later email that for the load this is too much as all load can
> be issued and storing into the vector register can be followed.
> I wasn't sure that because this tlb filling is happening only if an access is crossing the page boundary.
>
>
In addition to that, if we issue all the loads let say only the first page is
accessible, in the architectural point of view it would be fine as nothing will
be stored in the vector register but accessing the first page is "visible" from
the data bus.
Do you think this wouldn't cause any problem?
It might be just implementation dependent though.

Regards,
Yongbok