Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA

From: Leon Alrae <leon.alrae@imgtec.com>
To: Richard Henderson <rth@twiddle.net>,
	Yongbok Kim <yongbok.kim@imgtec.com>,
	qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	afaerber@suse.de, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA
Date: Fri, 15 May 2015 15:04:40 +0100	[thread overview]
Message-ID: <5555FCF8.7030903@imgtec.com> (raw)
In-Reply-To: <5555F7F7.3020401@twiddle.net>

On 15/05/2015 14:43, Richard Henderson wrote:
> On 05/15/2015 05:09 AM, Leon Alrae wrote:
>> On 14/05/2015 20:12, Richard Henderson wrote:
>>>   /* We know both pages are present and writable.  */
>>>   if (eaddr == baddr + 15) {
>>>       /* Consecutive pages in RAM.  */
>>>       memcpy(baddr, register, 16);
>>>   } else {
>>>       /* Someone's doing an MSA store to device memory.  */
>>>       for (i = 0; i < 2; ++i) {
>>>           helper_ret_stq_mmu(env, vaddr + i*8, register.d[0],
>>>                              make_memop_idx(MO_UNALN | MO_TEQ, mmu_idx),
>>>                              GETRA());
>>>       }
>>>   }
>>
>> We would additionally need to take care of vector elements' endianness
>> before using this code. Therefore always using helper_ret_st[bwlq]_mmu
>> (depending on data format) in a loop probably is simpler.
> 
> I suppose.  I'd thought one of the patches defined functions to do the
> swapping, so I assumed that would still be used.

IIUC they were required because of the byte access workaround, but now
with the MO_UNALN support in TCG (thanks for this!) neither the
workaround nor the swapping is needed for MSA I think.

Leon